CN1816030A - Method and apparatus for estimating and compensating frequency deviation in orthogonal multiplexing system - Google Patents

Abstract

The method includes steps: using mapping table lookup to simplify former a series of calculation of trigonometric function, and considering range of rotation phases in [0: + Pi]; when making phase compensation for OFDM symbol, adjusting sign digit if rotation phase in third, fourth quadrants; based on precision required by practical application, linear unbiased partitioning whole range of phase; based on equant size to determine magnitude of compensation factor list. The device includes frame synchronizer, frequency deviation estimator of carrier wave, unit for eliminating CP, unit of compensation factor list, and frequency deviation compensator of carrier wave. Using values of rotation phases calculated for each frame looks up list to obtain corresponding compensation factor. Using scheme of mapping table lookup, the invention solves disadvantages in maximum likelihood estimation method, where trigonometric function cannot be implemented in FPGA.

Description

The method and apparatus of estimation and compensating frequency deviation in the ofdm system

Technical field

The present invention relates to the communication technology, adopt the method and apparatus of training sequence estimation and compensating frequency deviation in particularly a kind of orthogonal FDM communication system.

Background technology

Orthogonal FDM communication system (hereinafter to be referred as OFDM: i.e. Orthogonal Frequency Division Multiplexing) is a kind of special multi-carrier modulation technology, its basic principle that transmits data is that data flow is divided into several parallel bit streams, and the data stream modulates that each is such is on single carrier wave.

One of major defect of OFDM is the sensitivity to carrier frequency shift, for multicarrier system, the skew of carrier frequency can cause producing between the subchannel to be disturbed, and has a plurality of orthogonal sub-carriers in the ofdm system, and its output signal is the stack of a plurality of sub-channel signals.For requiring subcarrier to keep the ofdm system of strict synchronism, the influence that frequency shift (FS) brought of carrier wave is more serious, if do not take measures to this ICI (Inter Channel Interference: interchannel interference) overcome, can bring very serious floor effect to systematic function, promptly increase the transmitting power of signal in any case, can not improve the performance of system significantly.

Because there is deviation in the carrier frequency of transmitting terminal and receiving terminal, each sample of signal at time t all comprises unknown phase factor e ^{J2 π Δ fci}, Vf wherein _cBe unknown carrier frequency offset. in order not destroy the orthogonality between the subcarrier, before receiving terminal carries out the FFT conversion, must estimate and compensate this unknown phase factor.

Comprise two classes in existing method about timing and frequency offset estimating: the first kind is the auxiliary estimations of data, promptly based on frequency pilot sign; Another kind of is that non-data are auxiliary, it is blind estimation, it utilizes the structure of ofdm signal, for example the Short Training of defined 10 repetitions of frame structure accords with in the 802.11.a standard, the long training symbol of 2 repetitions and the Cyclic Prefix (CP) that each OFDM symbol front is added can make full use of its good correlation properties and carry out timing and frequency offset estimating.

Existing associating timing and frequency deviation estimating method, the computational process of once using in the time of can using timing estimation when wherein estimating frequency deviation has been simplified whole Design of device.By maximum likelihood estimation device, promptly utilize two training symbols that repeat continuously to realize the estimation of frequency shift (FS), in a Juha Heiskala and John Terry " 802.11a WLAN (wireless local area network) " book, provided following derivation:

The transmission signal is s _n, passband signal y _nComplicated baseband model be

$y_n=s_n{e}^{j2\mathrm{\π}{f}_{\mathrm{tx}}n{T}_s}$

F wherein _TxFor sending carrier frequency.At receiver to carrier frequency f _TxSignal carry out after the down converted complex baseband signal r of reception _nIgnoring under the instantaneous noise situations be

$r_n=s_n{e}^{j2\mathrm{\π}{f}_{\mathrm{tx}}n{T}_s}{e}^{-j2\mathrm{\π}{f}_{\mathrm{tx}}n{T}_s}$

$=s_n{e}^{j2\mathrm{\π}{f}_{\mathrm{\Δ}}n{T}_s}$

F wherein _Δ=f _Tx-f _TxBe to send and the frequency difference of reception carrier, D is the time-delay between the identical sampling of two repetition training symbols, and L is the length of training symbol.

$z=\underset{n=0}{\overset{L-1}{\mathrm{\Σ}}}{r}_n{r}_{n+D}^{*}$

$=\underset{n=0}{\overset{L-1}{\mathrm{\Σ}}}{s}_n{e}^{j2\mathrm{\π}{f}_{\mathrm{\Δ}}n{T}_s}{\left(s_{n+D}{e}^{j2\mathrm{\π}{f}_{\mathrm{\Δ}}(n+D)T_s}\right)}^{*}$

$=\underset{n=0}{\overset{L-1}{\mathrm{\Σ}}}{s}_n{s}_{n+D}^{*}{e}^{j2\mathrm{\π}{f}_{\mathrm{\Δ}}n{T}_s}{e}^{-j2\mathrm{\π}{f}_{\mathrm{\Δ}}(n+D)T_s}$

$=e^{-j2\mathrm{\π}{f}_{\mathrm{\Δ}}D{T}_s}\underset{n=0}{\overset{L-1}{\mathrm{\Σ}}}{\left|s_n\right|}^2$

Can obtain carrier frequency offset thus $f_{\mathrm{\Δ}}=-\frac{1}{2\mathrm{\πD}{T}_s}\∠z$ Then can carry out the carrier frequency offset compensation to the OFDM symbol, suppose that each OFDM symbol is 64 points, its formula is

$\tilde{c}\left(n\right)=c\left(n\right)\exp \left[j2\mathrm{\π}\frac{f_{\mathrm{\Δ}}\mathrm{Tn}}{64}\right]$ (n＝0，1，2...，62，63)

The scope of application of this method has determined the degree that frequency shift (FS) can be estimated, this scope is directly relevant with the length of replicator, and the form of z is-2 π f _ΔDT _s, be defined in [π ,+π] scope, thereby the absolute value of frequency departure must be less than or equal to following critical value, promptly the anglec of rotation of z is littler than π

$\left|f_{\mathrm{\Δ}}\right|\≤\frac{\mathrm{\π}}{2\mathrm{\πD}{T}_s}=\frac{1}{2D{T}_s}$

The maximum frequency error that allows utilizes subcarrier spacing f usually _sCarry out normalization, as time-delay D equal symbol length, then

$\frac{1}{2D{T}_s}=\frac{1}{2}{f}_s$

Therefore frequency error is at most half of subcarrier spacing.This existing maximum likelihood is estimated device owing to need calculate carrier frequency offset by real-time related operation, and each OFDM symbol is done the respective phase compensation.For the ease of understanding, below illustrate:

Suppose z=a+bj (1)

Obtain $\∠z=\arctan \left(\frac{b}{a}\right)---\left(2\right)$

Because $f_{\mathrm{\Δ}}=-\frac{1}{2\mathrm{\πD}{T}_s}\∠z---\left(3\right)$ With $\tilde{c}\left(n\right)=c\left(n\right)\exp \left[j2\mathrm{\π}\frac{f_{\mathrm{\Δ}}\mathrm{Tn}}{64}\right]$ (n＝0，1，...，62，63) (4)

Result after also expansion can be compensated with (3) formula substitution (4) formula:

Recipient at ofdm communication system, the complex data flow that receives (comprising independently real part and imaginary data stream) is distinguished input delay auto-correlation computation device and is accorded with the auto-correlation computation device with the known training in this locality, two related operation results of output import the threshold decision device and determine time synchronized after normalization, after the frame of OFDM is synchronized to, according to existing maximum Likelihood, the real part of the delay autocorrelator output during frame synchronization and imaginary part (a and b) can be used to estimate the rotation of phase place and the deviation of further carrier frequency.

Because FPGA (Field Programmable Gate Arrays,: field programmable gate array) be based on the hardware device of extensive logical block, can be used for producing complicated user logic, but trigonometric function is (for example sinusoidal, cosine, arc tangent) in FPGA, can not directly be realized, the method that makes above-mentioned estimating carrier frequencies and compensation, real part a that has promptly obtained and empty step b input phase calculator, the complex result (need use SIN function, cosine function) that the phase value ∠ z (need use arctan function) of output rotation imports after the compensate of frequency deviation device can be compensated again can not directly be designed to a specific device that can be used on the FPGA.In order to address the above problem, need a kind of new method of design, make the device that on FPGA, can realize this method to be compared and be easy to develop, thus the estimation and the compensation of realization carrier frequency offset on hardware.

Summary of the invention

The objective of the invention is to utilize the autocorrelative result of delay (a and b) who when OFDM frame synchronization, has calculated to be rotated the estimation of phase place and to OFDM symbol compensation, the estimation with attainable carrier frequency offset on FPGA and the method and apparatus of compensation are provided.

To achieve these goals, the present invention has simplified the calculating of original a series of trigonometric function by the mapping look-up of table method, because the scope of rotatable phase is [π :+π], the cosine value of [π: 0] is the same with the cosine value of [0:+ π], be cos (θ)=cos θ, the sine value of [π: 0] is the negate of [0:+ π] sine value, promptly sin (θ)=-sin θ.So the scope of rotatable phase only need be considered [0:+ π], promptly the first, the angle of two quadrant is when doing phase compensation to the OFDM symbol, according to above-mentioned trigonometric function relational expression, regulate sign bit and work as rotatable phase the 3rd, four-quadrant is because the phase place of rotation is arbitrarily, can be according to the desired precision of practical application to the linear five equilibrium of whole phase range, i.e. m five equilibrium between [0: π], wherein m is determined by precision, m is big more, five equilibrium thin more, approximate error is also just more little, but along with the isodisperse purpose increases, corresponding correction factor table becomes big, consumed the memory resource of more FPGA inside, for example when m was 64, the phase place of linear five equilibrium was 0

..., π, and when m was 128, the phase place of linear five equilibrium was 0,

π, approximate error reduces half, but the correction factor table has increased one times; Rotatable phase is approximately immediate five equilibrium phase place arbitrarily, the characteristic of pressing trigonometric function, and the tangent value of branch phase places such as linearity is non-linear five equilibrium, can determine the size of compensating factor table according to the thickness of five equilibrium.

Carrier frequency offset provided by the present invention is estimated and the device of compensation comprises: the absolute value device, for handling conveniently, save FPGA LE (LOGIC ELEMENT) resource, the symbol of temporarily ignoring real part and imaginary data, get their absolute value, data represent with binary form, and according to their symbol, corresponding quadrant flag bit are set; Phase limitator, according to the output of absolute value device, for saving the FPGA resource, the temporary transient phase place that further limits rotation exists

Be that its tangent value is not more than 1,, exchange imaginary part and real part data, corresponding actual situation flag bit is set when imaginary data during greater than the real part data; Molecule denominator shift unit, output according to phase limitator, molecule (imaginary data) is less than denominator (real part data), the binary number of denominator move to left to highest order be not 0, the binary number of the molecule identical figure place that moves to left simultaneously, divider is sent in the high t position of the high 2t position of molecule and denominator, according to the length of the demand of back divider precision suitably being selected t, be cost (tolerable) to lose some computational accuracies like this, simplified the complexity of employed divider subsequently, to reach the effect (annotate: the use of divider can consume the LE of lot of F PGA, and increases with the increase of divisor and dividend length) of saving the FPGA resource; Divider, according to the output of molecule denominator shift unit, imaginary data obtains one and is not more than 1 merchant divided by the real part data, represents with the t bit binary data; Address mapper is determined the address of compensating factor memory according to the output of divider and corresponding quadrant flag bit and actual situation flag bit; The compensating factor memory, according to the output of mapper, promptly pairing compensating factor is read in the address of compensating factor memory.This memory stores n the sine value and the cosine value of in advance good m rotatable phase in [0: π] scope, represent (big) with the fixed binary form through suitably sending out; Phase compensator, according to the output of compensating factor memory and corresponding quadrant flag bit, to each of the OFDM symbol of input to plural phase compensation, i.e. complex operation; The compensation result reducer because compensating factor is through suitably amplification, dwindles accordingly to result's (real part and imaginary data) of phase compensator; And result memory, the output of depositing the compensation result reducer, real part and imaginary data are separately deposited.

Therefore, the present invention utilizes the mapping look-up of table scheme, has solved the shortcoming that existing maximum likelihood estimation algorithm intermediate cam function can not be realized in FPGA.

Description of drawings

Fig. 1 is the block diagram of the existing frame-synchronizing device of explanation correlation technique;

Fig. 2 is the block diagram of explanation according to carrier frequency offset estimation of the present invention and compensation arrangement;

Fig. 3 is the flow chart that the explanation carrier frequency offset is estimated and compensated.

Embodiment

Please refer to accompanying drawing 1-3, will describe the structure of the device of estimation with carrier frequency shift of the present invention and compensation in detail.In routine down explanation, both made part identical in different accompanying drawings also use identical referenced drawings label.The content that defines in the explanation only provides with helping complete understanding of the present invention.In addition, well-known function and structure are not elaborated, in order to avoid unnecessarily make the present invention fuzzy.

At first, the plural number stream (one road real part data and one tunnel imaginary data) of Fig. 1 A/D converter (A/D) output is represented (length of its median M depends on the precision and the model of analog to digital converter) with M position binary form, imports existing frame-synchronizing device.Existing frame-synchronizing device comprised delay auto-correlation device and with local known training sequence relevant apparatus.When frame synchronization then, postpone the plural number output of auto-correlation device, its real part and imaginary data are come the deviation of estimating carrier frequency as the input of apparatus of the present invention.

As shown in Figure 2, this device comprises: absolute value device 100, for handling conveniently, save LE (LOGICELEMENT) resource of FPGA, the symbol of temporarily ignoring real part and imaginary data is got their absolute value, and data are represented with binary form, and according to their symbol, corresponding quadrant flag bit is set, and for example first quartile is that 00, the second quadrant is 10, third quadrant is that 11, the four-quadrants are limited to 01; Phase limitator 111, according to the output of absolute value device, for saving the FPGA resource, the temporary transient phase place that further limits rotation exists Be that its tangent value is not more than 1,, exchange imaginary part and real part data, and corresponding actual situation flag bit is set when imaginary data during greater than the real part data, for example, when phase place exists

In the scope, the actual situation flag bit is 1, when phase place exists

In the scope, the actual situation flag bit is 0; Molecule denominator shift unit 112, output according to phase limitator, molecule (imaginary data) is less than denominator (real part data), the binary number of denominator move to left to highest order be not 0, the binary number of the molecule identical figure place that moves to left simultaneously, divider is sent in the high t position of the high 2t position of molecule and denominator, according to the length of the demand of back divider precision suitably being selected t, be cost (tolerable) to lose some computational accuracies like this, simplified the complexity of employed divider subsequently, to reach the effect (annotate: the use of divider can consume the LE of lot of F PGA, and increases with the increase of divisor and dividend length) of saving the FPGA resource; Divider 113, according to the output of molecule denominator shift unit, imaginary data obtains one and is not more than 1 merchant divided by the real part data, represents with the t bit binary data; Address mapper 114 is determined the address of compensating factor memory according to the output of divider and corresponding quadrant flag bit and actual situation flag bit; Compensating factor memory 115, according to the output of mapper, promptly pairing compensating factor is read in the address of compensating factor memory.This memory stores n the sine value and the cosine value of in advance good m rotatable phase in [0: π] scope, represent (big) with the fixed binary form through suitably sending out; Phase compensator 116, according to the output of compensating factor memory and corresponding quadrant flag bit to each of OFDM symbol to plural phase compensation, i.e. complex operation; Compensation result reducer 117 because compensating factor is through suitably amplification, dwindles accordingly to result's (real part and imaginary data) of phase compensator; And result memory 118, the output of depositing the compensation result reducer, real part and imaginary data are separately deposited.

The recipient of ofdm system, utilize existing frame-synchronizing device that the data flow that receives is carried out synchronously.Postpone the real part of auto-correlation output and the empty step data are come estimating carrier frequency as the input of apparatus of the present invention deviation during frame synchronization.The complex data of frame-synchronizing device output is arbitrarily, and its real part and imaginary data are all represented (positive number is with former representation, and negative is represented with two) with N position binary form, and length N also is arbitrarily.This depends on the input data of frame-synchronizing device.Real part and the imaginary part two paths of data of supposing frame-synchronizing device output are 32 bits.And suppose that its real part is 11111111111111111111111101100000 (160), its imaginary part is 00000000000000000000000110010000 (+400).

100 absolute value devices take absolute value to the real part data and the imaginary data of input, and according to their sign bit, quadrant sign X are set, and its form is x ₁x ₀, x wherein ₁Be the sign bit of real part data, x ₀Be the sign bit of imaginary data, can obtain

The 00-------first quartile

10-------second quadrant

The 11-------third quadrant

The 01-------four-quadrant

From the input data of supposition, the sign bit of its real part is 1, promptly is a negative, and the output of absolute value device is 00000000000000000000000010100000 (+160), and the sign bit of its imaginary part is 0, promptly is a positive number.The output of absolute value device is constant, still is 00000000000000000000000110010000 (+400), and can determine that quadrant flag bit X is 10, and at second quadrant, promptly the scope of rotatable phase is

111 phase limitators are handled the real part and the imaginary data of the output of absolute value device, and the phase place of rotation is limited to In the scope, promptly imaginary data is not more than the real part data.Because the real part and the imaginary data of absolute value device output all are positive numbers, promptly in the first quartile scope, when imaginary data during greater than the real part data, i.e. phase place $\mathrm{\α}\∈(\frac{\mathrm{\π}}{4},\frac{\mathrm{\π}}{2}],$ Exchange imaginary part and real part, obtain

And actual situation flag bit C is set, C is

1------------------works as imaginary data greater than the real part data $\mathrm{\α}\∈(\frac{\mathrm{\π}}{4},\frac{\mathrm{\π}}{2}]$

0------------------works as imaginary data and is not more than the real part data $\mathrm{\α}\∈(0,\frac{\mathrm{\π}}{4}]$ The input data of supposing, real part are 00000000000000000000000010100000 (+160), and imaginary part is 00000000000000000000000110010000 (+400), exchange real part and imaginary data, the phase place after the feasible displacement $\mathrm{\α}\∈(0,\frac{\mathrm{\π}}{4}],$ The real part that is phase limitator output is 00000000000000000000000110010000 (+400), and imaginary part is 00000000000000000000000010100000 (+160), and C is set is 1.

112 molecule denominator shift units are shifted and intercept the real part of phase limitator output and imaginary data (all representing with N position binary form).With suitable reduction data precision is that cost is simplified divider subsequently, to reach the effect of saving the FPGA resource and reducing system complexity.The imaginary data of phase place delimiter output is as molecule, and the real part data are as denominator.By the function of above-mentioned phase limitator as can be known, molecule is less than or equal to denominator, promptly subsequently the result that obtains of divider smaller or equal to 1.Because floating number can not realize in hardware, needs by suitable amplification.The mechanism of operation is the binary data t position of denominator of moving to left earlier, and making the highest order of denominator is not 0, and the molecule t position that correspondingly moves to left intercepts and export the high p position of denominator and the high 2p position of molecule then.Length p depends on the requirement to back divider and address mapper precision.By displacement and intercepting, can enlarge 2p doubly to the merchant of divider generation subsequently.For the input data of supposition, molecule is 00000000000000000000000010100000 (+160), and denominator is 00000000000000000000000110010000 (+400).To the denominator t position that moves to left, making its highest order is not 0, promptly obtains 11001000000000000000000000000000, has moved to left 23.To the molecule identical figure place that moves to left, promptly obtain 01010000000000000000000000000000.According to the requirement of divider and address mapper subsequently, suitably select length p.Suppose that p is 8, promptly intercept the high 16 of the most-significant byte of denominator and molecule, the denominator of output is 11001000 (200), and molecule is 0101000000000000 (20480).As do not have this molecule denominator shift unit, and promptly dividend is 160, and divisor is 400, and obtaining theoretic merchant is 0.4, and floating number can not show in hardware accurately, has influenced the map addresses of compensating factor memory subsequently.

113 dividers according to the molecule and the denominator data of molecule denominator shift unit output, calculate and the corresponding merchant of output.The divisor of divider and dividend are set to p position and 2p position respectively, and the merchant who obtains is the p position.Wherein the length of p depends on the multiple of the required expansion of theoretic merchant (floating number), promptly uses the precision of binary number representation floating number.Hypothesis p according to the front is 8, and molecule is 0101000000000000 (20480), and denominator is 11001000 (200), obtains and the merchant that exports is 01100110 (102), and the merchant who is about above-mentioned theory has enlarged 256, promptly 2 ₈Doubly.

114 address mapper, according to the high u position of the address of the merchant of divider output and quadrant sign and actual situation flag bit mapping compensating factor memory, the points N of an OFDM symbol is then depended in low v position, its relation is N=2 ^y, be mapped to promptly that a block length is the beginning of the data of N in the compensating factor memory.Because the phase place of rotation is arbitrarily in [π, π] scope, in order to save the resource of FPGA, promptly reduces the size of compensating factor memory, can be to the linear five equilibrium of whole phase range, promptly rotatable phase is similar to and its immediate five equilibrium phase place arbitrarily.For easy and simple to handle, the scope that defines rotatable phase in said process is

At this scope internal linear D five equilibrium, each five equilibrium phase place is corresponding to the blocks of data in the compensating factor memory, the length of data block depends on counting of a defined OFDM symbol, for example OFDM symbol of regulation comprises 64 points in the 802.11a standard, and OFDM symbol of regulation comprises 256 points in 802.16 standards.Because existing maximum likelihood estimation algorithm is done the estimation of primary carrier frequency departure to each frame, so approximate rotatable phase remains unchanged in a frame, corresponding compensating factor is

$\cos [\frac{n}{N}\∠z]$ With $\sin [\frac{n}{N}\∠z]$

Wherein ∠ z is approximate rotatable phase, and N is counting of an OFDM symbol

N=0,1,2 ..., n-1 is promptly for each symbol in the frame (N point), and the compensating factor piece in the respective memory (N point) is constant, and to the every bit in the OFDM symbol (a pair of plural number), has some corresponding compensation factors.The tangent value of branch phase places such as linearity is non-linear, calculates its corresponding tangent value, because Tangent value in the scope is less than or equal to 1, equally amplifies 2 with above-mentioned ^pDoubly.The result of divider output and D tangent value that amplifies are made comparisons, get immediate with it tangent value and pairing five equilibrium phase place, again according to corresponding marker bit, can determine to be similar to actual rotatable phase at [π, + π] the interior five equilibrium phase place of scope, and map out the high address of corresponding compensation factor memory, can find the block compensation factor in the memory. Linear isodisperse D in the scope depends on the precision of desired carrier frequency offset compensation, promptly get thin more, to accurate more, but then by the compensation of rotatable phase that carrier frequency offset causes, the compensating factor memory will increase, and promptly can consume the ROM resource of FPGA in a large number.Suppose Interior 16 five equilibriums, referring to component and the pairing nonlinear tangent values such as phase linearity of Fig. 4, can determine the result's 102 immediate tangent values with divider output, and further determine corresponding five equilibrium phase place, because through above-mentioned processing, define the estimated approximate five equilibrium phase place that goes out and exist

In the scope,, can make approximate rotatable phase shine upon back the quadrant at original place in conjunction with above-mentioned quadrant flag bit X (10) and actual situation flag bit C (1), promptly in [π ,+π] scope, and the high address of output corresponding compensation factor memory.

115 compensating factor memories, in branch phase places such as [0, π] middle M, each five equilibrium phase place exists N sine value and cosine value.N depends on counting of a defined in advance OFDM symbol, and for example 802.11a has stipulated that an OFDM symbol is 64 points, i.e. N=64, and 802.16 stipulated that an OFDM symbol is 256 points, promptly N=256. can obtain

$\cos [\frac{n}{N}\∠z_i],$ $\sin [\frac{n}{N}\∠z_i]$ N=0 wherein, 1 ..., N-1

I=0,1 ..., M is because the sine of phase place and cosine value all smaller or equal to 1, can suitably enlarge 2 as required ^qDoubly.The compensating factor memory stores enlarged 2 ^qSine and cosine value doubly.The size of compensating factor memory depends on parameter N and M, promptly to the phase place of each linear five equilibrium, can calculate N sine and cosine value in advance and enlarge 2 ^qDoubly, deposit in the memory successively.One total M+1 five equilibrium phase place.When definition whole OFDM system parameter, can determine N, and determining of M is a kind of balance to required precision and hardware resource, i.e. the precision of carrier wave frequency deviation compensation is high more, and the compensating factor memory is just big more, and the resource of the FPGA that consumes is also just many more.To existing 802.11a system design, N=64, as 64 five equilibriums in [0, π], promptly the five equilibrium PHASE DISTRIBUTION is 0,

..., π.

$\cos [\frac{n}{64}\∠z_i]$ With $\sin [\frac{n}{64}\∠z_i]$ N=0 wherein, 1 ..., 63, ∠ z _i=0,

..., the result of sine and cosine functions above the π deposits two compensating factor memories (sinusoidal data and cosine data are separately deposited) in successively with binary form after enlarging.According to the output of front address mapper, from the compensating factor memory, read corresponding data.Branch phase place ∠ z such as each linearity _iA corresponding blocks of data in the compensating factor memory promptly in above-mentioned formula, is fixed a ∠ z, and n=0,1 ..., N-1.

116 phase compensators are done the compensation of carrier frequency offset to each of OFDM symbol of input to plural number.Because existing maximum Likelihood is that each frame is made a frequency offset estimating, so in a frame, the approximate phase place that obtains by said method is constant, promptly in the frame, the compensating factor that each OFDM symbol is done phase compensation is a constant (corresponding blocks of data n=0 fixing in the memory, 1 ..., N-1).Can find a blocks of data in the approximate pairing phase compensating factor memories of branch phase place ∠ z such as linearity according to above-mentioned reflection method.When definition and design ofdm system parameter, need provide and comprised F OFDM symbol in the frame, each symbol has comprised N point (being N group plural number), and the OFDM data that arbitrary assumption is imported are Z _Sn=a _Sn+ jb _Sn

Wherein s is the OFDM symbolic number, in a frame, and s=0,1 ..., F-1,

N is counting of an OFDM symbol, n=0, and 1 ..., N-1,

Reading corresponding phase compensating factor piece is

C _n＝d _n+je _n

N=0 wherein, 1 ..., N-1,

Result after the compensation is

$Z_{\mathrm{sn}}=Z_{\mathrm{sn}}*C_n$

Can obtain result after the carrier frequency offset compensation by complex multiplication.The scope of having described the rotatable phase that is caused by carrier frequency offset in front is [π, + π], and the pairing model of phase compensating factor memory is [0 ,+π], as ∈ [0, + π] time, have cos ()=cos , sin ()=-sin , can be by quadrant sign X, revise the symbol of respective phase compensating factor, can obtain

$Z=(a_{\mathrm{sn}}{d}_n-b_{\mathrm{sn}}{e}_n)+j(a_{\mathrm{sn}}{e}_n+b_{\mathrm{sn}}{d}_{n)}$ When ∈ [0 ,+π]

$Z=(a_{\mathrm{sn}}{d}_n+b_{\mathrm{sn}}{e}_n)+j(b_{\mathrm{sn}}{d}_n-a_{\mathrm{sn}}{e}_n)$ When ∈ [π, 0]

117 compensation result reducers suitably dwindle the real part and the imaginary data of phase compensator output.As previously mentioned, because phase compensating factor has enlarged 2 as required ^qDoubly, so also wanting corresponding, the result after the rotatable phase compensation dwindles 2 ^qDoubly.I.e. real part and imaginary data for representing with binary form, the q position has moved to right.

118 result memories, be used for storing successively real part and the imaginary data that the compensation result reducer is exported, when whole OFDM system is done planning, consider from system requirements and hardware resource, the capacity of definition result memory, for example the capacity of definable result memory is frame data, promptly stores each OFDM symbol (each OFDM symbol has comprised N point again) after the carrier frequency offset compensation in the frame.According to the design of ofdm system, other device can read the data in the result memory and do next step processing.By suitable Handshake Protocol, when the frame data in the result memory processed intact after, the next frame data are estimated and compensation back renewal result memory through above-mentioned carrier frequency offset.

Although above the invention has been described in conjunction with various embodiment, they are all just illustrative.Those skilled in the art can various replacements and conversion in addition on the basis of above-mentioned detailed description.Therefore, all fall within the change in claim or its scope that is equal to and revise and will be contained by the claim of being added.

Claims (4)

1, the method for estimation and compensating frequency deviation in a kind of ofdm system, it is characterized in that: step is as follows:

A. simplify the calculating of original a series of trigonometric function by the mapping look-up of table method, the scope of rotatable phase only need be considered [0:+ π], promptly the first, and the angle of two quadrant;

B. when the OFDM symbol is done phase compensation, regulate sign bit and work as rotatable phase the 3rd, four-quadrant;

C. according to the desired precision of practical application to the linear five equilibrium of whole phase range, i.e. m five equilibrium between [0: π], rotatable phase is approximately immediate five equilibrium phase place arbitrarily;

D. determine the size of compensating factor table according to the thickness of five equilibrium.

2, a kind ofly realize in the described ofdm system of claim 1 estimating and the device of the method for compensating frequency deviation that it is characterized in that: comprising: frame synchronizer is used for the data flow that receives synchronously by the training sequence of setting; Carrier frequency offset estimator is used for the phase place rotation that approximate calculation is caused by carrier frequency offset; Remove the CP device, be used to remove the preceding Cyclic Prefix of each OFDM symbol; Compensating factor table device is used to store the compensating factor corresponding to the rotatable phase that is caused by carrier frequency offset; The carrier wave frequency deviation compensator, the rotatable phase value that calculates by each frame is tabled look-up and is obtained the corresponding compensation factor, and each the OFDM sign indicating number in the frame is carried out compensate of frequency deviation, to realize Frequency Synchronization.

3, a kind ofly realize in the described ofdm system of claim 1 estimating and the device of the method for compensating frequency deviation, it is characterized in that: comprise absolute value device, phase limitator, molecule denominator shift unit, divider, address mapper, compensating factor memory, phase compensator, compensation result reducer, result memory.

4, the device of the method for estimation and compensating frequency deviation in the ofdm system according to claim 3 is characterized in that:

This absolute value device for handling conveniently, is saved resource, temporarily ignores the symbol of real part and imaginary data, gets their absolute value, and data represent with binary form, and according to their symbol, corresponding quadrant flag bit is set;

This phase limitator, it is according to the output of absolute value device, and for saving resource, the temporary transient phase place that further limits rotation exists

Be that its tangent value is not more than 1,, exchange imaginary part and real part data, corresponding actual situation flag bit is set when imaginary data during greater than the real part data;

This molecule denominator shift unit, it is according to the output of phase limitator, molecule, be imaginary data, less than denominator, i.e. real part data, the binary number of denominator move to left to highest order be not 0, the binary number of the molecule identical figure place that moves to left is simultaneously sent into divider to the high t position of the high 2t position of molecule and denominator, according to the length of the demand of back divider precision suitably being selected t;

This divider, it is according to the output of molecule denominator shift unit, and imaginary data obtains one and is not more than 1 merchant divided by the real part data, represents with the t bit binary data;

This address mapper, it determines the address of compensating factor memory according to the output of divider and corresponding quadrant flag bit and actual situation flag bit;

This compensating factor memory, it is according to the output of mapper, it is the address of compensating factor memory, read pairing compensating factor, this memory stores n the sine value and the cosine value of in advance good m rotatable phase in [0: π] scope, with the fixed binary form through suitably amplifying expression;

This phase compensator, it is according to the output of compensating factor memory and corresponding quadrant flag bit, to each of the OFDM symbol of input to plural phase compensation, i.e. complex operation;

This compensation result reducer is used for the result of phase compensator is dwindled accordingly;

This result memory, the output of depositing the compensation result reducer, real part and imaginary data are separately deposited.

Images