CN103973308A - D/a converter - Google Patents

D/a converter Download PDF

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Publication number
CN103973308A
CN103973308A CN201410043091.7A CN201410043091A CN103973308A CN 103973308 A CN103973308 A CN 103973308A CN 201410043091 A CN201410043091 A CN 201410043091A CN 103973308 A CN103973308 A CN 103973308A
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resistor
terminal
transistor
couple
circuit
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CN201410043091.7A
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CN103973308B (en
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铃木久雄
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Socionext Inc
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Fujitsu Semiconductor Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/78—Simultaneous conversion using ladder network
    • H03M1/785—Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0612—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic over the full range of the converter, e.g. for correcting differential non-linearity
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

A digital-to-analog (D/A) converter includes first resistors coupled in series, second resistors respectively coupled to the first resistors and each having a resistance twice as large as the resistance of the first resistor, and first switch circuits respectively coupled to the second resistors. Third resistors each have a resistance twice as large as the resistance of the first resistor. Second switch circuits each are coupled to the third resistors and a GND wire. A control circuit controls the first and second switch circuit in accordance with the digital input signals to set a state of a connection node to either one of a first voltage, a second voltage, and a high impedance.

Description

D/A converter
Technical field
The disclosure relates to digital-to-analog (D/A) transducer.
Background technology
As the one for digital input signals being converted to the D/A converter of analog signal, the R-2R type D/A converter of known use R-2R resistor ladder network (for example, Japanese Patent Publication 63-47289 communique).
Referring to Figure 19, traditional R-2R type D/A converter 100 comprises resistor network 110 and six switches 200 to 205 corresponding with 6 bit digital input signal D0 to D5.Switch 200 to 205 comprises and is coupled in respectively the transistor 200a to 205a between wire 220 and the resistor network 110 with high voltage VD level and is coupled in respectively resistor network 110 and has the transistor 200b to 205b between the wire 221 of low-voltage GND level.Transistor 200a to 205a and transistor 200b to 205b are according to complementally on/off of digital input signals D0 to D5.In shown embodiment, each in switch 200 to 205 is CMOS inverter circuit.
R-2R type D/A converter 100 outputting analog signal Vo, analog signal Vo has by cut apart the magnitude of voltage that the voltage difference between high voltage VD and low-voltage GND obtains by the connection resistance that is included in resistance in resistor network 110 and corresponding transistor 200a to 205a and 200b to 205b.For example, as shown in Figure 20, R-2R type D/A converter 100 output has with code (decimal number) and the analog signal Vo of the corresponding magnitude of voltage of code (binary number being represented by digital input signals D0 to D5) is set.For the magnitude of voltage of the analog signal Vo in Figure 20, high voltage VD is 6.4[V], low-voltage GND is 0[V].Each code is the decimal number corresponding with the binary system array being represented by digital input signals D0 to D5.
Summary of the invention
In R-2R type D/A converter 100 as shown in figure 19, the size weighting according to digital input signals D0 to D5 to transistor 200a to 205a and 200b to 205b.In Figure 19, the numerical value shown in the side of each transistor 200a to 205a and 200b to 205b represents the ratio of transistor size.That is, symbol " × 1 " represents one times, and symbol " × 2 " represents twice, and symbol " × 4 " represents four times, and symbol " × 8 " represents octuple, and symbol " × 16 " represents 16 times, and symbol " × 32 " represents 32 times.Therefore, with the size of the ratio weighting transistor 200a to 205a of binary system (2 powers) and the size of transistor 200b to 205b.
Transistor size is weighted to suppress the deterioration of D/A conversion accuracy, as the differential nonlinearity (DNL) of R-2R type D/A converter 100.For example, flow through the current value that is included in the resistor in resistor network 110 according to code (logic level of digital input signals D0 to D2) variation is set.At this, as shown in Figure 19 and Figure 21, switch 200 has the resistance R 200 of connection, switch 201 has the resistance R 201 of connection, and switch 202 has the resistance R 202 of connection, and switch 203 has the resistance R 203 of connection, switch 204 has the resistance R 204 of connection, and switch 205 has the resistance R 205 of connection.Suppose that connecting the resistance value of resistance R 200 to R205 is equal to each other, the terminal voltage that is couple to the terminal a to f of the resistor of connecting resistance R 200 to R205 changes owing to flowing through the electric current that is included in the resistor in resistor network 110.The variation of terminal voltage increases DNL.Therefore, as shown in figure 22, in the time that the resistance value of connection resistance R 200-R205 is equal to each other, DNL characteristic significantly worsens.At this, the DNL waveform in Figure 22 illustrates the DNL(longitudinal axis about each code (transverse axis)) size, and the DNL characteristic when resistance value of connecting resistance R 200-R205 is equal to each other is shown.DNL is the error with desirable step-length as the step-length (step size) in the analog signal Vo of D/A conversion output.Therefore, can think, in the time having corresponding to the DNL of each code the value that approaches zero, DNL characteristic is good, and in the time thering is the value of offset from zero corresponding to the DNL of each code, DNL characteristic degradation.
As shown in figure 19, the above-mentioned situation mutually the same with the resistance value of connecting resistance R 200 to R205 is contrary, when the transistor size of transistor 200a to 205a and 200b to 205b adds temporary with binary ratio, as shown in figure 23, can obtain good DNL characteristic.For example, as shown in figure 19, in the time that the transistor size of transistor 200a to 205a and 200b to 205b is weighted, the resistance value of connecting resistance R 205 to R200 is compared weighting with binary.For example, taking the resistance value of connecting resistance R 205 as benchmark, the resistance value of connecting resistance R 204 is 2 times, the resistance value of connecting resistance R 203 is 4 times, the resistance value of connecting resistance R 202 is 8 times, and the resistance value of connecting resistance R 201 is 16 times, and the resistance value of connecting resistance R 200 is 32 times.For example, be set to 0.2[k Ω when connecting resistance R 205] time, connect resistance R 204 and become 0.4[k Ω], connect resistance R 203 and become 0.8[k Ω], connect resistance R 202 and become 1.6[k Ω], connect resistance R 201 and become 3.2[k Ω], connect resistance R 200 and become 6.4[k Ω].When the resistance value of connecting resistance R 205 to R200 adds temporary with binary ratio like this, the variation of the terminal voltage of terminal a to f can be suppressed, and as shown in figure 23, can obtain good DNL characteristic.
But in the time that the figure place in R-2R type D/A converter 100 increases, the excursion of connecting the resistance value of resistance R 200 to R205 increases, and DNL characteristic (D/A conversion accuracy) worsens.
For example, the DNL waveform in Figure 23 illustrates the DNL characteristic when resistance components of switch 200 to 205 is processed as fixed value.But for actual R-2R type D/A converter 100, the connection resistance of transistor 200a to 205a and 200b to 205b becomes the resistance components of switch 200 to 205.Now, the connection resistance of MOS transistor changes according to the magnitude of voltage that is applied to source terminal from the drain terminal of MOS transistor.Therefore, the connection resistance value of transistor 200a to 205a and 200b to 205b changes according to the variation that code (logic level of digital input signals D0 to D5) is set.Therefore, according to the variation that code is set, occur error in the connection resistance value of transistor 200a to 205a and 200b to 205b with binary between than the resistance value of weighting, and to change appear in the terminal voltage of terminal a to f, result D/A conversion accuracy (DNL characteristic) worsens.
According to an aspect of the present invention, a kind of digital-to-analog (D/A) transducer that generates analog signal according to digital input signals, comprise multiple the first resistors between the first lead-out terminal and the second lead-out terminal that is coupled in series in the described analog signal of output, described the first resistor has identical resistance.Multiple the second resistors comprise the first terminal that is couple to respectively described multiple the first resistors, and the resistance of each the second resistor is the twice of the resistance of described the first resistor.Described the first lead-out terminal is couple to the first terminal of one of described multiple second resistors.Multiple the first switching circuits are couple to respectively the second terminal of described multiple the second resistors.The 3rd resistor, the resistance of described the 3rd resistor is the twice of the resistance of the first resistor, and the first terminal of described the 3rd resistor is couple in the first terminal of the second resistor except being couple to second resistor of described the first lead-out terminal.Second switch circuit comprises the first terminal of the second terminal that is couple to the 3rd resistor and is couple to the second terminal of the first wire.Control circuit is couple to described the first and second switching circuits, and is configured to generate for controlling the first signal of described the first switching circuit and for controlling the secondary signal of described second switch circuit according to described digital input signals.Control one or more first switching circuit that is coupled to following the second resistor in described multiple the first switching circuit, and the state that is arranged at the connected node between described one or more first switching circuit and corresponding the second resistor is set to the first voltage, be different from any in second voltage and the high impedance of described the first voltage, this second resistor is coupled to described the first lead-out terminal and the node between the connected node between two adjacent the first resistors, and the first terminal of described the 3rd resistor is coupled to this second resistor.
Additional object of the present invention and advantage part provide in the following description, and part will become obviously by this description, or can learn by implementing the present invention.Utilize element and the combination in appended claims, specifically noted can realize and obtain objects and advantages of the present invention.
Should be appreciated that above general description and following detailed description are all exemplary and explanat, and do not limit claimed the present invention.
Brief description of the drawings
Fig. 1 is according to the circuit block diagram of the D/A converter of embodiment;
Fig. 2 A to Fig. 2 E is the schematic diagram of explaining the method for weighting of switch;
Fig. 3 is the schematic diagram of explaining the method for weighting of switch;
Fig. 4 is the circuit diagram of the example of the internal structure of logical circuit;
Fig. 5 explains according to the schematic diagram of the operation of the D/A converter of this embodiment;
Fig. 6 A and Fig. 6 B explain according to the schematic diagram of the action of the D/A converter of this embodiment;
Fig. 7 A and Fig. 7 B are the schematic diagrames of explaining the problem of traditional D/A converter;
Fig. 8 A is the circuit diagram that occurs the large D/A converter changing in the connection resistance of switch;
The figure of the DNL characteristic of the D/A converter that Fig. 8 B is;
Fig. 9 A is the circuit diagram that occurs the large traditional D/A converter changing in the connection resistance of switch;
Fig. 9 B is the figure of the DNL characteristic of the D/A converter of Fig. 9 A;
Figure 10 A is the circuit diagram that occurs the large D/A converter changing in the connection resistance of switch;
Figure 10 B is the figure of the DNL characteristic of the D/A converter of Figure 10 A;
Figure 11 A is the circuit diagram that occurs the large traditional D/A converter changing in the connection resistance of switch;
Figure 11 B is the figure of the DNL characteristic of the D/A converter of Figure 11 A;
Figure 12 is according to the circuit block diagram of the D/A converter of a variation;
Figure 13 is according to the figure of the DNL characteristic of the D/A converter of this variation;
Figure 14 A is according to the circuit diagram that occurs the D/A converter of the large variation changing in the connection resistance of switch;
Figure 14 B is the figure of the DNL characteristic of the D/A converter of Figure 14 A;
Figure 15 A is the circuit diagram that occurs the large traditional D/A converter changing in the connection resistance of switch;
Figure 15 B is the figure of the DNL characteristic of the D/A converter of Figure 15 A;
Figure 16 is according to the circuit block diagram of the D/A converter of a variation;
Figure 17 A is according to the circuit diagram that occurs the D/A converter of large this variation changing in the connection resistance of switch;
Figure 17 B is the figure of the DNL characteristic of the D/A converter of Figure 17 A;
Figure 17 C is the figure of the DNL characteristic of the D/A converter of Figure 14 A, Figure 15 A and Figure 17 A;
Figure 18 is according to the circuit block diagram of the D/A converter of a variation;
Figure 19 is the circuit diagram of traditional D/A converter;
Figure 20 is the schematic diagram of explaining the operation of traditional D/A converter;
Figure 21 is the equivalent circuit diagram of traditional D/A converter;
Figure 22 is the figure of the DNL characteristic of the traditional D/A converter of the connection resistance when all switches when mutually the same;
Figure 23 is the figure of the DNL characteristic of the traditional D/A converter when with binary connection resistance than weighting switch;
Figure 24 is the figure of relation between interpretive code and the terminal voltage of terminal a to g;
Figure 25 is the figure of the impact on DNL characteristic of the variation of connection resistance of explaining the switch of highest significant position (MSB) side; And
Figure 26 is the figure of the impact on DNL characteristic of the variation of connection resistance of explaining the switch of least significant bit (LSB) side.
Description of reference numerals
1,1A-1C digital-analog convertor
10 resistor networks
20-25,30-35 inverter circuit
40-45NOR circuit
50 logical circuits
R0-R5 resistor (the first resistor)
R10-R15 resistor (the second resistor)
R20 resistor (the 4th resistor)
R21-R25 resistor (the 3rd resistor)
SW0-SW5 switch (the first switching circuit)
S0 switch (the 3rd switching circuit)
S1-S5 switch (second switch circuit)
TN0-TN5 transistor
TP0-TP5 transistor
T0-T5 transistor (the 3rd transistor)
Tn reference transistor
Tp reference transistor
Embodiment
Explain embodiment below with reference to Fig. 1 to Figure 11.
Referring to Fig. 1, can be R-2R type D/A converter according to the digital-to-analog of embodiment (D/A) transducer 1.D/A converter 1 generates the analog signal Vo with the magnitude of voltage corresponding with 6 bit digital input signal D0-D5.Digital input signals D0 is least significant bit (LSB), and digital input signals D1 is the second least significant bit, and digital input signals D2 is the 3rd least significant bit, and digital input signals D3 is the 4th least significant bit.In addition, digital input signals D4 is the 5th least significant bit, and digital input signals D5 is highest significant position (MSB).
D/A converter 1 comprises resistor network 10, switching circuit SW0 to SW5, the switching circuit S0 to S5 corresponding with digital input signals D0 to D5, inverter circuit 20 to 25 and 30 to 35 or the logical circuit 50 that is imported into of non-(NOR) circuit 40 to 45 and digital input signals D0 to D5 respectively.At this, switching circuit SW0, SW1, SW2, SW3, SW4 and SW5 are the switches arranging accordingly with digital input signals D0, D1, D2, D3, D4 and D5 respectively.Switching circuit S0, S1, S2, S3, S4 and S5 are the switches arranging accordingly with digital input signals D0, D1, D2, D3, D4 and D5 respectively.
Resistor network 10 comprises that the resistor R0 being coupled in series between the first lead-out terminal and the second lead-out terminal To is to R5, be couple to the resistor R10 to R15 of switching circuit SW0 to SW5 and be couple to respectively the resistor R20 to R25 of the first terminal of resistor R10 to R15 respectively.Resistor R0 has an identical resistance R to R5 is each.The resistance of each resistor R10 to R15 is set to the twice (2R) of each resistor R0 to the resistance R of R5.The resistance of each resistor R20 to R25 is set to the twice (2R) of each resistor R0 to the resistance R of R5.That is to say, the resistance of each resistor R20 to R25 is set to the resistance 2R equating with the resistance 2R of each resistor R10 to R15.In Fig. 1, for the ease of understanding the resistance of resistor R0 to R5, R10 to R15 and resistor R20 to R25, show resistor R0 to the each resistor in R5 by a resistor symbols, and the each resistor in resistor R10 to R15 and resistor R20 to R25 is shown by two resistor symbols.Resistance is that the each resistor in resistor R10 to R15 and the R20 to R25 of 2R can have the circuit structure that is connected in series the resistor that two resistance are R.The resistance of resistor R10, R11, R12, R13, R14 and R15 arranges accordingly with digital input signals D0, D1, D2, D3, D4 and D5 respectively.
Resistor R0 is to R5 coupled in series.The first terminal of resistor R10 to R15 is couple to the first terminal of resistor R20 to R25 the node that resistor R0 couples mutually to R5.For example, the first terminal of the first terminal of resistor R10 and resistor R20 is couple to the first terminal of resistor R0 (right terminal in Fig. 1), that is, and and the first lead-out terminal.The connected node that the second terminal that the first terminal of resistor R11 and the first terminal of resistor R21 are couple to resistor R0 and the first terminal of resistor R1 couple mutually.The connected node that the second terminal that the first terminal of resistor R12 and the first terminal of resistor R22 are couple to resistor R1 and the first terminal of resistor R2 couple mutually.The connected node that the second terminal that the first terminal of resistor R13 and the first terminal of resistor R23 are couple to resistor R2 and the first terminal of resistor R3 couple mutually.The connected node that the second terminal that the first terminal of resistor R14 and the first terminal of resistor R24 are couple to resistor R3 and the first terminal of resistor R4 couple mutually.The connected node that the second terminal that the first terminal of resistor R15 and the first terminal of resistor R25 are couple to resistor R4 and the first terminal of resistor R5 couple mutually.The second terminal of resistor R5 is couple to the second lead-out terminal To.
The second terminal of resistor R10 is couple to switching circuit SW0, and the second terminal of resistor R11 is couple to switching circuit SW1, and the second terminal of resistor R12 is couple to switching circuit SW2.The second terminal of resistor R13 is couple to switching circuit SW3, and the second terminal of resistor R14 is couple to switching circuit SW4, and the second terminal of resistor R15 is couple to switching circuit SW5.The first terminal of resistor R20 is couple to the first terminal of resistor R10, and the second terminal of resistor R20 is couple to switching circuit S0.The first terminal of resistor R21 is couple to the first terminal of resistor R11, and the second terminal of resistor R21 is couple to switching circuit S1.The first terminal of resistor R22 is couple to the first terminal of resistor R12, and the second terminal of resistor R22 is couple to switching circuit S2.The first terminal of resistor R23 is couple to the first terminal of resistor R13, and the second terminal of resistor R23 is couple to switching circuit S3.The first terminal of resistor R24 is couple to the first terminal of resistor R14, and the second terminal of resistor R24 is couple to switching circuit S4.The first terminal of resistor R25 is couple to the first terminal of resistor R15, and the second terminal of resistor R25 is couple to switching circuit S5.
Switching circuit SW0 comprises two transistor T P0 and TN0.For example, transistor T P0 is P channel MOS transistor, and transistor T N0 is N-channel MOS transistor.The source terminal of transistor T P0 is couple to provides the wire of high voltage VD (hereinafter claiming the line also referred to as VD).The drain terminal of transistor T P0 is couple to the second terminal of resistor R10 and the drain terminal of transistor T N0.For example, the node N0 that the second terminal that the drain terminal of transistor T P0 and TN0 is couple to resistor R10 and the lead-out terminal of switching circuit SW0 couple mutually.The source terminal of transistor T N0 is couple to provides the wire of low-voltage GND (hereinafter also referred to as GND line).The gate terminal of transistor T P0 is couple to the lead-out terminal of inverter circuit 20.The input terminal of inverter circuit 20 is couple to the lead-out terminal of inverter circuit 30, and from logical circuit 50, signal DT0 is offered to inverter circuit 30.The gate terminal of transistor T N0 is couple to the lead-out terminal of NOR circuit 40.The output signal of inverter circuit 30 is provided for NOR circuit 40, and from logical circuit 50, signal DI0 is offered to NOR circuit 40.
Transistor T P0 is according to the logic level of signal DT0 (" 0(logic low L level) " or " the high H level of 1(logic) ") connect/cut-off.In addition, transistor T N0 is according to the logic level of the logic level of signal DT0 and signal DI0 (" 0(logic L level) " or " 1(logic H level) ") connect/cut-off.
For example, in the time exporting L level signal DT0 from logical circuit 50, transistor T P0 connects in response to the L level signal of exporting from inverter circuit 20, and transistor T N0 ends in response to the L level signal of exporting from NOR circuit 40.In the time that transistor T P0 connects thus, node N0 is couple to VD line, and the voltage of node N0 is set to H level (high voltage VD level).For example, the transistor T P0 that node N0 is switched on draws high high voltage VD level.In addition,, when export H level signal DT0 and L level signal DI0 from logical circuit 50, transistor T P0 ends in response to the H level signal of exporting from inverter circuit 20, and transistor T N0 connects in response to the H level signal of exporting from NOR circuit 40.In the time that transistor T N0 connects thus, node N0 is couple to GND line, and the voltage of node N0 is set to L level (low-voltage GND level).For example, the transistor T N0 that node N0 is switched on is pulled down to low-voltage GND level.In addition,, when export H level signal DT0 and H level signal DI0 from logical circuit 50, transistor T P0 ends in response to the H level signal of exporting from inverter circuit 20, and transistor T N0 ends in response to the L level signal of exporting from NOR circuit 40.In the time that transistor T P0 and TN0 all end therefrom, node N0 and VD line and GND line disconnect, and become open-circuit condition.When as transistor T P0 and TN0, the two all ends, node N0 becomes high impedance status.Therefore, switching circuit SW0 is in response to signal DT0 and DI0 node N0 and is set to the tri-state buffer circuit of H level, L level or high impedance status.
The structure of switching circuit SW1 to SW5 is identical with the structure of switching circuit SW0, at this by brief explanation.
SW0 is similar with switching circuit, and switching circuit SW1 is the tri-state buffer circuit that node N1 is set to H level, L level or high impedance status.Switching circuit SW1 comprises two transistor T P1 and TN1.For example, transistor T P1 is P channel MOS transistor, and transistor T N1 is N-channel MOS transistor.The source terminal of transistor T P1 is couple to VD line.The drain terminal of transistor T P1 is couple to the second terminal of resistor R11 and the drain terminal of transistor T N1.The node N1 that the second terminal that the drain terminal of transistor T P1 and TN1 is couple to resistor R11 and the lead-out terminal of switching circuit SW1 couple mutually.The source terminal of transistor T N1 is couple to GND line.The gate terminal of transistor T P1 is couple to the lead-out terminal of inverter circuit 21.The input terminal of inverter circuit 21 is couple to the lead-out terminal of inverter circuit 31, and from logical circuit 50, signal DT1 is offered to inverter circuit 31.The gate terminal of transistor T N1 is couple to the lead-out terminal of NOR circuit 41.The output signal of inverter circuit 31 is provided for NOR circuit 41, and from logical circuit 50, signal DI1 is offered to NOR circuit 41.
Transistor T P1 connects/ends according to the logic level of signal DT1 (" 0 " or " 1 ").In addition, transistor T N1 connects/ends according to the logic level of the logic level of signal DT1 and signal DI1 (" 0 " or " 1 ").In switching circuit SW1, at least one in transistor T P1 and TN1 is in response to signal DT1 and DI1 and end.
SW0 is similar with switching circuit, and switching circuit SW2 is the tri-state buffer circuit that node N2 is set to H level, L level or high impedance status.Switching circuit SW2 comprises two transistor T P2 and TN2.For example, transistor T P2 is P channel MOS transistor, and transistor T N2 is N-channel MOS transistor.The source terminal of transistor T P2 is couple to VD line.The drain terminal of transistor T P2 is couple to the second terminal of resistor R12 and the drain terminal of transistor T N2.The node N2 that the second terminal that the drain terminal of transistor T P2 and TN2 is couple to resistor R12 and the lead-out terminal of switching circuit SW2 couple mutually.The source terminal of transistor T N2 is couple to GND line.The gate terminal of transistor T P2 is couple to the lead-out terminal of inverter circuit 22.The input terminal of inverter circuit 22 is couple to the lead-out terminal of inverter circuit 32, and from logical circuit 50, signal DT2 is offered to inverter circuit 32.The gate terminal of transistor T N2 is couple to the lead-out terminal of NOR circuit 42.The output signal of inverter circuit 32 is provided for NOR circuit 42, and from logical circuit 50, signal DI2 is provided for to NOR circuit 42.
Transistor T P2 connects/ends according to the logic level of signal DT2 (" 0 " or " 1 ").In addition, transistor T N2 connects/ends according to the logic level of the logic level of signal DT2 and signal DI2 (" 0 " or " 1 ").In switching circuit SW2, at least one in transistor T P2 and TN2 is in response to signal DT2 and DI2 and end.
SW0 is similar with switching circuit, and switching circuit SW3 is the tri-state buffer circuit that node N3 is set to H level, L level or high impedance status.Switching circuit SW3 comprises two transistor T P3 and TN3.For example, transistor T P3 is P channel MOS transistor, and transistor T N3 is N-channel MOS transistor.The source terminal of transistor T P3 is couple to VD line.The drain terminal of transistor T P3 is couple to the second terminal of resistor R13 and the drain terminal of transistor T N3.The node N3 that the second terminal that the drain terminal of transistor T P3 and TN3 is couple to resistor R13 and the lead-out terminal of switching circuit SW3 couple mutually.The source terminal of transistor T N3 is couple to GND line.The gate terminal of transistor T P3 is couple to the lead-out terminal of inverter circuit 23.The input terminal of inverter circuit 23 is couple to the lead-out terminal of inverter circuit 33, and from logical circuit 50, signal DT3 is offered to inverter circuit 33.The gate terminal of transistor T N3 is couple to the lead-out terminal of NOR circuit 43.The output signal of inverter circuit 33 is provided for NOR circuit 43, and from logical circuit 50, signal DI3 is offered to NOR circuit 43.
Transistor T P3 connects/ends according to the logic level of signal DT3 (" 0 " or " 1 ").In addition, transistor T N3 connects/ends according to the logic level of the logic level of signal DT3 and signal DI3 (" 0 " or " 1 ").In switching circuit SW3, at least one in transistor T P3 and TN3 is in response to signal DT3 and DI3 and end.
SW0 is similar with switching circuit, and switching circuit SW4 is the tri-state buffer circuit that node N4 is set to H level, L level or high impedance status.Switching circuit SW4 comprises two transistor T P4 and TN4.For example, transistor T P4 is P channel MOS transistor, and transistor T N4 is N-channel MOS transistor.The source terminal of transistor T P4 is couple to VD line.The drain terminal of transistor T P4 is couple to the second terminal of resistor R14 and the drain terminal of transistor T N4.The node N4 that the second terminal that the drain terminal of transistor T P4 and TN4 is couple to resistor R14 and the lead-out terminal of switching circuit SW4 couple mutually.The source terminal of transistor T N4 is couple to GND line.The gate terminal of transistor T P4 is couple to the lead-out terminal of inverter circuit 24.The input terminal of inverter circuit 24 is couple to the lead-out terminal of inverter circuit 34, and from logical circuit 50, signal DT4 is offered to inverter circuit 34.The gate terminal of transistor T N4 is couple to the lead-out terminal of NOR circuit 44.The output signal of inverter circuit 34 is provided for NOR circuit 44, and from logical circuit 50, signal DI4 is offered to NOR circuit 44.
Transistor T P4 connects/ends according to the logic level of signal DT4 (" 0 " or " 1 ").In addition, transistor T N4 connects/ends according to the logic level of the logic level of signal DT4 and signal DI4 (" 0 " or " 1 ").In switching circuit SW4, at least one in transistor T P4 and TN4 is in response to signal DT4 and DI4 and end.
SW0 is similar with switching circuit, and switching circuit SW5 is the tri-state buffer circuit that node N5 is set to H level, L level or high impedance status.Switching circuit SW5 comprises two transistor T P5 and TN5.For example, transistor T P5 is P channel MOS transistor, and transistor T N5 is N-channel MOS transistor.The source terminal of transistor T P5 is couple to VD line.The drain terminal of transistor T P5 is couple to the second terminal of resistor R15 and the drain terminal of transistor T N5.The node N5 that the second terminal that the drain terminal of transistor T P5 and TN5 is couple to resistor R15 and the lead-out terminal of switching circuit SW5 couple mutually.The source terminal of transistor T N5 is couple to GND line.The gate terminal of transistor T P5 is couple to the lead-out terminal of inverter circuit 25.The input terminal of inverter circuit 25 is couple to the lead-out terminal of inverter circuit 35, and from logical circuit 50, signal DT5 is offered to inverter circuit 35.The gate terminal of transistor T N5 is couple to the lead-out terminal of NOR circuit 45.The output signal of inverter circuit 35 is provided for NOR circuit 45, and from logical circuit 50, signal DI5 is offered to NOR circuit 45.
Transistor T P5 connects/ends according to the logic level of signal DT5 (" 0 " or " 1 ").In addition, transistor T N5 connects/ends according to the logic level of the logic level of signal DT5 and signal DI5 (" 0 " or " 1 ").In switching circuit SW5, at least one in transistor T P5 and TN5 is in response to signal DT5 and DI5 and end.
Switching circuit S0 comprises a transistor T 0.For example, transistor T 0 is N-channel MOS transistor.The drain terminal (the first terminal) of transistor T 0 is couple to the second terminal of resistor R20.Low-voltage GND is provided for the source terminal (the second terminal) of transistor T 0.From logical circuit 50, signal DS0 is offered to the gate terminal (control terminal) of transistor T 0.Transistor T 0 is according to the logic level of signal DS0 (" 0(logic L level) " or " 1(logic H level) ") connect/cut-off.According to the connection of transistor T 0/cut-off action, the second terminal of resistor R20 is set to L level (low-voltage GND level) or high impedance status with the node NS0 that switching circuit S0 couples mutually.For example, in the time that transistor T 0 is connected in response to H level signal DS0, node NS0 is couple to GND line, and the voltage of node NS0 is set to L level (low-voltage GND level).For example, the transistor T 0 that node NS0 is switched on is pulled down to low-voltage GND level.In addition,, in the time that transistor T 0 ends in response to L level signal DS0, node NS0 and GND line disconnect, and become open-circuit condition.That is to say, in the time that transistor T 0 ends, node NS0 becomes high impedance status.
Switching circuit S1 comprises a transistor T 1.For example, transistor T 1 is N-channel MOS transistor.The drain terminal (the first terminal) of transistor T 1 is couple to the second terminal (node NS1) of resistor R21.The source terminal (the second terminal) of transistor T 1 is couple to GND line.From logical circuit 50, signal DS1 is offered to the gate terminal (control terminal) of transistor T 1.Transistor T 1 is according to connect/cut-off of the logic level of signal DS1 (" 0 " or " 1 ").According to the connection of transistor T 1/cut-off action, the second terminal of resistor R21 is set to L level (low-voltage GND level) or high impedance status with the node NS1 that switching circuit S1 couples mutually.For example, in the time that transistor T 1 is connected in response to H level signal DS1, node NS1 is couple to GND line, and the voltage of node NS1 is set to L level.That is to say, the transistor T 1 that node NS1 is switched on is pulled down to low-voltage GND level.In addition,, in the time that transistor T 1 ends in response to L level signal DS1, node NS1 and GND line disconnect, and become open-circuit condition.In the time that transistor T 1 ends, node NS1 becomes high impedance status.
The structure of switching circuit S2 to S5 is identical with the structure of switching circuit S1, at this by brief explanation.
Switching circuit S2 comprises a transistor T 2.For example, transistor T 2 is N-channel MOS transistors.The drain terminal (the first terminal) of transistor T 2 is couple to the second terminal (node NS2) of resistor R22.The source terminal (the second terminal) of transistor T 2 is couple to GND line.From logical circuit 50, signal DS2 is offered to the gate terminal (control terminal) of transistor T 2.Transistor T 2 is according to connect/cut-off of the logic level of signal DS2 (" 0 " or " 1 ").According to the connection of transistor T 2/cut-off action, the second terminal of resistor R22 is set to L level (low-voltage GND level) or high impedance status with the node NS2 that switching circuit S2 couples mutually.
Switching circuit S3 comprises a transistor T 3.For example, transistor T 3 is N-channel MOS transistors.The drain terminal (the first terminal) of transistor T 3 is couple to the second terminal (node NS3) of resistor R23.The source terminal (the second terminal) of transistor T 3 is couple to GND line.From logical circuit 50, signal DS3 is offered to the gate terminal (control terminal) of transistor T 3.Transistor T 3 is according to connect/cut-off of the logic level of signal DS3 (" 0 " or " 1 ").According to the connection of transistor T 3/cut-off action, the second terminal of resistor R23 is set to L level (low-voltage GND level) or high impedance status with the node NS3 that switching circuit S3 couples mutually.
Switching circuit S4 comprises a transistor T 4.For example, transistor T 4 is N-channel MOS transistors.The drain terminal (the first terminal) of transistor T 4 is couple to the second terminal (node NS4) of resistor R24.The source terminal (the second terminal) of transistor T 4 is couple to GND line.From logical circuit 50, signal DS4 is offered to the gate terminal (control terminal) of transistor T 4.Transistor T 4 is according to connect/cut-off of the logic level of signal DS4 (" 0 " or " 1 ").According to the connection of transistor T 4/cut-off action, the second terminal of resistor R24 is set to L level (low-voltage GND level) or high impedance status with the node NS4 that switching circuit S4 couples mutually.
Switching circuit S5 comprises a transistor T 5.For example, transistor T 5 is N-channel MOS transistors.The drain terminal (the first terminal) of transistor T 5 is couple to the second terminal (node NS5) of resistor R25.The source terminal (the second terminal) of transistor T 5 is couple to GND line.From logical circuit 50, signal DS5 is offered to the gate terminal (control terminal) of transistor T 5.Transistor T 5 is according to connect/cut-off of the logic level of signal DS5 (" 0 " or " 1 ").According to the connection of transistor T 5/cut-off action, the second terminal of resistor R25 is set to L level (low-voltage GND level) or high impedance status with the node NS5 that switching circuit S5 couples mutually.
In D/A converter 1, ideally, being included in transistor T P0 to TP5 in switching circuit SW0 to SW5 and the connection resistance of TN0 to TN5 is zero [Ω].This is because ideally, the terminal voltage that applies the resistance of high voltage VD or low-voltage GND to it via transistor is equal to each other.In addition, in D/A converter 1, flow through resistor R0 to the magnitude of current of R5 and R10 to R15 according to code is set, that is, the logic level of digital input signals D0 to D5 (" 0(logic L level) " or " 1(logic H level) ") combination and change.Therefore,, in the time that the connection resistance of transistor T P0 to TP5 and TN0 to TN5 is greater than zero [Ω] and is equal to each other, the variation of this magnitude of current can change the terminal voltage of resistor R10 to R15.
Therefore, according to digital input signals D0 to D5, the connection resistance of transistor T P0 to TP5 and TN0 to TN5 is weighted.For example, the connection resistance weighting with the ratio (1:2:4:8:16:32) of binary system (2 powers) to transistor T P5 to TP0, and with the connection resistance weighting of this binary comparison transistor T N5 to TN0.Similarly, with the connection resistance weighting of the transistor T 5 to T0 of this binary comparison and transistor T P5 to TP0 and TN5 to TN0 coupled in parallel.
For example, as shown in Figure 2 A, the connection resistance of transistor T P5 is set to reference resistance (× 1).The connection resistance of transistor T P4 is set to the twice (× 2) of reference resistance, and the connection resistance of transistor T P3 is set to four times (× 4) of reference resistance.Similarly, the connection resistance of transistor T P2 is set to the octuple (× 8) of the connection resistance (× 1) of transistor T P5, the connection resistance of transistor T P1 is set to 16 times (× 16) of the connection resistance (× 1) of transistor T P5, and the connection resistance of transistor T P0 is set to 32 times (× 32) of the connection resistance (× 1) of transistor T P5.Meanwhile, the connection resistance of transistor T N5 and T5 is set to reference resistance (× 1).The connection resistance of transistor T N4 and T4 is set to the twice (× 2) of this reference resistance, and the connection resistance of transistor T N3 and T3 is set to 4 times (× 4) of this reference resistance.Similarly, the connection resistance of transistor T N2 and T2 is set to the octuple (× 8) of the connection resistance (× 1) of transistor T N5 and T5, the connection resistance of transistor T N1 and T1 is set to 16 times (× 16) of the connection resistance (× 1) of transistor T N5 and T5, and the connection resistance of transistor T N0 and T0 is set to 32 times (× 32) of the connection resistance (× 1) of transistor T N5 and T5.
At this, connect resistance and be set to the transistor T P3 of four times and there is following structure (m=2): two reference transistor Tp coupled in parallel as shown in Figure 2 B, wherein, each reference transistor Tp has channel width Wp and channel length Lp as shown in Figure 2 D.In the case, the gate area of transistor T P3 is Wp × Lp × 2.Similarly, connecting resistance is set to transistor T N3 and the T3 of four times and has separately following structure (m=2): two reference transistor Tn coupled in parallel as shown in Figure 2 B, wherein, each reference transistor Tn has channel width Wn and channel length Ln as shown in Figure 2 E.In the case, the each gate area of transistor T N3 and T3 is Wn × Ln × 2.
Connect four reference transistor Tp(m=4 that transistor T P4 that resistance is set to twice (the connection resistance of transistor T P3 1/2 times) uses coupled in parallel).In the case, the gate area of transistor T P4 is Wp × Lp × 4.Similarly, connect resistance and be set to the transistor T N4 of twice (the connection resistance of transistor T P3 and T3 1/2 times) and T4 and use separately four reference transistor Tn(m=4 of coupled in parallel).In the case, the each gate area of transistor T N4 and T4 is Wn × Ln × 4.
Connect 8 reference transistor Tp(m=8 that transistor T P5 that resistance is set to reference resistance (the connection resistance of transistor T P3 1/4 times) uses coupled in parallel).In the case, the gate area of transistor T P5 is Wp × Lp × 8.Similarly, connect resistance and be set to the transistor T N5 of reference resistance (the connection resistance of transistor T N3 and T3 1/4 times) and T5 and use separately 8 reference transistor Tn(m=8 of coupled in parallel).In the case, the each gate area of transistor T N5 and T5 is Wn × Ln × 8.
Simultaneously, the transistor T P2 that connection resistance is set to 8 times (twices of the connection resistance of transistor T P3) has following structure (m=2 two stacks): two groups of reference transistor Tp coupled in parallel as shown in Figure 2 C, wherein, every group has the two stacks of two reference transistor Tp(of coupled in series).In the case, the gate area of transistor T P2 is Wp × Lp × 4.Similarly, transistor T N2 and T2 that connection resistance is set to 8 times (twices of the connection resistance of transistor T N3 and T3) have following structure separately: two groups of reference transistor Tn coupled in parallel as shown in Figure 2 C, wherein, every group has the two stacks of two reference transistor Tn(of coupled in series).In the case, the each gate area of transistor T N2 and T2 is Wn × Ln × 4.
Connect the transistor T P1 that resistance is set to 16 times (connection resistance of transistor T P3 4 times) and there is following structure (m=2 four stacks): two groups of reference transistor Tp coupled in parallel, wherein, every group has 4 reference transistor Tp(tetra-stacks of coupled in series).In the case, the gate area of transistor T P1 is Wp × Lp × 8.Similarly, connect transistor T N1 and the T1 that resistance is set to 16 times (connection resistance of transistor T N3 and T3 4 times) and there is separately following structure (m=2 four stacks): two groups of reference transistor Tn coupled in parallel, wherein, every group has 4 reference transistor Tn(tetra-stacks of coupled in series).In the case, the each gate area of transistor T N1 and T1 is Wn × Ln × 8.
Connect the transistor T P0 that resistance is set to 32 times (connection resistance of transistor T P3 8 times) and there is following structure (m=2 eight stacks): two groups of reference transistor Tp coupled in parallel, wherein, every group has 8 reference transistor Tp(eight stacks of coupled in series).In the case, the gate area of transistor T P0 is Wp × Lp × 16.Similarly, connect transistor T N0 and the T0 that resistance is set to 32 times (connection resistance of transistor T N3 and T3 8 times) and there is separately following structure (m=2 eight stacks): two groups of reference transistor Tn coupled in parallel, wherein, every group has 8 reference transistor Tn(eight stacks of coupled in series).In the case, the each gate area of transistor T N0 and T0 is Wn × Ln × 16.
Therefore, according to the present embodiment, total gate area of transistor T P0 to TP5 is Wp × Lp × 42, and total gate area of transistor T N0 to TN5 is Wn × Ln × 42, and total gate area of transistor T 0 to T5 is Wn × Ln × 42.
The structure of transistor T P0 to TP5, TN0 to TN5 and T0 to T5 can be changed into example as shown in Figure 3.Only describe transistor T P0 to TP5 below in detail.Connect 64 reference transistor Tp(m=64 that transistor T P5 that resistance is set to reference resistance can use coupled in parallel).Connect 32 reference transistor Tp(m=32 that transistor T P4 that resistance is set to two times of reference resistances can use coupled in parallel).Connect 16 reference transistor Tp(m=16 that transistor T P3 that resistance is set to 4 times of reference resistances can use coupled in parallel).Connect 8 reference transistor Tp(m=8 that transistor T P2 that resistance is set to 8 times of reference resistances can use coupled in parallel).Connect 4 reference transistor Tp(m=4 that transistor T P1 that resistance is set to 16 times of reference resistances can use coupled in parallel).Connect 2 reference transistor Tp(m=2 that transistor T P0 that resistance is set to 32 times of reference resistances can use coupled in parallel).In the case, total gate area of transistor T P0 to TP5 is Wp × Lp × 126.Although omitted detailed description at this, transistor T N0 to TN5 and T0 to T5 can change similarly.
According to digital input signals D0 to D5(the logical circuit 50 that is transfused to 6 bit digital input signal D0 to D5 as shown in Figure 1, arranges code) combination producing signal DT0 to DT5, DI0 to DI5 and the DS0 to DS5 of logic level (bit value).
For example, logical circuit 50 arranges code and generates and have signal DT0 to DT5, DI0 to DI5 and the DS0 to DS5 of desired signal level according to this, makes node N0 to N5 and node NS0 to NS5 have voltage as shown in Figure 5.Fig. 5 illustrates when this code is from equaling " 0 " (, code (digital input signals D0 to D5) is set for " 000000 ") be progressively increased to each node N0 to N5 and the voltage of NS0 to NS5 and the voltage of analog signal Vo while equaling " 63 " (, code being set for " 111111 ").For the magnitude of voltage of analog signal Vo in Fig. 5, high voltage VD is 6.4[V], low-voltage GND is 0[V].For this code, decimally counting method represents the binary number by the logic level representative of digital input signals D0 to D5.Letter " H " in form represents that the voltage of corresponding node is set to high voltage VD level, and letter " L " represents that the voltage of corresponding node is set to low-voltage GND level, and mark "-" represents that corresponding node is set to open-circuit condition (high impedance status).
Next, the example of the internal structure of logical circuit 50 is described.
As shown in Figure 4, logical circuit 50 comprise inverter circuit 51, NOR circuit 52 to 55, NOR circuit 56 to 59, inverter circuit 60, XOR (EXOR) circuit 61 to 65, with non-(NAND) circuit 66 to 71 and inverter circuit 72 to 77.
The output signal as the logical inversion of digital input signals D0 is outputed to NOR circuit 56 and EXOR circuit 61 and 62 by inverter circuit 51.
NOR circuit 52 will output to NOR circuit 56 and 57 and EXOR circuit 62 and 63 as the output signal of the NOR operation result of digital input signals D0 and D1.The output signal as the NOR operation result of digital input signals D0, D1 and D2 is outputed to NOR circuit 56,57 and 58 and EXOR circuit 63 and 64 by NOR circuit 53.The output signal as the NOR operation result of digital input signals D0, D1, D2 and D3 is outputed to NOR circuit 56,57,58 and 59 and EXOR circuit 64 and 65 by NOR circuit 54.NOR circuit 55 will output to the gate terminal of the transistor T 5 in NOR circuit 56,57,58 and 59, inverter circuit 60, EXOR circuit 65 and switching circuit S5 as the output signal of the NOR operation result of digital input signals D0, D1, D2, D3 and D4.The output signal of NOR circuit 55 is signal DS5.
The 61 output conducts of EXOR circuit have the signal DS0 of the XOR result of the signal of high voltage VD level and the output signal of inverter circuit 51.EXOR circuit 62 is exported the signal DS1 as the XOR result of the output signal of the output signal of inverter circuit 51 and NOR circuit 52.EXOR circuit 63 is exported the signal DS2 as the XOR result of the output signal of the output signal of NOR circuit 52 and NOR circuit 53.EXOR circuit 64 is exported the signal DS3 as the XOR result of the output signal of the output signal of NOR circuit 53 and NOR circuit 54.EXOR circuit 65 is exported the signal DS4 as the XOR result of the output signal of the output signal of NOR circuit 54 and NOR circuit 55.
The output signal as the NOR operation result of the output signal of inverter circuit 51 and the output signal of NOR circuit 52 to 55 is outputed to NAND circuit 66 and inverter circuit 72 by NOR circuit 56.The output signal as the NOR operation result of the output signal of NOR circuit 52 to 55 is outputed to NAND circuit 67 and inverter circuit 73 by NOR circuit 57.The output signal as the NOR operation result of the output signal of NOR circuit 53 to 55 is outputed to NAND circuit 68 and inverter circuit 74 by NOR circuit 58.The output signal as the NOR operation result of the output signal of NOR circuit 54 and 55 is outputed to NAND circuit 69 and inverter circuit 75 by NOR circuit 59.The output signal as the logical inversion of the output signal of NOR circuit 55 is outputed to NAND circuit 70 and inverter circuit 76 by inverter circuit 60.
NAND circuit 66 is exported the signal DT0 as the NAND operation result of the output signal of digital input signals D0 and NOR circuit 56.NAND circuit 67 is exported the signal DT1 as the NAND operation result of the output signal of digital input signals D1 and NOR circuit 57.NAND circuit 68 is exported the signal DT3 as the NAND operation result of the output signal of digital input signals D2 and NOR circuit 58.NAND circuit 69 is exported the signal DT3 as the NAND operation result of the output signal of digital input signals D3 and NOR circuit 59.NAND circuit 70 is exported the signal DT4 as the NAND operation result of the output signal of digital input signals D4 and inverter circuit 60.NAND circuit 71 is exported as digital input signals D5 and the signal DT5 of NAND operation result of signal with high voltage VD level.
Inverter circuit 72 is exported the signal DI0 as the logical inversion of the output signal of NOR circuit 56.Inverter circuit 73 is exported the signal DI1 as the logical inversion of the output signal of NOR circuit 57.Inverter circuit 74 is exported the signal DI2 as the logical inversion of the output signal of NOR circuit 58.Inverter circuit 75 is exported the signal DI3 as the logical inversion of the output signal of NOR circuit 59.Inverter circuit 76 is exported the signal DI4 as the logical inversion of the output signal of inverter circuit 60.Inverter circuit 77 output signal DI5, DI5 is by by anti-phase the signal logic with high voltage VD that obtain and be fixed on the signal of low-voltage GND level (L level).
According to the present embodiment, resistor R0 is the example of the first resistor to R5, and resistor R10 to R15 is the example of the second resistor, and resistor R21 to R25 is the example of the 3rd resistor, resistor R20 is the example of the 4th resistor, and resistor R25 is the example of the 5th resistor.Switching circuit SW0 to SW5 is the example of the first switching circuit, and switching circuit S1 to S5 is the example of second switch circuit, and switching circuit S0 is the example of the 3rd switching circuit, and switching circuit S5 is the example of the 4th switching circuit.Logical circuit 50, inverter circuit 20 to 25 and 30 to 35 and NOR circuit 40 to 45 are examples of control circuit, transistor T N0 to TN5 is the example of the first transistor, transistor T P0 to TP5 is the example of transistor seconds, reference transistor Tn is the example of the first MOS transistor, and reference transistor Tp is the example of the second MOS transistor.Signal DT0 to DT5 and DI0 to DI5(or offer the signal of the grid of transistor T P0 to TP5 and TN0 to TN5) be the example of first signal, signal DS1 to DS5 is the example of secondary signal, signal DS0 is the example of the 3rd signal, low-voltage GND is the example of the first voltage, and high voltage VD is the example of second voltage.
As mentioned above, in the time that the figure place of the traditional R-2R type D/A converter 100 as shown in Figure 19 and Figure 21 increases, the excursion of connecting the resistance of resistance R 200 to R205 increases, and the terminal voltage of terminal a to f changes increase.In addition, for the fluctuation width of the terminal voltage of terminal a to f, obviously, near the terminal of LSB side, (for example, terminal fluctuation width f) is greater than terminal (for example, terminal fluctuation width a) near MSB side.
Figure 24 illustrates when the resistance weighting (as shown in figure 21) of connecting resistance R 205 to R200 with binary system comparison, and code is while being progressively increased to " 64 " from " 0 ", the terminal voltage of the terminal a to g retouching out for each code.Now, high voltage VD is 6.4[V], low-voltage GND is 0.0[V], therefore, ideally, each in the terminal voltage of terminal a to g has 6.4[V] or 0.0[V] magnitude of voltage.This means and depart from 6.4[V when the terminal voltage of terminal a to g] or 0.0[V] time, it is large that the fluctuation width of the terminal voltage of terminal a to g becomes.
Result from Figure 24 is clear to be found out, the terminal voltage of the terminal (for example, terminal a to c) of MSB side is depicted near 6.4[V] or 0.0[V] position (magnitude of voltage).On the other hand, in the time that terminal approaches LSB side (terminal d → e → f → g), terminal voltage is depicted in away from 6.4[V] or 0.0[V] position (magnitude of voltage).In other words,, from MSB side to LSB side, the fluctuation width of the terminal voltage of terminal a to g increases.Such reason will be explained.As mentioned above, in R-2R type D/A converter 100, from MSB side to LSB side, with binary system comparison switch 205 to 200(transistor 205a to 200a and 205b to 200b) the resistance weighting of connection resistance R 205 to R200.Now, the connection resistance of MOS transistor 205a to 200a and 205b to 200b changes according to applied magnitude of voltage.Therefore, that connects resistance R 205 to R200 arranges LSB side transistor that resistance is larger because the connection resistance of itself is large, thereby the voltage producing in its drain terminal has large fluctuation width.As a result, from MSB side to LSB side, the excursion (fluctuation range) of connecting the resistance of resistance R 205 to R200 increases.
From above obviously, in the time that the figure place in R-2R type D/A converter 100 increases, the excursion (fluctuation range) of the terminal voltage of terminal a to g increases.In addition, the increase of the excursion of the terminal voltage of terminal a to g increases the excursion (fluctuation range) of connecting resistance R 205 to R200, the problem that this causes the D/A conversion accuracy of R-2R type D/A converter 100 to worsen.
Therefore, utilize according to the D/A converter 1 of the present embodiment, the transistor (transistor of MSB side) with little connection resistance is connected as far as possible, and the transistor (transistor of LSB side) with large connection resistance is disconnected as far as possible, make it possible to export the analog signal Vo with desired voltage values according to code is set.For example, the logical circuit 50 of D/A converter 1 generates signal DT0 to DT5 and DI0 to DI5, makes according to code is set, and the node N0 to N5 of LSB side becomes open-circuit condition as far as possible.
As shown in Figure 5, according to the present embodiment, when the digital input signals D0 side from as LSB is to the digital input signals D5 side as MSB, when " 0 " has repeated one or more time, the node corresponding with the digital input signals of " 0 " of repeating is set to open-circuit condition.Relation between node N0 to N5 and the voltage of NS0 to NS5 arranging in logical circuit 50 to code and according to code is below elaborated.
First, in the time that code is " 0 ", (code=000000 is set), all numerals from LSB to MSB are all " 0 " (repeat 6 times " 0 " from LSB).In the case, the node N5 corresponding with digital input signals D5 as MSB is set to L level, and the node NS5 of the switching circuit S5 corresponding with MSB is set to L level.Then,, from being set to the node NS5 of L level, all node N0 to N4 and NS0 to NS4 in LSB side are set to open-circuit condition.For example, in the time that code is " 0 ", logical circuit 50 generates H level signal DT5, L level signal DI5 and H level signal DS5 according to code=000000 is set.In response to H level signal DT5 and L level signal DI5, transistor T P5 cut-off, and transistor T N5 connection, meanwhile, transistor T 5 is connected in response to H level signal DS5.Node N5 is couple to GND line thus, and node NS5 is couple to GND, and therefore, the voltage of node N5 and NS5 is set to L level (low-voltage GND level).Meanwhile, logical circuit 50 generates H level signal DT0 to DT4, H level signal DI0 to DI4 and L level signal DS0 to DS4 according to code=000000 is set.In response to H level signal DT0 to DT4 and H level signal DI0 to DI4, transistor T P0 to TP4 and transistor T N0 to TN4 end.Node N0 to N4 becomes open-circuit condition thus.In addition,, in response to L level signal DS0 to DS4, transistor T 0 to T4 ends.Node NS0 to NS4 becomes open-circuit condition thus.Under this voltage status (connection status), because node N0 to N5 and NS0 to NS5 are not couple to the line beyond GND line, so analog signal Vo becomes the 0.0[V corresponding with code " 0 "].
Next, in the time that code is " 1 ", (code=000001 is set), from LSB, does not repeat one or more time " 0 ".In the case, only have the node N0 corresponding with digital input signals D0 as " 1 " to be set to H level, and the node N1 to N5 corresponding with digital input signals D1 to D5 as " 0 " is set to L level.In addition, node NS0 is set to L level, and node NS1 to NS5 is set to open-circuit condition.Therefore, according to from LSB " 0 " do not repeat one or more time code, the voltage status that traditional D/A converter 100 of code=000001 is set with input arranges voltage status (connection status) similarly.For example, according to the code that does not repeat one or more time " 0 " from LSB, corresponding to digital input signals D0 to D5, node N0 to N5 is couple to respectively GND line or VD line.In addition, the node NS0 of the switching circuit S0 corresponding with LSB is couple to GND line, and the node NS1 to NS5 of other switching circuits S1 to S5 is set to open-circuit condition.
For example, the code that does not repeat one or more time " 0 " in response to basis from LSB is always the digital input signals D0(LSB of " 1 "), logical circuit 50 is exported L level signal DS0 and H level signal DS1 to DS5.Transistor T 0 is connected in response to L level signal DS0, and transistor T 1 to T5 ends in response to H level signal DS1 to DS5.Node NS0 is couple to GND line thus, and the voltage of node NS0 is set to L level (low-voltage GND level), and node NS1 to NS5 is set to open-circuit condition.
In addition, in response to the digital input signals D0 as " 1 ", logical circuit 50 generates signal DT0, DT1, DT2, DT3, DT4 and DT5, and generate L level signal DI0 to DI5, wherein, signal DT0, DT1, DT2, DT3, DT4 and DT5 have the logic level by the logic level logical inversion of digital input signals D0, D1, D2, D3, D4 and D5 is obtained.In the time that digital input signals D1 to D5 is " 0 ", H level signal is provided for transistor T P1 to TP5 and TN1 to TN5 thus, and in the time that digital input signals D0 to D5 is " 1 ", L level signal is provided for transistor T P1 to TP5 and TN0 to TN5.
In the present embodiment, in response to the digital input signals D0 as " 1 ", in logical circuit 50, generate L level signal DT0 and L level signal DI0, and in response to L level signal DT0 to DI0, transistor T P0 connects and transistor T N0 cut-off.Node N0 is couple to VD line thus, and node N0 is set to H level (high voltage VD level).In addition, in response to the digital input signals D1 to D5 as " 0 ", in logical circuit 50, generate H level signal DT1 to DT5 and L level signal DI1 to DI5, and in response to signal DT1 to DT5 and DI1 to DI5, transistor T P1 to TP5 cut-off and transistor T N1 to TN5 connects.Node N1 to N5 is couple to GND line thus, and node N1 to N5 is set to L level (low-voltage GND level).
Under such connection status, analog signal Vo becomes the 0.1[V corresponding with code " 1 "].
Next, in the time that code is " 2 ", (code=000010 is set), from LSB, " 0 " occurs once.In the case, become for the first time afterwards the corresponding node NS1 of the digital input signals D1 of " 1 " and be set to L level with repeat one or more time " 0 " from LSB, and the node N0 and the NS0 that are arranged at the LSB side of node NS1 are set to open-circuit condition.In addition, the node N1 corresponding with digital input signals D1 as " 1 " is set to H level, and the node N2 to N5 corresponding with digital input signals D2 to D5 as " 0 " is set to L level.Then, the node NS2 to NS5 being set to beyond the node NS1 of L level is set to open-circuit condition.In other words, from LSB " 0 " be set similarly repeat to become for the first time after one or more time the voltage status (connection status) of the MSB side (high-order side) of the digital input signals D1 of " 1 " with the voltage status of traditional D/A converter 100 of input digital input signals D1 to D5=00001.Under connection status as above, the node N2 to N5 corresponding with digital input signals D2 to D5 as " 0 " is couple to GND line, the node N1 corresponding with digital input signals D1 as " 1 " is couple to VD line, and node NS1, the N0 of the LSB side of node N1 and NS0 are not couple to VD line, but be couple to GND line.Therefore the impedance phase of the impedance of, seeing from the lead-out terminal of D/A converter 1 when digital input signals D0 to D5=000010 is input to traditional D/A converter 100 with.Meanwhile, with the digital input signals D0(LSB as " 0 ") corresponding transistor T N0 and T0 disconnect, node N0 and NS0 are set to open-circuit condition, and the switching circuit S1(transistor T 1 corresponding with the digital input signals D1 of high bit) connect.Therefore, disconnect in LSB side and transistor T N0 and the T0 with larger connection resistance, connect in MSB side and the transistor T 1 with less connection resistance and variation.The variation of connecting thus resistance can entirety reduce, and can suppress the reduction of the D/A conversion accuracy being caused by this variation.Therefore, can generate the 0.2[V corresponding with code " 2 " with high accuracy] analog signal Vo.
Next, in the time that code is " 3 ", (code=000011 is set), from LSB, does not repeat one or more time " 0 ".In the case, only have the node N0 corresponding with digital input signals D0 as " 1 " to be set to H level, and the node N1 to N5 corresponding with digital input signals D1 to D5 as " 0 " is set to L level.In addition, node NS0 is set to L level, and node NS1 to NS5 is set to open-circuit condition.In other words, be similar to the situation of node " 1 ", the voltage status that traditional D/A converter of code=000011 is set with input arranges voltage status (connection status) similarly.Under such connection status, analog signal Vo becomes the 0.3[V corresponding with code " 3 "].
Next, in the time that code is " 4 ", (code=000100 is set), from LSB, " 0 " occurs twice.In the case, the node NS2 of the switching circuit S2 corresponding with the digital input signals D2 that becomes for the first time afterwards " 1 " from LSB repetition " 0 " is set to L level, and from node NS2, node N1, the NS1, N0 and the NS0 that are arranged at LSB side are set to open-circuit condition.In addition, the node N2 corresponding with digital input signals D2 as " 1 " is set to H level, and the node N3 to N5 corresponding with digital input signals D3 to D5 as " 0 " is set to L level.Then,, except being set to the node NS2 of L level, node NS3 to NS5 is set to open-circuit condition.In other words, with the voltage status of traditional D/A converter 100 of input digital input signals D2 to D5=0001, repetition from LSB " 0 " is set similarly and becomes for the first time afterwards the voltage status (connection status) of the MSB side of the digital input signals D2 of " 1 " (high-order side).Under connection status as above, the node N3 to N5 corresponding with digital input signals D3 to D5 as " 0 " is couple to GND line, the node N2 corresponding with digital input signals D2 as " 1 " is couple to VD line, and node NS2, N1, NS1, N0 and the NS0 of the LSB side of node N2 are not couple to VD line, but be couple to GND line.Therefore the impedance phase of the impedance of, seeing from the lead-out terminal of D/A converter 1 when digital input signals D0 to D5=000010 is input to traditional D/A converter 100 with.Simultaneously, transistor T N0, TP0, T0, TN1, TP1 and the T1 corresponding with digital input signals D0 as " 0 " and D1 disconnect, node N0, NS0, N1 and NS1 are set to open-circuit condition, and the switching circuit S2(transistor T 2 corresponding with the digital input signals D2 of high bit) connect.Therefore, disconnect in LSB side and transistor T N0, T0, TN1 and the T1 with larger connection resistance, connect in MSB side and the transistor T 2 with less connection resistance and variation.The variation of connecting thus resistance can entirety reduce, and the reduction of the D/A conversion accuracy being caused by this variation can be suppressed.Therefore, can generate the 0.2[V corresponding with code " 2 " with high accuracy] analog signal Vo.
As mentioned above, according to from LSB " 0 " repeated one or more time code, any becoming for the first time afterwards in the corresponding node NS1 to NS5 of the digital input signals of " 1 " with repetition from LSB " 0 " is set to L level, and all nodes that are arranged at the LSB side of this node that is set to L level are all set to open-circuit condition (referring to the dotted line frame in Fig. 5).With the voltage status of traditional D/A converter 100, the voltage status (connection status) of the MSB side (high-order side) of the digital input signals that becomes " 1 " is set for the first time similarly.Now, in the middle of the transistor T 0 to T5 of switching circuit S0 to S5, only have a transistor to connect.Therefore, in the time that " 0 " repeats one or more time from LSB, be positioned at LSB side and be set to open-circuit condition corresponding to the node of the digital input signals as " 0 ", the transistor of the large connection resistance of having of LSB side is disconnected as far as possible.
Similarly, for follow-up code, as shown in Figure 5, according to the voltage that code (digital input signals D0 to D5) is set arranges node N0 to N5 and NS0 to NS5.
Repeat the code of one or more time by describing basis " 0 " from LSB below, the node of LSB side has been set to as far as possible to the effect of open-circuit condition.
First, the problem of traditional D/A converter 100 is described.As mentioned above, in R-2R type D/A converter 100, from MSB side to LSB side, with binary system comparison switch 205 to 200(transistor 205a to 200a and 205b to 200b) the resistance weighting of connection resistance R 205 to R200.In the time that the connection resistance of transistor 205a to 200a and 205b to 200b changes according to applied magnitude of voltage, its voltage that resistance generates because their connection resistance itself is large compared with the transistor of large LSB side in its drain terminal that arranges of connecting resistance R 205 to R200 has large fluctuation width.As a result, from MSB side to LSB side, the excursion (fluctuation range) of connecting the resistance of resistance R 205 to R200 increases.In the time that the variation of the connection resistance of transistor 205a to 200a and 205b to 200b increases like this, the binary weighting between position is than significantly worsening.
Fig. 7 A illustrates the example of traditional D/A converter, wherein, increases than the excursion of the connection resistance of the switch of weighting 205 to 200 and 210 with binary system from MSB side to LSB side.In Fig. 7 A, in switch 205 to 200 and 210, the percentage that resistance departs from the excursion that resistance is set is connected in the numeric representation of each.
When inputing to D/A converter 100 as shown in Figure 7 A according to the digital input signals D0 to D5=100000 of code " 32 ", for example, as shown in Figure 7 B, only have node a to be couple to VD line, and node b to g is couple to GND line.Now, in GND line side, in switch 204 to 200 and 210,2%, 3%, 4%, 5%, 6% and 6% variation is by comprehensive.This causes the problem that excursion increases and D/A conversion accuracy worsens at the connection resistance of GND line side switch 204 to 200 and 210.
Meanwhile, Fig. 6 A illustrates according to the example of the D/A converter 1 of the present embodiment, and wherein from MSB side to LSB side, the excursion of the connection resistance of switching circuit SW5 to SW0 and S5 to S0 increases.In Fig. 6 A, in switching circuit SW0 to SW5 and S0 to S5 numeric representation transistor T P0 to TP5, TN0 to TN5 in each and T0 to T5, the connection resistance of each departs from the percentage of the excursion that resistance is set.
When being input to D/A converter 1 as shown in Figure 6A according to the digital input signals D0 to D5=100000 of code " 32 ", as shown in Figure 6B, the node NS5 that becomes for the first time afterwards the corresponding switching circuit S5 of the digital input signals D5 of " 1 " with repetition from LSB " 0 " is set to L level.In addition, the node N5 corresponding with digital input signals D5 as " 1 " is set to H level.Then all node N0 to N4 and the NS0 to NS4 that, are arranged at the LSB side of the node NS5 that is set to L level are set to open-circuit condition.Thereby, as shown in Figure 6B, only have node N5 to be couple to VD line, and only have node NS5 to be couple to GND line.Therefore, be only couple to GND line at the switching circuit S5 of MSB side and connection resistance variations little (being 1% in the case).Therefore, contrary by comprehensive traditional D/A converter 100 with the variation in GND line side 2% to 6%, only there is transistor (being transistor T P5 and the T5 in the case) current flowing of little excursion and little connection resistance, thereby produce analog signal Vo.As a result, by compared with comprehensive traditional D/A converter 100, can generate analog signal Vo with variation in GND line side 2% to 6% with better D/A conversion accuracy.Therefore, can generate the 3.2[V corresponding with code " 32 " with higher precision] analog signal Vo.
Next, with reference to Fig. 8 to Figure 11, the relation between variation and the DNL characteristic occurring in the connection resistance of switching circuit SW0 to SW5 and S0 to S5 is described.
Fig. 8 A illustrates the D/A converter 1 according to the present embodiment, wherein in the connection resistance of switching circuit SW5 to SW0 and S5 to S0, occurs large variation.For example, all connection resistance of switching circuit SW5 to SW0 and S5 to S0 are all resistance " D " as shown in Figure 2, that is, and and the resistance of the octuple of the reference resistance of transistor T P5, TN5 and T5.Therefore, the connection resistance of switching circuit SW5 to SW0 and switching circuit S5 to S0 not with binary system than weighting, and connect resistance variation increase.Fig. 9 A illustrates traditional D/A converter 100, wherein, similar with the D/A converter 1 shown in Fig. 8 A, in the connection resistance of switch 205 to 200 and 210, occurs large variation.For example, the connection resistance of switch 205 to 200 and 210 is all resistance " D " as shown in Figure 2.
Fig. 8 B illustrates the DNL waveform of D/A converter 1 as shown in Figure 8 A, and Fig. 9 B illustrates the DNL waveform of D/A converter 100 as shown in Figure 9 A.These DNL waveforms illustrate the DNL(longitudinal axis about each code (transverse axis)) size.
As shown in the DNL waveform of Fig. 9 B, for D/A converter 100 as shown in Figure 9 A, there is large crest waveform in every four codes (code=4,8,12,16,20,24,28,32,36,40,44,48,52,56 and 60).For example, according to D/A converter 100, there is large crest waveform in every 16 codes (code 16,32 and 48).And for the node of LSB side is set to as far as possible open-circuit condition according to the D/A converter 1 of the present embodiment, as shown in Figure 8 B, according to from LSB " 0 " repeat one or more time code, the peak value of the crest waveform that every four codes occur is less.For example, utilize D/A converter 1, the peak value of the crest waveform that every 16 codes occur is significantly less than the peak value of the crest waveform of traditional D/A converter 100.This is because the code of emersion wave spike shape is that repeat twice or code more frequently " 0 " from LSB, and according to these codes, reduces the variation of GND line side joint energising resistance by the node of LSB side being set to as much as possible to open-circuit condition.Compared with traditional D/A converter 100, as mentioned above, according to the D/A converter 1 of the present embodiment, because the peak value of crest waveform is less, the fluctuation width (peak to peak) of DNL is also less.Compared with traditional D/A converter 100, D/A converter 1 is by being that open-circuit condition significantly improves DNL characteristic as far as possible by the Node configuration of LSB side.
Figure 10 A illustrates the D/A converter 1 according to the present embodiment, wherein in the connection resistance of switching circuit SW5 to SW0 and S5 to S0, occurs large variation.For example, in Figure 10 A, the connection resistance of switching circuit SW5, SW4, SW3, SW2, SW1 and SW0 depart from the excursion that resistance is set be respectively-1% ,-2% ,-3% ,+4% ,+5% and+6%.Similarly, the connection resistance of switching circuit S5, S4, S3, S2, S1 and S0 depart from the excursion that resistance is set be respectively-1% ,-2% ,-3% ,+4% ,+5% and+6%.In Figure 10 A, the connection resistance of switching circuit SW5 to SW0 and S5 to S0 all changes subtracting (-) direction and adding in (+) direction.Figure 11 A illustrates traditional D/A converter 100, wherein, similar with the D/A converter 1 shown in Figure 10 A, in the connection resistance of switch 205 to 200, occurs large variation.For example, with binary system than the excursion of the connection resistance of the switch of weighting 205,204,203,202,201 and 200 be respectively-1% ,-2% ,-3% ,+4% ,+5% and+6%.
Figure 10 B illustrates the DNL waveform of D/A converter 1 as shown in Figure 10 A, and Figure 11 B illustrates the DNL waveform of D/A converter 100 as shown in Figure 11 A.
As shown in the DNL waveform in Figure 11 B, according to the D/A converter 100 shown in Figure 11 A, there is large crest waveform in every four codes (code=4,8,12,16,20,24,28,32,36,40,44,48,52,56 and 60).For example, according to D/A converter 100, start every 16 codes (code 8,24,40 and 56) from code " 8 " and occur large crest waveform.When code changes to " 8 " from " 7 ", change to " 24 " from " 23 ", change to " 40 " and in the time that " 55 " change to " 56 ", occur large DNL from " 39 ".For example, large DNL occurs in the time that code changes, the digital input signals D0 to D2 that is wherein imported into switch 200 to 202 changes to L level from H level subtracting in direction, and the digital input signals D3 that is imported into switch 203 changes to H level from L level adding in direction.On the contrary, as shown in Figure 10 B, according to the D/A converter 1 of the present embodiment, the peak value of the crest waveform that every four codes occur is less.For example, utilize D/A converter 1, the peak value that starts the crest waveform that every 16 codes occur from code " 8 " is obviously less.Can think, this is to be " 0 " code in triplicate from LSB because of code " 8 ", " 24 ", " 40 " and " 56 ", and according to these codes, the node of LSB side is set to open-circuit condition as far as possible.By being open-circuit condition by these Node configurations like this, can reduce the variation of the connection resistance of GND line side, and only have (in the case for subtracting direction) vicissitudinous switching circuit SW3 to SW5 and S3 in the same direction can be couple to VD line or GND line.Compared with traditional D/A converter 100, utilize according to the D/A converter 1 of the present embodiment, as mentioned above, because the peak value of waveform is less, the fluctuation width (peak to peak) of DNL is less.Compared with traditional D/A converter, by the node of LSB side is set to open-circuit condition as far as possible, even connect resistance in direction and all change adding direction and subtract, also can significantly improve DNL characteristic according to the D/A converter 1 of the present embodiment.
Embodiment described so far can provide following effect.
The resistor R20 to R25 of the first terminal that is couple to the resistor R10 to R15 separately with resistance 2R is provided, and inserts and couple switching circuit S0 to S5 between the second terminal of resistor R20 to R25 and GND line.For example, provide " the resistor R20 to R25 in switching circuit S0 to S5 and resistor T0 to T5(pull down switch) ", and they are coupled in parallel to respectively " resistor R10 to R15 and the transistor T N0 to TN5(separately in switching circuit SW0 to SW5 with resistance 2R pull down switch) ".In addition the each switching circuit SW0 to SW5 that, is couple to resistor R10 to R15 is tri-state buffer circuit.In addition, according to from LSB " 0 " repeat one or more time code, any becoming for the first time afterwards in the corresponding node NS1 to NS5 of the digital input signals of " 1 " with repetition from LSB " 0 " is set to L level, and all nodes that are arranged at the LSB side of the node that is set to L level are set to open-circuit condition.Therefore, there is large connection resistance and the transistor of excursion (transistor of LSB side) is disconnected as far as possible, and there is little connection resistance and the transistor of transformation range (transistor of MSB side) is connected.In the time that the transistor of LSB side is disconnected, the transistorized connection resistance of disconnecting does not affect D/A converter precision, therefore, can ignore these and connect resistance.As a result, in the time that the transistor of LSB side is disconnected, compared with situation about connecting with these transistors, the variation that the transistorized connection resistance (easily causing the connection resistance of variation) of disconnecting can reduce to connect resistance.Therefore,, even if D/A converter 1 median increases, also can suppress to increase with figure place the increase of connection resistance variations together.
By reduce transistor T P0 to TP5 and TN0 to TN5 in switching circuit SW0 to SW5 connection resistance resistance (absolute value) is set, also can reduce the excursion of the connection resistance of switching circuit SW0 to SW5.But, for reduce transistor T P0 to TP5 and TN0 to TN5 connection resistance resistance is set, must increase the channel width of each transistor T P0 to TP5 and TN0 to TN5.The increase of the channel width of transistor T P0 to TP5 and TN0 to TN5 will increase element area and the circuit area of D/A converter 1.
On the contrary, D/A converter 1 can, in the case of the element area that does not increase transistor T P0 to TP5 and TN0 to TN5, suppress the increase of the connection resistance variations of the switching circuit SW0 to SW5 causing due to figure place increase.Therefore,, in the time needing the D/A conversion accuracy of par, compared with the area of D/A converter 100, can reduce the area of D/A converter 1.
Multiple reference transistor Tp and Tn coupled in parallel are so that low connection resistance to be set, and multiple reference transistor Tp and Tn coupled in series are to arrange high connection resistance.Therefore, can suppress the increase of circuit area.For example, when by only using being connected in parallel of reference transistor Tp and Tn, connect resistance with binary system comparison and add temporary,, when the number docking energising resistance of the reference transistor Tp by coupled in parallel and Tn adds temporary, as shown in Figure 3, total gate area becomes Wp × Lp × 126+Wn × Ln × 252.Similarly, in the time that the transistor size of transistor T P0 to TP5, TN0 to TN5 and T0 to T5 is set to binary system than the size of weighting, total gate area becomes Wp × Lp × 126+Wn × Ln × 252.And when by using being connected in parallel and being connected in series of reference transistor Tp and Tn, connect resistance with binary system comparison to add temporary, as shown in Figure 2, total gate area becomes Wp × Lp × 42+Wn × Ln × 84.Therefore, by using being connected in series of reference transistor Tp and Tn, the increase of suppressor grid area better.
In the time calculating the reference transistor Tp of coupled in series and the connection resistance of Tn, reference transistor Tp and Tn are connected in series the increase corresponding to channel length Lp and the Ln of reference transistor Tp and Tn, but in fact, channel length Lp and Ln do not increase physically.Therefore,, in the time of reference transistor Tp and Tn coupled in series, easily cause the difference of manufacture and the variation of connecting resistance.As shown in Figure 2, transistor T P0 to TP2, the TN0 to TN2 of LSB side and T0 to T2 adopt the structure of reference transistor Tp and Tn coupled in series.Therefore, easily cause the connection resistance variations of transistor T P0 to TP2, TN0 to TN2 and the T0 to T2 of LSB side.
But, even if adopt this structure, also can generate analog signal Vo with good D/A conversion accuracy according to the D/A converter 1 of the present embodiment.The following describes its reason.
First,, according to D/A converter 1, in LSB side and easily cause that connecting the transistor of resistance variations disconnects as far as possible, and the switching circuit S1 to S5 that is arranged at MSB side connects as far as possible.Therefore, in the time that the transistor of LSB side is disconnected, the transistorized connection resistance of disconnecting does not affect D/A conversion accuracy, and can ignore these and connect resistance.As a result, in the time that the transistor of LSB side is disconnected, compared with situation about connecting with these transistors, the variation that the transistorized connection resistance (easily causing the connection resistance of variation) of disconnecting can reduce to connect resistance.Therefore,, even in the time that transistor T P0 to TP2, the TN0 to TN2 of LSB side and the connection resistance of T0 to T2 easily occur changing, also can suppress preferably reducing of the D/A conversion accuracy that caused by this variation.
In addition, according to R-2R type D/A converter, the impact of the variation of LSB side joint energising resistance the is less than MSB side variation of connection resistance on the impact of DNL characteristic on DNL characteristic.Describe as an example of traditional D/A converter 100 example.
Figure 25 illustrates the DNL waveform of traditional D/A converter 100 as shown in figure 21, wherein with binary system than the connection resistance R 205 of weighting to R200, the resistance that only has the connection resistance R 205 corresponding with MSB is with respect to resistance variations being set 10%.For example, Figure 25 shows the DNL waveform in following situation: connect the resistance that arranges of resistance R 205 to R200 and be respectively 0.2[k Ω], 0.4[k Ω], 0.8[k Ω], 1.6[k Ω], 3.2[k Ω] and 6.4[k Ω], and only have the connection resistance of connecting resistance R 205 with respect to resistance variations is set+10% and be 0.22[k Ω].In addition, Figure 26 illustrates the DNL waveform of traditional D/A converter 100 as shown in figure 21, wherein, with binary system than the connection resistance R 200 of weighting to R205, the resistance that only has the connection resistance R corresponding with LSB 200 and connect resistance R 210 with respect to resistance variations is set+10%.For example, Figure 26 illustrates the DNL waveform in following situation: the resistance that arranges of connecting resistance R 205 to R200 and R210 is respectively 0.2[k Ω], 0.4[k Ω], 0.8[k Ω], 1.6[k Ω], 3.2[k Ω], 6.4[k Ω] and 6.4[k Ω], and only have the resistance of connecting resistance R 200 and R210 with respect to reference resistance changed+10% and be 7.04[k Ω].Therefore, when LSB side and there is the higher connection resistance R 200 that resistance is set and changed+10% time, connection resistance R 205 that to connect resistance be MSB side with respect to the absolute value that resistance variations is set changed+32(25 of absolute value 10% time) doubly.
In DNL waveform as shown in figure 25, in the time there is following code change, DNL characteristic significantly worsens: switching will be provided for the signal level (, in the time that code is switched to " 32 " from " 31 ") of the digital input signals D5 of the have+10% connection resistance R 205 changing.And in DNL waveform as shown in figure 24, while there is following code change, DNL characteristic significantly worsens: the signal level of only switching the digital input signals D0 that will be provided for the have+10% connection resistance R 200 changing.Obviously find out from Figure 25 and Figure 26, between DNL waveform as shown in figure 25 and DNL waveform as shown in figure 26, the fluctuation width (peak to peak) of DNL is mutually the same.Although between Figure 25 and Figure 26, to connect resistance and differ 32 times with respect to the absolute value that resistance is set, the fluctuation width of DNL is equal to each other.Therefore, obviously, the variation of the connection resistance of LSB side is less 32 times on the impact of DNL characteristic than the variation of the connection resistance of MSB side on the impact of DNL characteristic.
As mentioned above, the impact of the variation of the connection resistance of LSB side the is less than MSB side variation of connection resistance on the impact of DNL characteristic on DNL characteristic, therefore, even in the time easily occurring changing in the transistorized connection resistance of LSB side, also can suppress preferably the decline of the D/A conversion accuracy causing due to this variation.
Without departing from the spirit and scope of the present invention in the situation that, can realize the present invention with many other particular forms, this is apparent for a person skilled in the art.For example, should be appreciated that the present invention can adopt following form.
According to the abovementioned embodiments of the present invention, resistor R21 to R25 is set, resistor R21 to R21 is couple to the first terminal of all resistor R11 to R15 except resistor R10 in the middle of multiple resistor R10 to R15 separately with resistance 2R, and the first terminal of resistor R10 is couple to the first lead-out terminal (the first terminal of resistor R0).This is not restrictive, for example, the 1A of D/A converter as shown in figure 12 can be provided, wherein resistor R21 and R22(the 3rd resistor) be couple to the first terminal of some resistors (being resistor R11 and R12 in the case: the second resistor) in the middle of resistor R11 to R15 and switching circuit S1 and S2(second switch circuit) can be couple to resistor R21 and R22.In other words,, according to D/A converter 1A, omitted resistor R23, R24 and R25 and switching circuit S3, S4 and the S5 of D/A converter 1 as shown in Figure 1.
Utilize such D/A converter 1A, the transistor (transistor of LSB side) with large connection resistance is disconnected as far as possible, thereby exports the analog signal Vo with desired voltage values according to code is set.For example, according to from LSB to first of the digital input signals D2(than corresponding with the resistor R21 of the first terminal that is couple to resistor R22) the digital input signals D1 " 0 " of low repeats, and the code that " 1 " occurs as digital input signals D2, node N1, N0, NS1 and the NS0 corresponding with digital input signals D0 and D1 are set to high impedance.According to this code, the switching circuit S2 corresponding with digital input signals D2 connects, and node NS2 is set to L level.In addition, according to from LSB to first of the digital input signals D1(than corresponding with the resistor R11 of the first terminal that is couple to resistor R21) the digital input signals D0(second of low) " 0 " repeat, and the code that " 1 " occurs as digital input signals D1, node N0 and the NS0 corresponding with digital input signals D0 are set to high impedance.In other words, be that " 0 " and digital input signals D1 are the codes of " 1 " according to LSB, node N0 and NS0 are set to high impedance status.According to this code, the switching circuit S1 corresponding with digital input signals D1 connects and node NS1 is set to L level.Meanwhile, be different from switching circuit S1, switching circuit S2 cut-off, and node NS2 is set to high impedance status.
Therefore, the transistor (transistor of LSB side) with large connection resistance is disconnected as far as possible, and has little connection resistance and variation and connect at the transistor of MSB side, thereby effect similar to the above embodiments is provided.In DNL waveform as shown in figure 13, be set to the code of high impedance status according to node N1, N0, NS1 and NS0, DNL has the value that approaches zero.Therefore, D/A converter 1A can obtain good DNL characteristic.Figure 13 illustrates when adding the temporary DNL waveform of D/A converter 1A with the connection resistance of binary system comparison switching circuit SW5 to SW0.
Figure 14 A illustrates following D/A converter 1A, wherein, in the connection resistance of the switching circuit SW2 to SW0 in the middle of switching circuit SW5 to SW0 and S2 to S0 and S2 to S0, occurs large variation.For example, the connection resistance of switching circuit SW5 to SW2 is resistance " A ", " B ", " C " and " D " as shown in Figure 2, that is, with respect to the reference resistance of switching circuit SW5 with binary system than these resistance of weighting.And the connection resistance of switching circuit SW2 to SW0 and S2 to S0 is all resistance " D " as shown in Figure 2.Therefore, the connection resistance of switching circuit SW2 to SW0 and S2 to S0 not with binary system than weighting, and connect resistance variation increase.Figure 15 A illustrates traditional D/A converter 100, wherein, similar with the D/A converter 1A shown in Figure 14 A, in the connection resistance of switch 202 to 200 and 210, occurs large variation.For example, the connection resistance of switch 205,204,203 and 202 is resistance " A ", " B ", " C " and " D " as shown in Figure 2, and the resistance of switch 202,201,200 and 210 is all resistance " D ".
Figure 14 B illustrates the DNL waveform of D/A converter 1A as shown in Figure 14 A, and Figure 15 B illustrates the DNL waveform of the D/A converter 100 as shown in Figure 15 A.
As shown in the DNL waveform of Figure 15 B, utilize the D/A converter 100 as shown in Figure 15 A, there is large crest waveform in every two codes.For example, start every eight codes (code 4,12,20,28,36,44,52 and 60) from code 4 and occur large crest waveform.In the time there is following code change, there is large DNL: digital input signals D0 and the D1 that be imported into the switch 200 and 201 with large connection resistance variations change to " 0 " from " 1 ", for example, in the time that code changes to " 4 " from " 3 ".And utilize D/A converter 1A as shown in Figure 14 A, as shown in Figure 14B, the peak value of the crest waveform that every two codes occur is less.For example, utilize D/A converter 1A, the peak value that starts the crest waveform that every eight codes occur from code " 4 " is obviously less.Can think, this is because be set to as far as possible open-circuit condition according to the node of code 4,12,20,28,36,44,52 and 60, LSB side, thereby can reduce the variation of the connection resistance of GND line side.
According to above-mentioned variation, provide resistor R21 and the R22 of the first terminal of multiple resistor R11 of being couple in the middle of resistor R11 to R15 and R12.But this is not restrictive.For example, D/A converter 1B as shown in figure 16, resistor R22(the 3rd resistor of the first terminal that one of is couple in resistor R11 to R15 (being resistor R12 in the case: the second resistor) is provided), and switching circuit S2(second switch circuit) be couple to resistor R22.In other words, utilize D/A converter 1B, omitted resistor R21 and switching circuit S1 in D/A converter 1A as shown in figure 12.
Utilize such D/A converter 1B, the transistor (transistor of LSB side) with large connection resistance is disconnected as far as possible, to export the analog signal Vo with desired voltage values according to code is set.For example, according to from LSB to first of the digital input signals D2(than corresponding with the resistor R12 of the first terminal that is couple to resistor R22) the digital input signals D1 " 0 " of low repeats, and the code that " 1 " occurs as digital input signals D2, node N1, N0, NS1 and the NS0 corresponding with digital input signals D0 and D1 are set to high impedance status.According to this code, the switching circuit S2 corresponding with digital input signals D2 connects and node NS2 is set to L level.
Therefore, the transistor (transistor of LSB side) with large connection resistance is disconnected as far as possible, and connects at the transistor of the little connection resistance of having of MSB side and variation, thereby provides and the similar effect of effect of above-described embodiment.
Figure 17 A illustrates D/A converter 1B, wherein in the connection resistance of switching circuit SW2 to SW0, the S2 in the middle of switching circuit SW5 to SW0, S2 and S0 and S0, occurs large variation.For example, the connection resistance of switching circuit SW5 to SW2 is resistance " A ", " B ", " C " and " D " as shown in Figure 2, that is, with respect to the reference voltage of switching circuit SW5 with binary system than the resistance of weighting.And the connection resistance of switching circuit SW2 to SW0, S2 and S0 is all resistance " D " as shown in Figure 2.Therefore, the connection resistance of switching circuit SW2 to SW0, S2 and S0 not with binary system than weighting, and these connect resistance variations increase.
Figure 17 B illustrates the DNL waveform of D/A converter 1B as shown in Figure 17 A, and Figure 17 C illustrates the DNL waveform (referring to dotted line) of the DNL waveform (referring to chain-dotted line) of the DNL waveform (referring to solid line) of D/A converter 1A as shown in Figure 14 A, D/A converter 1B as shown in Figure 17 A and the traditional D/A converter 100 as shown in Figure 15 A.Figure 17 C amplification illustrates according to the DNL of code " 0 " to " 16 ".
Utilize D/A converter 1B as shown in Figure 17 B, the peak value that starts the crest waveform that every eight codes occur from code " 4 " is less than the peak value of the crest waveform of the traditional D/A converter 100 as shown in Figure 15 B.Can think, this is because be set to as far as possible open-circuit condition according to the node of code 4,12,20,28,36,44,52 and 60, LSB side, thereby can reduce the variation of the connection resistance of GND line side.
In addition, as shown in Figure 17 C, utilize as the D/A converter 1A and the 1B that illustrate respectively in Figure 14 A and Figure 17 B, be less than the DNL of traditional D/A converter 100 according to the DNL of code 4,12,20,28,36,44,52 and 60.In addition, utilize D/A converter 1A as shown in Figure 14 A, be less than generally the DNL of the D/A converter 1B as shown in Figure 17 B according to the DNL of the code except above-mentioned code 4,12,20,28,36,44,52 and 60.As a result, while being couple to the first terminal of a resistor R12 with resistor R22 compared with, when the multiple resistor R11 in the middle of resistor R21 and R22 are couple to resistor R11 to R15 and the first terminal of R12, can obtain obviously better DNL characteristic.
According to above-described embodiment and variation, the transistor (transistor of LSB side) with large connection resistance is disconnected as far as possible, thus according to from LSB " 0 " repeat one or more time code, output has the analog signal Vo of desired voltage values.This is not restrictive, and the transistor with large connection resistance can disconnect as far as possible, thus according to for example from LSB " 1 " repeat the code of one or more time, output has the analog signal Vo of desired voltage values.In the case, for example, as shown in figure 18, switching circuit S0 to S5 inserts and is coupled between node NS0 to NS5 and VD line.In addition, the transistor T 0 to T5 in switching circuit S0 to S5 is changed into P channel MOS transistor from N-channel MOS transistor.
Utilize D/A converter 1C as shown in figure 18, according to from LSB " 1 " repeat one or more time code, with from LSB " 1 " after repeating, become for the first time the corresponding node NS1 to NS5 of the digital input signals of " 0 " and be set to H level, and all nodes that are arranged at the LSB side of the node that is set to H level are all set to open-circuit condition.According to the digital input signals that becomes for the first time " 0 ", with the voltage status of traditional D/A converter 100, the voltage status (connection status) of MSB side (high-order side) is set similarly.Therefore, in the time that from LSB side, " 1 " repeats one or more time, the node of the LSB side corresponding with digital input signals as " 1 " is set to open-circuit condition, thereby the transistor with the high LSB side of connecting resistance is disconnected as far as possible.Therefore, can provide and the similar effect of effect of above-described embodiment.
Utilizing D/A converter 1C, is the code of " 0 " according to the digital input signals D0 as LSB, and in response to digital input signals D0 to D5, node N0 to N5 is couple to GND line or VD line.In addition, the node NS0 of the switching circuit S0 corresponding with LSB is couple to VD line, and the node NS1 to NS5 of other switching circuits S1 to S5 is set to open-circuit condition.Therefore, utilize D/A converter 1C as shown in figure 18, when code, the analog signal Vo during for " 0 " is 0.1[V], and analog signal Vo in the time that code is " 63 " is 6.4[V].
According to the variation as shown in Figure 12 and Figure 16, similar with the switching circuit SW3 to SW5 according to above-described embodiment, be couple to the switching circuit SW3 to SW5 that its first terminal is not couple to the resistor R13 to R15 of the 3rd resistor (for example, resistor R23 to R25) and also adopt tri-state buffer circuit.This is not restrictive, and be arranged at the node between resistor R1 and the R2 of the 3rd resistor (being resistor R22 in the case) of highest significant position from being couple to, the switching circuit SW3 to SW5 that is arranged at the second lead-out terminal side can change into traditional D/A converter 100 in the similar CMOS inverter circuit of switch 200 to 205.In other words, as long as when in the middle of switching circuit SW0 to SW5, at least switching circuit SW0 to SW2 is tri-state buffer circuit, switching circuit SW0 to SW2 is couple to resistor R10 to R12, wherein the first terminal of resistor R10 to R12 is coupled between the node between resistor R1 and R2 and the first lead-out terminal (the first terminal of resistor R0), is couple to resistor R1 and R2 as the first terminal of the resistance 22 of an example of the 3rd resistor.
Above-described embodiment and variation adopt 6 D/A converters 1, the 1A to 1C of R-2R resistor ladder type, but the figure place of D/A converter 1,1A to 1C can appropriate change.
According to above-described embodiment and variation, high voltage VD is set to 6.4[V], low-voltage GND is set to 0.0[V], but these magnitudes of voltage can appropriate change.
All examples of quoting herein and language with good conditionsi are all intended for the object of instruction, with the concept that helps reader more in depth to understand principle of the present invention and proposed by inventor, and not should be understood to be confined to these example of quoting especially and conditions, these examples in this specification organize the performance that does not also relate to quality of the present invention.Although described embodiments of the invention in detail, should be appreciated that without departing from the spirit and scope of the present invention in the situation that, can carry out various changes, substitutions and modifications to it.

Claims (13)

1. a digital-to-analog D/A converter, described D/A converter generates analog signal according to digital input signals, and described D/A converter comprises:
Multiple the first resistors, it is coupled in series between the first lead-out terminal and the second lead-out terminal, exports described analog signal from described the second lead-out terminal, and described the first resistor has identical resistance;
Multiple the second resistors, it comprises the first terminal that is couple to respectively described multiple the first resistors, and the resistance of each the second resistor is the twice of the resistance of described the first resistor, described the first lead-out terminal is couple to the first terminal of second resistor in described multiple the second resistor;
Multiple the first switching circuits, it is couple to respectively the second terminal of described multiple the second resistors;
The 3rd resistor, the resistance of described the 3rd resistor be described the first resistor resistance twice and comprise the first terminal, the first terminal of described the 3rd resistor is couple in the first terminal of the second resistor except being couple to second resistor of described the first lead-out terminal;
Second switch circuit, the second terminal that it comprises the first terminal of the second terminal that is couple to described the 3rd resistor and is couple to the first wire; And
Control circuit, it is couple to described the first switching circuit and described second switch circuit, and is configured to generate for controlling the first signal of described the first switching circuit and for controlling the secondary signal of described second switch circuit according to described digital input signals,
Wherein, control one or more first switching circuit that is coupled to following the second resistor in described multiple the first switching circuit, and the state that is arranged at the connected node between described one or more first switching circuit and corresponding the second resistor is set to the first voltage, be different from any in second voltage and the high impedance of described the first voltage, this second resistor is coupled to described the first lead-out terminal and the node between the connected node between two adjacent the first resistors, and the first terminal of described the 3rd resistor is coupled to this second resistor.
2. D/A converter according to claim 1, wherein each the first switching circuit comprises:
The first transistor, it is coupled in the connected node between described the first switching circuit and the second resistor of correspondence and has between the lower voltage node of described the first voltage; And
Transistor seconds, it is coupled in the connected node between described the first switching circuit and the second resistor of correspondence and has between the high voltage node of described second voltage, and
Wherein each the first switching circuit is exported described the first voltage or described second voltage according to described first signal to the connected node between described the first switching circuit and the second resistor of correspondence.
3. D/A converter according to claim 1 and 2, wherein said control circuit is connected described second switch circuit, and make each in described the first switching circuit for described high impedance, the second resistor that each in described the first switching circuit is couple to and the connected node of following the first resistor couples: this first resistor is arranged on the first lead-out terminal side of the connected node between described the 3rd resistor and described second resistor of connection.
4. D/A converter according to claim 3, wherein said control circuit makes to be couple to any connection in the multiple described second switch circuit of multiple described the 3rd resistors.
5. D/A converter according to claim 1 and 2, also comprises:
The 4th resistor, it comprises the first terminal that is couple to described the first lead-out terminal, and the resistance of described the 4th resistor is the twice of the resistance of described the first resistor; And
The 3rd switching circuit, the second terminal that it comprises the first terminal of the second terminal that is couple to described the 4th resistor and is couple to described the first wire,
Wherein said control circuit generates the 3rd signal for controlling described the 3rd switching circuit according to described digital input signals.
6. D/A converter according to claim 5, wherein, in the time that described digital input signals is expressed as follows first code: in first code, from the least significant bit of described digital input signals to as than the second of first low next bit, repeat first logic level corresponding with described the first voltage, and in described first appearance second logic level corresponding with described second voltage, described control circuit is configured to:
Generate described first signal, with between described the first switching circuit and described the second resistor be set to described high impedance from described least significant bit to the corresponding connected node in described deputy position,
Generate described first signal, to be set to described second voltage with described first corresponding connected node between described the first switching circuit and described the second resistor,
Generate described secondary signal, to connect and described first corresponding described second switch circuit, and
Generate described the 3rd signal, to make described the 3rd switching circuit cut-off.
7. D/A converter according to claim 1 and 2, wherein
Be couple to the first switching circuit of second resistor the second terminal coupling with described the first lead-out terminal corresponding to the least significant bit of described digital input signals, and
Be couple to first switching circuit of the second terminal of following the second resistor corresponding to the highest significant position of described digital input signals: another terminal that this second resistor and terminal are couple to the first resistor of described the second lead-out terminal couples.
8. D/A converter according to claim 6, wherein in the time that described digital input signals represents the code different from described first code, described control circuit generates described secondary signal, to make described second switch circuit cut-off, and generate described the 3rd signal, to connect described the 3rd switching circuit.
9. D/A converter according to claim 6, wherein
Described the 3rd resistor comprises the 5th resistor, and the first terminal of described the 5th resistor is couple to the first terminal of described second resistor corresponding with the highest significant position of described digital input signals,
Described second switch circuit comprises the 4th switching circuit of the second terminal that is couple to described the 5th resistor, and
In the time that all positions from described least significant bit to described highest significant position of described digital input signals all have described the first logic level, described control circuit is configured to:
Generate described first signal, be set to described the first voltage with the corresponding connected node with described highest significant position between described the first switching circuit and described the second resistor,
Generate described first signal, be set to described high impedance with the connected node corresponding with position except described highest significant position between described the first switching circuit and described the second resistor,
Generate described secondary signal, to connect described the 4th switching circuit, and
Generate described the 3rd signal, to make described the 3rd switching circuit cut-off.
10. D/A converter according to claim 6, wherein
Described the 3rd resistor is one of multiple described the 3rd resistors, and described second switch circuit is one of multiple described second switch circuit, and
In the time that described digital input signals represents described first code, described control circuit is configured to:
Generate described secondary signal, to connect and described first corresponding described second switch circuit,
Generate described secondary signal, to make and the corresponding described second switch circuit cut-off in position except described first, and
Generate described the 3rd signal, to make described the 3rd switching circuit cut-off.
11. D/A converters according to claim 1 and 2, wherein, for each the second resistor being couple to except the first terminal the second resistor of described the first lead-out terminal, arrange described the 3rd resistor and described second switch circuit.
12. D/A converters according to claim 1 and 2, wherein
Each in described the first switching circuit comprises: be coupled in the second terminal of described the second resistor and have the first transistor between described first wire of described the first voltage, and be coupled in the second terminal of described the second resistor and there is the transistor seconds between the second wire of described second voltage, the first transistor of described the first switching circuit has the connection resistance arranging with the ratio of two power, the transistor seconds of described the first switching circuit has the connection resistance arranging with the ratio of two power
At least described the first transistor or described transistor seconds end in response to described first signal, and
Described second switch circuit comprises the 3rd transistor, described the 3rd transistor comprise the second terminal that is couple to described the 3rd resistor the first terminal, be couple to the second terminal of described the first wire and receive the control terminal of described secondary signal.
13. D/A converters according to claim 12, wherein
At least one in described multiple the first transistor has the structure of multiple the first MOS transistor coupled in series, and
At least one in described multiple transistor seconds has the structure of multiple the second MOS transistor coupled in series.
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