CN103973100A - Positive and negative voltage generation device - Google Patents
Positive and negative voltage generation device Download PDFInfo
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- CN103973100A CN103973100A CN201310030794.1A CN201310030794A CN103973100A CN 103973100 A CN103973100 A CN 103973100A CN 201310030794 A CN201310030794 A CN 201310030794A CN 103973100 A CN103973100 A CN 103973100A
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Abstract
The invention discloses a positive and negative voltage generation device which solves the problem that the area is wasted due to the fact that a flash memory relies on a single positive voltage charge pump or a single negative voltage charge pump to generate positive high voltage or negative high voltage. The device comprises a pushing and lifting capacitor, a transfer level and a four-phase clock circuit. The pushing and lifting capacitor is connected with the transfer level, and the four-phase clock circuit is connected with the pushing and lifting capacitor. The device further comprises a first control switch and a second control switch, wherein the first control switch and the second control switch are connected with the two ends of the transfer level respectively; the first control switch comprises an NMOS tube, a PMOS tube, a VPOS PIN, a GND and an NVEN PIN; the second control switch comprises an NMOS tube, a PMOS tube, a VNEG PIN, a VDD and an NVEN PIN. The process that the device generates positive high voltage or negative high voltage is completed in only one charge pump, and the area of a chip of the flash memory is saved.
Description
Technical field
The present invention relates to memory technology field, particularly relate to a kind of generating positive and negative voltage generation device.
Background technology
In existing flash memory, there are two kinds of charge pumps, be respectively malleation charge pump and negative pressure charge pump.Rely on malleation charge pump to produce positive voltage, rely on negative pressure charge pump to produce negative voltage.If flash memory need to use positive voltage and negative voltage, malleation charge pump and negative pressure charge pump need to be set in chip simultaneously; If flash memory uses positive voltage and negative voltage when different, malleation charge pump wherein or negative pressure charge pump are by the area of waste flash memory chip.
Summary of the invention
The invention discloses a kind of generating positive and negative voltage generation device, rely on independent malleation charge pump or negative pressure charge pump to produce the problem of the area waste that positive high voltage or negative high voltage cause to solve flash memory in background technology.
In order to address the above problem, the invention discloses a kind of generating positive and negative voltage generation device, comprise and elect electric capacity, transmitting stage and four phase clock circuit, described election electric capacity is connected with described transmitting stage, described four phase clock circuit are connected with described election electric capacity, also comprise: the first control switch and the second control switch; Described the first control switch and described the second control switch are connected respectively the two ends of described transmitting stage;
Described the first control switch comprises NMOS pipe, PMOS pipe, VPOS PIN pin, GND and NVEN PIN pin;
Described the second control switch comprises NMOS pipe, PMOS pipe, VNEG PIN pin, VDD and NVEN PIN pin;
In the time that the NVEN PIN of described the first control switch and described the second control switch pin all accesses digital low level, the PMOS of described the first control switch and described the second control switch manages equal conducting, the NMOS pipe of described the first control switch and described the second control switch all disconnects, the VDD access electric charge of described the second control switch, and transmitted the VPOS PIN pin output positive high voltage of described the first control switch by described four phase clock circuit control electric charges;
In the time that the NVEN PIN of described the first control switch and described the second control switch pin all accesses digital high, the PMOS pipe of described the first control switch and described the second control switch all disconnects, the NMOS of described the first control switch and described the second control switch manages equal conducting, the GND ground connection of described the first control switch, and transmitted the VNEG PIN pin output negative high voltage of described the second control switch by described four phase clock circuit control electric charges.
Preferably, in described the first control switch, the grid of described NMOS pipe, the grid of described PMOS pipe are connected with described NVEN PIN pin, the source electrode of described NMOS pipe is connected with the source electrode of described PMOS pipe and accesses described transmitting stage, the drain electrode of described PMOS pipe is connected with described VPOS PIN pin, and the drain electrode of described NMOS pipe is connected with described GND.
Preferably, in described the second control switch, the grid of described NMOS pipe, the grid of described PMOS pipe are connected with described NVEN PIN pin, the source electrode of described NMOS pipe is connected with the source electrode of described PMOS pipe and accesses described transmitting stage, the drain electrode of described PMOS pipe is connected with described VDD, and the drain electrode of described NMOS pipe is connected with described VNEG PIN pin.
Preferably, the clock of described four phase clock circuit has predefined sequential relationship.
Preferably, two PMOS in the described election electric capacity of the pipe of a pair of NMOS in described transmitting stage and corresponding connection manage and form a MOS level.
Preferably, an adjacent separate unit of described two MOS levels composition.
Preferably, the quantity of described separate unit is directly proportional to the positive voltage value of the VPOS PIN pin output of described the first control switch, or the negative value of exporting to the VNEG PIN pin of described the second control switch is directly proportional.
Preferably, described four phase clock circuit are connected with described election electric capacity, comprising:
The shunt in described four phase clock circuit with identical sequential relationship is connected with the election electric capacity in same MOS level.
Preferably, describedly transmitted by described four phase clock circuit control electric charges, comprising:
, transmit to the direction requiring by transmitting stage according to the sequential relationship control electric charge of the clock of described four phase clock circuit.
Preferably, the electric current described in described foundation with sequential relationship pushes or draws electric charge, comprising:
In the time that the NVEN PIN of described the first control switch and described the second control switch pin all accesses digital low level, push the VPOS PIN pin of positive charge to described the first control switch from the VDD of described the second control switch;
In the time that the NVEN PIN of described the first control switch and described the second control switch pin all accesses digital high, push the VNEG PIN pin of negative electrical charge to described the second control switch from the GND of described the first control switch.
Compared with background technology, the embodiment of the present invention comprises following advantage:
By access digital high or digital low level, adjusts that PMOS in two control switchs manages and conducting and the disconnection of NMOS pipe.In the time of input digital high, the PMOS pipe conducting in two control switchs, NMOS manages disconnection, and the electric charge being accessed by four phase clock circuit controls, produces positive high voltage output; In the time of the digital low level of input, the PMOS pipe in two control switchs disconnects, and the conducting of NMOS pipe, and the electric charge being accessed by four phase clock circuit controls, produce negative high voltage output.The process that produces positive high voltage or negative high voltage only completes in a charge pump, does not need independently malleation charge pump and negative pressure charge pump, has saved the chip area of flash memory.
Meanwhile, taking separate unit as unit, increase or reduce the quantity of separate unit, can correspondingly increase or reduce the positive voltage of generation or the numerical value of negative voltage.
Brief description of the drawings
Fig. 1 shows a kind of generating positive and negative voltage generation device schematic diagram in the embodiment of the present invention;
Fig. 2 shows a kind of generating positive and negative voltage generation device schematic diagram in the embodiment of the present invention;
Fig. 3 shows four phase clock circuit sequences in the embodiment of the present invention and is related to schematic diagram.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
The embodiment of the invention discloses a kind of generating positive and negative voltage generation device, described a kind of generating positive and negative voltage generation device, is specifically as follows the charge pump for generation of generating positive and negative voltage.In described a kind of generating positive and negative voltage generation device, comprise two control switchs, by conducting or the disconnection relation of PMOS pipe and NMOS pipe in two control switchs, and the control of four phase clock circuit, correspondingly produces positive voltage or negative voltage.
Introduce in detail a kind of generating positive and negative voltage generation device disclosed by the invention below by enumerating several specific embodiments.
Embodiment mono-
Introduce in detail the disclosed a kind of generating positive and negative voltage generation device of the embodiment of the present invention.
With reference to Fig. 1, show a kind of generating positive and negative voltage generation device schematic diagram in the embodiment of the present invention.
Described a kind of generating positive and negative voltage generation device, specifically can comprise: elect electric capacity 10, transmitting stage 12, four phase clock circuit 14, the first control switch 16 and the second control switch 18.
Wherein, described election electric capacity 10 is connected with described transmitting stage 12, and described four phase clock circuit 14 are connected with described election electric capacity 10, and described the first control switch 16 and described the second control switch 18 are connected respectively the two ends of described transmitting stage 12.
Particularly, described the first control switch 16 can comprise NMOS pipe, PMOS pipe, VPOS PIN pin, GND and NVEN PIN pin.
Preferably, in described the first control switch 16, can only include a NMOS pipe, a PMOS pipe, a VPOS PIN pin, a GND and a NVEN PIN pin.
Particularly, described the second control switch 18 can comprise NMOS pipe, PMOS pipe, VNEG PIN pin, VDD and NVEN PIN pin.
Preferably, in described the second control switch 18, can only include a NMOS pipe, a PMOS pipe, a VNEG PIN pin, a VDD and a NVEN PIN pin.
Described transmitting stage 12 adopts NMOS pipe, and source is towards output port VNEG, and substrate connects source, can reduce to greatest extent threshold value loss.
Described election electric capacity 10 is substituted by PMOS pipe, and its source, drain terminal and substrate are connected together, and as a port of electric capacity, are connected to four phase clock circuit 14, and the grid of PMOS pipe is connected to transmitting stage 12.
In the time that the NVEN PIN pin of described the first control switch 16 and described the second control switch 18 all accesses digital low level, the PMOS of described the first control switch 16 and described the second control switch 18 manages equal conducting, the NMOS pipe of described the first control switch 16 and described the second control switch 18 all disconnects, the VDD access electric charge of described the second control switch 18, and control electric charge transmission by described four phase clock circuit 14, the VPOS PIN pin output positive high voltage of described the first control switch 16.
In the time that the NVEN PIN pin of described the first control switch 16 and described the second control switch 18 all accesses digital high, the PMOS pipe of described the first control switch 16 and described the second control switch 18 all disconnects, the NMOS of described the first control switch 16 and described the second control switch 18 manages equal conducting, the GND ground connection of described the first control switch 16, and control electric charge transmission by described four phase clock circuit 14, the VNEG PIN pin output negative high voltage of described the second control switch 18.
In sum, the disclosed a kind of generating positive and negative voltage generation device of the embodiment of the present invention, compared with background technology, has the following advantages:
By access digital high or digital low level, adjusts that PMOS in two control switchs manages and conducting and the disconnection of NMOS pipe.In the time of input digital high, the PMOS pipe conducting in two control switchs, NMOS manages disconnection, and the electric charge being accessed by four phase clock circuit controls, produces positive voltage output; In the time of the digital low level of input, the PMOS pipe in two control switchs disconnects, and the conducting of NMOS pipe, and the electric charge being accessed by four phase clock circuit controls, produce negative voltage output.The process that produces positive voltage or negative voltage only completes in a charge pump, does not need independently malleation charge pump and negative pressure charge pump, has saved the chip area of flash memory.
Embodiment bis-
Introduce in detail the disclosed a kind of generating positive and negative voltage generation device of the embodiment of the present invention.
With reference to Fig. 2, show a kind of generating positive and negative voltage generation device schematic diagram in the embodiment of the present invention.
Described a kind of generating positive and negative voltage generation device, specifically can comprise: elect electric capacity, transmitting stage, four phase clock circuit, the first control switch and the second control switch.
Wherein, described election electric capacity is connected with described transmitting stage.Described four phase clock circuit are connected with described election electric capacity, and particularly, the shunt in described four phase clock circuit with identical sequential relationship is connected with the election electric capacity in same MOS level.
Described the first control switch and described the second control switch are connected respectively the two ends of described transmitting stage, and the clock of described four phase clock circuit has predefined sequential relationship, and sequential relationship as shown in Figure 3.PH1-PH4 represents respectively four kinds of sequential relationships.
Particularly, described the first control switch can comprise NMOS pipe, PMOS pipe, VPOS PIN pin, GND and NVEN PIN pin.In described the first control switch, the grid of described NMOS pipe, the grid of described PMOS pipe are connected with described NVEN PIN pin, the source electrode of described NMOS pipe is connected with the source electrode of described PMOS pipe and accesses described transmitting stage, the drain electrode of described PMOS pipe is connected with described VPOS PIN pin, and the drain electrode of described NMOS pipe is connected with described GND.
Particularly, described the second control switch can comprise NMOS pipe, PMOS pipe, VNEG PIN pin, VDD and NVEN PIN pin.In described the second control switch, the grid of described NMOS pipe, the grid of described PMOS pipe are connected with described NVEN PIN pin, the source electrode of described NMOS pipe is connected with the source electrode of described PMOS pipe and accesses described transmitting stage, the drain electrode of described PMOS pipe is connected with described VDD, and the drain electrode of described NMOS pipe is connected with described VNEG PIN pin.
Described transmitting stage adopts NMOS pipe, and source is towards output port VNEG, and substrate connects source, can reduce to greatest extent threshold value loss.
Described election electric capacity is substituted by PMOS pipe, and its source, drain terminal and substrate are connected together, and as a port of electric capacity, are connected to four phase clock circuit, and the grid of PMOS pipe is connected to transmitting stage.
A pair of NMOS pipe in described transmitting stage forms a MOS level with two PMOS pipes in the described election electric capacity of corresponding connection.An adjacent separate unit of described two MOS levels composition.
The quantity of described separate unit is directly proportional to the positive voltage value of the VPOS PIN pin output of described the first control switch, or the negative value of exporting to the VNEG PIN pin of described the second control switch is directly proportional.
In Fig. 2, stage1 can be the first MOS level, stage2 can be the second MOS level, and a separate unit of the common composition of stage1 and stage2, in described a kind of generating positive and negative voltage generation device, constantly copy this separate unit, the positive voltage of generation or negative voltage are correspondingly higher.
The clock PH1 and the PH4 that are connected with stage1 are " protruding ", and the clock PH2 and the PH3 that are connected with stage2 are " recessed ".
In the time that the NVEN PIN of described the first control switch and described the second control switch pin all accesses digital low level, the PMOS of described the first control switch and described the second control switch manages equal conducting, the NMOS pipe of described the first control switch and described the second control switch all disconnects, the VDD access electric charge of described the second control switch, and transmitted the VPOS PIN pin output positive high voltage of described the first control switch by described four phase clock circuit control electric charges.
In the time that the NVEN PIN of described the first control switch and described the second control switch pin all accesses digital high, the PMOS pipe of described the first control switch and described the second control switch all disconnects, the NMOS of described the first control switch and described the second control switch manages equal conducting, the GND ground connection of described the first control switch, and transmitted the VNEG PIN pin output negative high voltage of described the second control switch by described four phase clock circuit control electric charges.
Above-mentionedly transmitted by described four phase clock circuit control electric charges, specifically can comprise:
, transmit to the direction requiring by transmitting stage according to the sequential relationship control electric charge of the clock of described four phase clock circuit.
Wherein, according to described in have sequential relationship electric current push or draw electric charge, be specifically as follows:
In the time that the NVEN PIN of described the first control switch and described the second control switch pin all accesses digital low level, push the VPOS PIN pin of positive charge to described the first control switch from the VDD of described the second control switch.
In the time that the NVEN PIN of described the first control switch and described the second control switch pin all accesses digital high, push the VNEG PIN pin of negative electrical charge to described the second control switch from the GND of described the first control switch.
In sum, the disclosed a kind of generating positive and negative voltage generation device of the embodiment of the present invention, compared with background technology, has the following advantages:
By access digital high or digital low level, adjusts that PMOS in two control switchs manages and conducting and the disconnection of NMOS pipe.In the time of input digital high, the PMOS pipe conducting in two control switchs, NMOS manages disconnection, and the electric charge being accessed by four phase clock circuit controls, produces positive voltage output; In the time of the digital low level of input, the PMOS pipe in two control switchs disconnects, and the conducting of NMOS pipe, and the electric charge being accessed by four phase clock circuit controls, produce negative voltage output.The process that produces positive voltage or negative voltage only completes in a charge pump, does not need independently malleation charge pump and negative pressure charge pump, has saved the chip area of flash memory.
Meanwhile, taking separate unit as unit, increase or reduce the quantity of separate unit, can correspondingly increase or reduce the positive voltage of generation or the numerical value of negative voltage.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, and what each embodiment stressed is and the difference of other embodiment, between each embodiment identical similar part mutually referring to.
Above to the disclosed a kind of generating positive and negative voltage generation device of the embodiment of the present invention, be described in detail, applied specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment is just for helping to understand method of the present invention and core concept thereof; , for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention meanwhile.
Claims (10)
1. a generating positive and negative voltage generation device, comprise and elect electric capacity, transmitting stage and four phase clock circuit, described election electric capacity is connected with described transmitting stage, and described four phase clock circuit are connected with described election electric capacity, it is characterized in that, also comprise: the first control switch and the second control switch; Described the first control switch and described the second control switch are connected respectively the two ends of described transmitting stage;
Described the first control switch comprises NMOS pipe, PMOS pipe, VPOS PIN pin, GND and NVEN PIN pin;
Described the second control switch comprises NMOS pipe, PMOS pipe, VNEG PIN pin, VDD and NVEN PIN pin;
In the time that the NVEN PIN of described the first control switch and described the second control switch pin all accesses digital low level, the PMOS of described the first control switch and described the second control switch manages equal conducting, the NMOS pipe of described the first control switch and described the second control switch all disconnects, the VDD access electric charge of described the second control switch, and transmitted the VPOS PIN pin output positive high voltage of described the first control switch by described four phase clock circuit control electric charges;
In the time that the NVEN PIN of described the first control switch and described the second control switch pin all accesses digital high, the PMOS pipe of described the first control switch and described the second control switch all disconnects, the NMOS of described the first control switch and described the second control switch manages equal conducting, the GND ground connection of described the first control switch, and transmitted the VNEG PIN pin output negative high voltage of described the second control switch by described four phase clock circuit control electric charges.
2. device according to claim 1, is characterized in that,
In described the first control switch, the grid of described NMOS pipe, the grid of described PMOS pipe are connected with described NVEN PIN pin, the source electrode of described NMOS pipe is connected with the source electrode of described PMOS pipe and accesses described transmitting stage, the drain electrode of described PMOS pipe is connected with described VPOS PIN pin, and the drain electrode of described NMOS pipe is connected with described GND.
3. device according to claim 1, is characterized in that,
In described the second control switch, the grid of described NMOS pipe, the grid of described PMOS pipe are connected with described NVEN PIN pin, the source electrode of described NMOS pipe is connected with the source electrode of described PMOS pipe and accesses described transmitting stage, the drain electrode of described PMOS pipe is connected with described VDD, and the drain electrode of described NMOS pipe is connected with described VNEG PIN pin.
4. device according to claim 1, is characterized in that,
The clock of described four phase clock circuit has predefined sequential relationship.
5. device according to claim 1, is characterized in that,
A pair of NMOS pipe in described transmitting stage forms a MOS level with two PMOS pipes in the described election electric capacity of corresponding connection.
6. device according to claim 5, is characterized in that,
An adjacent separate unit of described two MOS levels composition.
7. device according to claim 6, is characterized in that,
The quantity of described separate unit is directly proportional to the positive voltage value of the VPOS PIN pin output of described the first control switch, or the negative value of exporting to the VNEG PIN pin of described the second control switch is directly proportional.
8. device according to claim 5, is characterized in that, described four phase clock circuit are connected with described election electric capacity, comprising:
The shunt in described four phase clock circuit with identical sequential relationship is connected with the election electric capacity in same MOS level.
9. device according to claim 4, is characterized in that, is describedly transmitted by described four phase clock circuit control electric charges, comprising:
, transmit to the direction requiring by transmitting stage according to the sequential relationship control electric charge of the clock of described four phase clock circuit.
10. device according to claim 9, is characterized in that, the electric current described in described foundation with sequential relationship pushes or draws electric charge, comprising:
In the time that the NVEN PIN of described the first control switch and described the second control switch pin all accesses digital low level, push the VPOS PIN pin of positive charge to described the first control switch from the VDD of described the second control switch;
In the time that the NVEN PIN of described the first control switch and described the second control switch pin all accesses digital high, push the VNEG PIN pin of negative electrical charge to described the second control switch from the GND of described the first control switch.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310030794.1A CN103973100B (en) | 2013-01-25 | 2013-01-25 | Positive and negative voltage generation device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310030794.1A CN103973100B (en) | 2013-01-25 | 2013-01-25 | Positive and negative voltage generation device |
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| CN103973100A true CN103973100A (en) | 2014-08-06 |
| CN103973100B CN103973100B (en) | 2017-02-08 |
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| CN201310030794.1A Active CN103973100B (en) | 2013-01-25 | 2013-01-25 | Positive and negative voltage generation device |
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| WO2022100728A1 (en) * | 2020-11-16 | 2022-05-19 | 上海唯捷创芯电子技术有限公司 | Positive-and-negative-voltage charge pump circuit, chip and communication terminal |
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Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |