CN103972150A - Method and system for etching oxide layer on both sides of fuse structure - Google Patents
Method and system for etching oxide layer on both sides of fuse structure Download PDFInfo
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- CN103972150A CN103972150A CN201310037358.7A CN201310037358A CN103972150A CN 103972150 A CN103972150 A CN 103972150A CN 201310037358 A CN201310037358 A CN 201310037358A CN 103972150 A CN103972150 A CN 103972150A
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- etching
- fuse
- oxide layer
- wires structure
- sides
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- 238000005530 etching Methods 0.000 title claims abstract description 94
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000002161 passivation Methods 0.000 claims description 14
- 238000005259 measurement Methods 0.000 claims description 12
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 11
- 229910002091 carbon monoxide Inorganic materials 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 4
- 239000003595 mist Substances 0.000 claims description 4
- 238000012360 testing method Methods 0.000 claims description 4
- 239000004341 Octafluorocyclobutane Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 3
- 239000001569 carbon dioxide Substances 0.000 claims description 3
- 239000013256 coordination polymer Substances 0.000 claims description 3
- BCCOBQSFUDVTJQ-UHFFFAOYSA-N octafluorocyclobutane Chemical compound FC1(F)C(F)(F)C(F)(F)C1(F)F BCCOBQSFUDVTJQ-UHFFFAOYSA-N 0.000 claims description 3
- 235000019407 octafluorocyclobutane Nutrition 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000005297 pyrex Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000007849 functional defect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a method for etching an oxide layer on both sides of a fuse structure. The method includes A, arranging a measuring module matched with the fuse structure in a scribing groove; B, measuring original thickness of the oxide layer on both sides of the fuse structure through the measuring module; C, calculating quantity of the oxide layer needed to be etched according to thickness of needed residual oxide layer in a passivating layer and the original thickness; D, determining etching time according to etching speed of an etcher; E, determining etching process according to the etching time and completing etch of the oxide layer on both sides of the fuse structure. The method accurately controls quantity of the etched oxide layer on both sides of the fuse structure, prevents the fuse failure and has the advantages of high etching efficiency, short etching time and low cost.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to the method and system of a kind of etching fuse-wires structure both sides oxide layer.
Background technology
At present, microelectric technique has entered very lagre scale integrated circuit (VLSIC) and age of system integration, and microelectric technique has become the beautiful and basic of whole information age.In microelectric technique, manufacture an integrated circuit and need to pass through the operations such as integrated circuit (IC) design, mask manufacture, original material manufacture, chip manufacture, encapsulation, test.Along with the develop rapidly of integrated circuit, integrated circuit fabrication process becomes and becomes increasingly complex with meticulous, semiconductor components and devices also becomes and affected by various defect, and single components and parts are as the inefficacy of transistor or memory cell, tend to cause the functional defect of whole integrated circuit.
Conventionally the solution of using is that in integrated circuit, to form some connecting lines that can fuse be fuse (fuse) structure, to guarantee the availability of integrated circuit.Generally speaking, fuse-wires structure is for connecting the redundant circuit of integrated circuit, in the time that defect appears in circuit, by fuse failure, redundant circuit repaired or replaced the circuit that occurs defect.Fuse-wires structure, in being usually used in internal memory, in the time that memory chip has been produced, if wherein there is partial memory cell to occur function problem, just can use the memory cell of redundancy to replace by fuse-wires structure, realizes the object of repairing.In addition, fuse-wires structure is also usually used in programmable circuit, according to user's needs, uses fuse-wires structure to programme to the standard logical unit in circuit, in order to realize specific function.
In actual applications, there is the failed phenomenon that fuses in fuse sometimes, thereby cause whole circuit malfunction.Fact proved, the parameter that affects fuse failure performance is the amount of the oxide layer of etching fuse-wires structure both sides.In the time that the amount of the oxide layer of etching is excessive, will damage fuse itself; In the time that the amount of the oxide layer of etching is too small, will cause fuse to fuse.But the method for the oxide layer of traditional etching fuse-wires structure both sides can not accurately be controlled the amount of etching oxidation layer, and etching efficiency is low, consuming time longer.
Summary of the invention
For above-mentioned technical problem, the object of the present invention is to provide the method and system of a kind of etching fuse-wires structure both sides oxide layer, it can be according to actual needs, accurately control the amount of the oxide layer of fuse-wires structure both sides etching, avoid the generation of fuse failure failure phenomenon, and etching efficiency is high, consuming time short, cost is low.
For reaching this object, the present invention by the following technical solutions:
A method for etching fuse-wires structure both sides oxide layer, it comprises the steps:
A, the measurement module coordinating with fuse-wires structure is placed in scribe line;
B, measure the original thickness of fuse-wires structure both sides oxide layer by described measurement module;
C, need residual oxidated layer thickness and described original thickness according to passivation layer, calculate the amount of the oxide layer of required etching;
D, according to the etching speed of etching machine, determine etch period;
E, determine etching processing procedure according to described etch period, complete the etching of fuse-wires structure both sides oxide layer.
Especially, the method for described etching fuse-wires structure both sides oxide layer also comprises step F:
After completing etching, carry out wafer sort (Chip Probing, CP).
Especially, described passivation material is selected from silicon oxynitride.
Especially, described etching machine adopts dry etching, and etching gas is octafluorocyclobutane (C
4f
8), oxygen (O
2), carbon monoxide (CO) and carbon dioxide (CO
2) mist.
Especially, described fuse-wires structure is polysilicon fuse or metal fuse.
The system that the invention also discloses a kind of etching fuse-wires structure both sides oxide layer, it comprises: measurement module, computing module, control module and etching machine;
Described measurement module matches with fuse-wires structure, is arranged in scribe line, for measuring the original thickness of fuse-wires structure both sides oxide layer;
Described computing module, for needing residual oxidated layer thickness and described original thickness according to passivation layer, calculates the amount of the oxide layer of required etching, and according to the etching speed of etching machine, determines etch period;
Described control module is for determining etching processing procedure according to described etch period, and control etching completes the etching of fuse-wires structure both sides oxide layer.
Especially, the system of described etching fuse-wires structure both sides oxide layer also comprises: test module, for after completing etching, carries out wafer sort.
Especially, described passivation material is selected from silicon oxynitride.
Especially, described etching machine adopts dry etching.
Especially, described fuse-wires structure is polysilicon fuse or metal fuse.
Compared with traditional lithographic method, the present invention can be according to actual needs, accurately controls the amount of the oxide layer of fuse-wires structure both sides etching, avoid the generation of fuse failure failure phenomenon, and etching efficiency is high, and consuming time short, cost is low.
Brief description of the drawings
The method flow diagram of the etching fuse-wires structure both sides oxide layer that Fig. 1 provides for the embodiment of the present invention;
The overall schematic of the fuse-wires structure that Fig. 2 provides for the embodiment of the present invention;
The system block diagram of the etching fuse-wires structure both sides oxide layer that Fig. 3 provides for the embodiment of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with drawings and Examples, the invention will be further described.
Please refer to shown in Fig. 1 the method flow diagram of the etching fuse-wires structure both sides oxide layer that Fig. 1 provides for the embodiment of the present invention.
In the present embodiment, the method for etching fuse-wires structure both sides oxide layer comprises the steps:
Step S101, the measurement module coordinating with fuse-wires structure is placed in scribe line.
Step S102, measure the original thickness of fuse-wires structure both sides oxide layer by described measurement module.
Step S103, need residual oxidated layer thickness and described original thickness according to passivation layer, calculate the amount of the oxide layer of required etching.
Step S104, according to the etching speed of etching machine, determine etch period.
Step S105, determine etching processing procedure according to described etch period, complete the etching of fuse-wires structure both sides oxide layer.
Step S106, after completing etching, carry out wafer sort (Chip Probing, CP).
The overall schematic of the fuse-wires structure that as shown in Figure 2, Fig. 2 provides for the embodiment of the present invention.The material of Semiconductor substrate 201 can be the one in monocrystalline silicon, polysilicon, amorphous silicon in the present embodiment.The material of dielectric layer 202 is selected from silica, organic silicate glass, Pyrex etc., preferably Pyrex.Described passivation layer 203 is selected from silicon oxynitride.Described etching machine adopts dry etching, and etching gas is octafluorocyclobutane (C
4f
8), oxygen (O
2), carbon monoxide (CO) and carbon dioxide (CO
2) mist.Described fuse-wires structure is polysilicon fuse or metal fuse.
For fear of the generation of fuse failure failure phenomenon, and be convenient to the wafer sort in later stage, in the present embodiment, passivation layer 203 needs residual oxidated layer thickness to be arranged between 5000 dust to 15000 dusts.It should be noted that, in the present invention, the both sides of fuse-wires structure are provided with groove, so, after fuse melts, will flow in the groove of both sides, avoid condense the again generation of electric conduction phenomena of fuse.
The system block diagram of the etching fuse-wires structure both sides oxide layer that as shown in Figure 3, Fig. 3 provides for the embodiment of the present invention.
In the present embodiment, the system of etching fuse-wires structure both sides oxide layer comprises: measurement module 301, computing module 302, control module 303, etching machine 304 and test module 305.
Described measurement module 301 matches with fuse-wires structure, is arranged in scribe line, for measuring the original thickness of fuse-wires structure both sides oxide layer.
Described computing module 302, for needing residual oxidated layer thickness and described original thickness according to passivation layer, calculates the amount of the oxide layer of required etching, and according to the etching speed of etching machine 304, determines etch period.
Described control module 303 is for determining etching processing procedure according to described etch period, and control etching completes the etching of fuse-wires structure both sides oxide layer.
Same, described in the present embodiment, passivation layer is selected from silicon oxynitride.Described etching machine 304 adopts dry etching, and etching gas is C
4f
8, O
2, CO and CO
2mist.Described fuse-wires structure is polysilicon fuse or metal fuse.
Technical scheme of the present invention has solved traditional lithographic method can not need residual oxidated layer thickness to carry out the problem of accurately controlling to passivation layer, avoided the generation of fuse failure failure phenomenon, and etching efficiency is high, and etching cost is low.
Above are only preferred embodiment of the present invention and institute's application technology principle, any be familiar with those skilled in the art the present invention disclose technical scope in, the variation that can expect easily or replacement, all should be encompassed in protection scope of the present invention.
Claims (10)
1. a method for etching fuse-wires structure both sides oxide layer, is characterized in that, comprises the steps:
A, the measurement module coordinating with fuse-wires structure is placed in scribe line;
B, measure the original thickness of fuse-wires structure both sides oxide layer by described measurement module;
C, need residual oxidated layer thickness and described original thickness according to passivation layer, calculate the amount of the oxide layer of required etching;
D, according to the etching speed of etching machine, determine etch period;
E, determine etching processing procedure according to described etch period, complete the etching of fuse-wires structure both sides oxide layer.
2. the method for etching fuse-wires structure according to claim 1 both sides oxide layer, is characterized in that, also comprises step F:
After completing etching, carry out wafer sort (Chip Probing, CP).
3. the method for etching fuse-wires structure according to claim 1 both sides oxide layer, is characterized in that, described passivation material is selected from silicon oxynitride.
4. according to the method for the etching fuse-wires structure both sides oxide layer one of claims 1 to 3 Suo Shu, it is characterized in that, described etching machine adopts dry etching, and etching gas is octafluorocyclobutane (C
4f
8), oxygen (O
2), carbon monoxide (CO) and carbon dioxide (CO
2) mist.
5. the method for etching fuse-wires structure according to claim 4 both sides oxide layer, is characterized in that, described fuse-wires structure is polysilicon fuse or metal fuse.
6. a system for etching fuse-wires structure both sides oxide layer, is characterized in that, comprising: measurement module, computing module, control module and etching machine;
Described measurement module matches with fuse-wires structure, is arranged in scribe line, for measuring the original thickness of fuse-wires structure both sides oxide layer;
Described computing module, for needing residual oxidated layer thickness and described original thickness according to passivation layer, calculates the amount of the oxide layer of required etching, and according to the etching speed of etching machine, determines etch period;
Described control module is for determining etching processing procedure according to described etch period, and control etching completes the etching of fuse-wires structure both sides oxide layer.
7. the system of etching fuse-wires structure according to claim 6 both sides oxide layer, is characterized in that, also comprises: test module, for after completing etching, carries out wafer sort.
8. the system of etching fuse-wires structure according to claim 6 both sides oxide layer, is characterized in that, described passivation material is selected from silicon oxynitride.
9. according to the system of the etching fuse-wires structure both sides oxide layer one of claim 6 to 8 Suo Shu, it is characterized in that, described etching machine adopts dry etching.
10. the system of etching fuse-wires structure according to claim 9 both sides oxide layer, is characterized in that, described fuse-wires structure is polysilicon fuse or metal fuse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310037358.7A CN103972150A (en) | 2013-01-30 | 2013-01-30 | Method and system for etching oxide layer on both sides of fuse structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310037358.7A CN103972150A (en) | 2013-01-30 | 2013-01-30 | Method and system for etching oxide layer on both sides of fuse structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103972150A true CN103972150A (en) | 2014-08-06 |
Family
ID=51241501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310037358.7A Pending CN103972150A (en) | 2013-01-30 | 2013-01-30 | Method and system for etching oxide layer on both sides of fuse structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465368A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | Contact hole etching device and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6773967B1 (en) * | 2002-01-04 | 2004-08-10 | Taiwan Semiconductor Manufacturing Company | Method to prevent antifuse Si damage using sidewall spacers |
| US20050233515A1 (en) * | 2003-12-23 | 2005-10-20 | Systems On Silicon Manufacturing Company Pet. Ltd | Method of etching a semiconductor device |
| CN101211779A (en) * | 2006-12-29 | 2008-07-02 | 联华电子股份有限公司 | Method for forming fuse window on semiconductor substrate web by two- stage etching mode |
| CN102299094A (en) * | 2010-06-24 | 2011-12-28 | 无锡华润上华半导体有限公司 | manufacturing method of fuse wire structure |
-
2013
- 2013-01-30 CN CN201310037358.7A patent/CN103972150A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6773967B1 (en) * | 2002-01-04 | 2004-08-10 | Taiwan Semiconductor Manufacturing Company | Method to prevent antifuse Si damage using sidewall spacers |
| US20050233515A1 (en) * | 2003-12-23 | 2005-10-20 | Systems On Silicon Manufacturing Company Pet. Ltd | Method of etching a semiconductor device |
| CN101211779A (en) * | 2006-12-29 | 2008-07-02 | 联华电子股份有限公司 | Method for forming fuse window on semiconductor substrate web by two- stage etching mode |
| CN102299094A (en) * | 2010-06-24 | 2011-12-28 | 无锡华润上华半导体有限公司 | manufacturing method of fuse wire structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465368A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | Contact hole etching device and method |
| CN104465368B (en) * | 2014-11-28 | 2017-07-07 | 上海华力微电子有限公司 | A kind of contact hole etching device and lithographic method |
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Application publication date: 20140806 |
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