CN103957094B - Data block synchrotron and rapid data block synchronization method - Google Patents
Data block synchrotron and rapid data block synchronization method Download PDFInfo
- Publication number
- CN103957094B CN103957094B CN201410201789.7A CN201410201789A CN103957094B CN 103957094 B CN103957094 B CN 103957094B CN 201410201789 A CN201410201789 A CN 201410201789A CN 103957094 B CN103957094 B CN 103957094B
- Authority
- CN
- China
- Prior art keywords
- data block
- cnt
- synchrotron
- data
- invalid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Particle Accelerators (AREA)
Abstract
A kind of data block synchrotron, it is applied in the network equipment, the data block synchrotron is often taken turns acceleration and reads in m 66 data of group, whether it is synchronous head to 66 Data Detection of per group of reading per adjacent two, to 66 data accumulation testing results of m groups, so as to quickly determine synchronous head position, detection efficiency is improve, shorten the data block synchronous time.
Description
Technical field
The present invention relates to a kind of data block synchrotron and 10G Ethernet Physical Coding Sublayer expedited data units synchronization side
Method.
Background technology
As high speed development and the popularization of Internet technology, data exchange requirement at a high speed, inexpensive are more and more urgent, hold
The continuous innovation for promoting network technology.Ethernet technology is the most widely used local area network technology at present, can be simple, economical
Ground builds the network of various speed.From 10Mbps standard ethernets, 100Mbps Fast Ethernets, 1000Mbps gigabit Ethernets,
Arrive 10Gbps, 40Gbps even 100Gbps ultrahigh speed Ethernets again, maintain while ethernet technology quickly updates good
Good inheritance.
IEEE formally passed through the 10Gbps ethernet technologys of 802.3ae standards in 2002.10G Fast Ethernets can be with
Meet high-transmission bandwidth demand, and compatible with ethernet technology before, and do not transmitted due to the mode of operation of its full duplex
The restriction of distance.Therefore, 10G ethernet technologys are widely used among LAN, Metropolitan Area Network (MAN) and wide area network, work for framework
High speed and infallible data network of the speed for 10Gbps.At present, 10G ethernet technologys have been widely used for convergence-level and backbone
Among layer network.
10G ethernet technology standards are determined by IEEE802.3ae.10G Ethernets be the standard specifies in seven layer networks of OSI
The implementation method of the media access control sublayer of physical layer and data link layer in model.
Physical Coding Sublayer (PCS) be located at physical layer upper strata, be connected with the media access control sublayer of data link layer upwards, downwards with
Physical medium attachment sublayer (PMA) connects.Different according to interface and application scenarios, 10G Ethernets PCS point is three kinds of realization sides
Formula, LAN 10G BASE-X, 10G BASE-R and wide area network 10G BASE-W.Wherein 10G BASE-X interfaces are multiple using multichannel
With technology, collect 4 road 3.125Gbps and form single channel 10Gbps.Other two kinds adopt single channel 10.3125Gbp fiber-optic transfer, are mesh
Front application mainstream.10G BASE-W are that insertion Wide Area Network interface sublayer is expanded on the basis of 10G BASE-R.Therefore 10G
BASE-R PCS are key modules in 10G Ethernets.
10G BASE-R PCS point is transmitter and receiver.Transmitter is by 64 XGMII form numbers from media access control sublayer
According to being encoded into 66, then through scrambler, form transmission code and give physical layer bottom.During reception, lock unit aligns first
66 transmission codes for receiving, that is, complete data block synchronization, then forms 64 of XGMII forms through 64B/66B descrambling procedures
Data.The characteristics of data block synchronizing process has 01 upset using low two perseverances of 66 transmission codes is realized.The feature is compiled by 64B/66B
Code, scrambler mechanism ensure.
Existing 10G BASE-R PCS normal datas block synchronization method only detects certain phase in 66 data of reading every time
Whether adjacent two be synchronous head, and detection efficiency is relatively low, and the time used by data block is synchronous is longer.
Content of the invention
In view of the foregoing, it is necessary to provide a kind of data block synchrotron and using the data block synchrotron reality
Existing 10G Ethernet Physical Coding Sublayer rapid data block synchronization methods, can effectively improve the synchronous speed of data block.
A kind of data block synchrotron, is applied in the network equipment, and the data block synchrotron is often taken turns acceleration and reads in m
66 data of group, are designated as RX successively0、RX1、…、RXm-1, often read in one group of 66 data RXkAfter (k=0,1,2 ..., m-1), number
According to block synchrotron to 66 data RXkEvery adjacent two do XOR, obtain RXk66 testing results TAG_
TEMk, i.e. TAG_TEMk[i]=RXk[i]^RXk[i+1], i=0,1,2 ..., 65, ^ represent XOR, and accumulative epicycle adds
66 testing results TAG of speedk=TAG_TEM0&TAG_TEM1&…&TAG_TEMk, wherein ＆ is represented and computing, in reading m
After 66 data of group, data block synchrotron determines 66 testing results TAG that epicycle acceleratesm-1In nearest from low order end
For 1 position n, so as to maximum probability locking synchronization head position.
The 10G Ethernet Physical Coding Sublayer expedited data units synchronization side that a kind of utilization data block synchrotron is realized
Method, the method include：
First step, under LOCK_INT states, puts block_lock=0, represents that now data block is asynchronous, puts test_
Sh=0, represents and is ready to read in data block, put AC_en=1, represent and open data block synchrotron, put AC_ready=0,
Represent that data block synchrotron does not complete a wheel and accelerates；
Second step, after receiving Rst signals, unconditionally jumps into RESET_CNT states, RESET_ by LOCK_INT states
Under CNT states, enumerator sh_cnt, sh_invalid_cnt reset, and prepare to start new round monitoring, and wherein sh_cnt is counted
Monitoring Data block number, the invalid data block number of sh_invalid_cnt count synchronization heads；
Third step, when 66 data, i.e. test_sh=1 are read in, jumps into TEST_SH states, under TEST_SH states,
Whether effectively to judge the synchronous head of current data block, if the synchronous head of current data block effectively, puts sh_valid=1, otherwise,
If the synchronous head of current data block is invalid, sh_valid=0 is put, complete to judge rearmounted test_sh=0.
Four steps, as sh_valid=1 and AC_ready=0, enters VALID_SH states, and sh_cnt adds 1, (1) when
sh_cnt<When 64, represent that epicycle monitoring not yet terminates, read in next secondary data, be i.e., after test_sh=1, return the 3rd step
Suddenly；(2) as sh_cnt=64 and sh_invalid_cnt=0, then the effective synchronous head of epicycle monitoring continuous monitoring to 64, turns
Enter state 64_GOOD, put block_lock=1, the synchronous success of expression data block is put AC_en=0, represents that closing data block is same
Step accelerator, returns second step；(3) as sh_cnt=64 and sh_invalid_cnt>0, then epicycle monitoring terminates, but has not
The data block invalid more than 16 synchronous heads, it is impossible to determine whether data block is synchronous, needs further to monitor, and returns second step
Suddenly；
5th step, as sh_valid=0 and AC_ready=0, enters state I NVALID_SH, and sh_cnt adds 1,
Sh_invalid_cnt adds 1, and (1), as block_lock=0, now data block is sentenced synchronously and during synchronous monitoring
The asynchronous head of disconnected current sync head test position maximum probability, synchronous head test position enter new round prison to high-order mobile one
Survey, return second step；(2) as block_lock=1 and sh_invalid_cnt=16, judge that now data block is different
Walk, put blok_lock=0, synchronous head test position is mobile one to a high position, and open data block synchrotron and put AC_
En=1, returns second step；(3) as block_lock=1 and sh_invalid_cnt<When 16 and sh_cnt=64, epicycle is supervised
Survey terminates, it is impossible to judge whether data block is synchronous, needs further to be monitored, and returns second step；(4) work as block_lock=1
And sh_invalid_cnt<16 and sh_cnt<When 64, epicycle monitoring does not terminate, and is test_sh in next group of 66 data readings
After=1, third step is jumped to.
6th step, work as AC_ready=1, i.e. data block synchrotron complete a wheel accelerate when, enter state AC_
LOCK, puts sh_cnt=sh_cnt+m, puts sh_invalid_cnt=0, and synchronous head test position is moved to position n, puts AC_
Ready=0, prepares to start next round acceleration, when next group of data reading is test_sh=1, returns third step.
Often wheel accelerates to read in m 66 data of group the present invention, and whether every to 66 Data Detection of per group of reading adjacent two
For synchronous head, to 66 data accumulation testing results of m groups, so as to quickly determine synchronous head position, detection efficiency is improve, shortened
Data block synchronous time.
Description of the drawings
Fig. 1 is the schematic diagram of data block synchrotron preferred embodiment of the present invention.
Fig. 2 is the Organization Chart of 66 position locks.
Fig. 3 is that the state of 10G Ethernets Physical Coding Sublayer rapid data block synchronization method preferred embodiment of the present invention is jumped
Turn figure.
Specific embodiment
Data block synchrotron of the present invention and 10G Ethernet Physical Coding Sublayer rapid data block synchronization methods
It is applied in the network equipment.The network equipment can be router or switch.
Refering to shown in Fig. 1, it is the schematic diagram of data block synchrotron preferred embodiment of the present invention.The data block synchronization
Accelerator reads in clock as clock with data, is run in the form of streamline.Data block synchrotron is often taken turns acceleration and reads in m groups
66 data, are designated as RX successively0、RX1,…,RXm-1.When synchronous head is not synchronous, one group of 66 data RX is often read ink(k=0,
1,2 ..., m-1) after, data block synchrotron is to 66 data RXkEvery adjacent two (66 pairs) do XOR, obtain
Arrive RXk66 testing results TAG_TEMk(TAG_TEMk[i]=RXk[i]^RXk[i+1], (i=0,1,2 ..., 65)), and tire out
66 testing results TAG that meter epicycle acceleratesk=TAG_TEM0&TAG_TEM1&…&TAG_TEMk, wherein ＆ represents and computing.When
After reading in 66 data of m groups, 66 testing results TAG that epicycle acceleratesm-1Middle most of position should be 0, be that 1 position is then
Possible synchronous head position.Data block synchrotron determines 66 testing results TAG that epicycle acceleratesm-1In from low order end most
Near for 1 position n, so as to maximum probability locking synchronization head position.In the present embodiment, the m values are between 6-10, i.e. m
=6,7,8,9 or 10.Per group of 66 data are a data block.
In the present embodiment, the data block synchrotron utilizes XOR door to RXkEvery adjacent two do different
Or computing, reading in one group of 66 data RXkAnd obtain RXk66 testing results TAG_TEMkAfterwards, TAG_TEM is closedkIn be
XOR door corresponding to 0 position (can not possibly be the position of synchronous head).It is unnecessary that this measure can be greatly decreased
XOR, has saved power consumption.
In the present embodiment, the data block synchrotron determines TAG using 66 position locksm-1In from low level
End nearest for 1 position n.The Organization Chart of 66 position locks is shown in Figure 2.
Refering to shown in Fig. 2, it is the Organization Chart of 66 position locks.66 position locks include multiple 8 lockings
Device and address arbiter.Each 8 lock is input into 8 data, exports valid and out [2:0].Valid is 18 digits of instruction
According in, at least 1 is 1, and it is out [2 that lowest order is 1 position:0]；Valid is that 08 data of instruction are all 0.Arbitrate address
Output result of the device according to 8 locks, according to from low level to high-order priority orders, exports 66 input datas TAGm-1
In from low order end nearest for 1 position n.
Refering to shown in Fig. 3, it is 10G Ethernets Physical Coding Sublayer rapid data block synchronization method preferred embodiment of the present invention
State transition figure.The state transition figure describes 10G Ethernets Physical Coding Sublayer rapid data block synchronization method of the present invention
Flow process as follows：
First step, under LOCK_INT states, puts block_lock=0, represents that now data block is asynchronous；Put test_
Sh=0, represents and is ready to read in data block (i.e. 66 data)；AC_en=1 is put, is represented and is opened data block synchrotron；Put
AC_ready=0, represents that data block synchrotron does not complete a wheel and accelerates.
Second step, after receiving Rst signals, unconditionally jumps into RESET_CNT states by LOCK_INT states.RESET_
Under CNT states, enumerator sh_cnt, sh_invalid_cnt reset, and prepare to start new round monitoring.Sh_cnt is counted and is monitored
Data block number, the invalid data block number of sh_invalid_cnt count synchronization heads.64 groups of 66 data are read in often wheel monitoring.
Third step, when 66 data (i.e. test_sh=1) are read in, jumps into TEST_SH states.TEST_SH states
Under, judge whether the synchronous head of current data block is effective.If the synchronous head of current data block effectively, puts sh_valid=1；No
Then, if the synchronous head of current data block is invalid, sh_valid=0 is put.Complete to judge rearmounted test_sh=0.Judge data block
Synchronous head whether judged for certain adjacent two (i.e. synchronous head test position) in data block, if data block
In two nothings 01 overturn, then the synchronous head of the data block is invalid.
Four steps, as sh_valid=1 and AC_ready=0, enters VALID_SH states, and sh_cnt adds 1.Work as sh_
cnt<When 64, represent that epicycle monitoring not yet terminates, after next secondary data reads in (test_sh=1), return third step；When
During sh_cnt=64 and sh_invalid_cnt=0, then epicycle monitoring continuous monitoring proceeds to state to 64 valid data blocks
64_GOOD, puts block_lock=1, represents the synchronous success of data block, puts AC_en=0, represent and close data block sync plus white
Device, returns second step；As sh_cnt=64 and sh_invalid_cnt>0, then epicycle monitoring terminates, but has less than 16
The invalid data block of synchronous head, it is impossible to determine whether synchronous head is synchronous, needs further to monitor, and returns second step.
5th step, as sh_valid=0 and AC_ready=0, enters state I NVALID_SH, and sh_cnt adds 1,
Sh_invalid_cnt adds 1.As block_lock=0, SLIP states are entered, now data block is synchronously and in synchronous monitoring
During, judge that the asynchronous head of current sync head test position maximum probability, synchronous head test position move one (i.e. to high-order
SLIP1), new round monitoring is entered, second step is returned；As block_lock=1 and sh_invalid_cnt=16, enter
SLIP states, judge that now data block is asynchronous, put blok_lock=0, and synchronous head test position moves one (i.e. to high-order
SLIP1), and open data block synchrotron (putting AC_en=1), return second step；As block_lock=1 and sh_
invalid_cnt<When 16 and sh_cnt=64, epicycle monitoring terminates, it is impossible to judge whether data block is synchronous, needs further to be supervised
Survey, return second step；As block_lock=1 and sh_invalid_cnt<16 and sh_cnt<When 64, epicycle monitoring is not tied
Beam, when next group of 66 data read in (i.e. test_sh=1), jumps to third step.
6th step, work as AC_ready=1, i.e. data block synchrotron complete a wheel accelerate when, enter state AC_
LOCK.Sh_cnt=sh_cnt+m is put, sh_invalid_cnt=0 is put, synchronous head test position is moved to position n (i.e.
SLIP2), AC_ready=0 is put, prepares to start next round acceleration.When next group of data read in (i.e. test_sh=1), return
Third step.Synchronous head test position is moved to position n can be referring to Fig. 1.
10G Ethernets Physical Coding Sublayer rapid data block synchronization method of the present invention is not in the case where original standard is destroyed
Propose, increase data block synchrotron newly, during AC_en=1, open data block synchrotron, as AC_ready=1, represent
Data block synchrotron has completed a wheel accelerator, locking synchronization head position n, the data block synchronization as AC_ready=0
Accelerator starts next round accelerator.The present invention can on the basis of original preferred circuit Design assistant accelerating circuit.When new
In the case that method is invalid, will be according to standard method normal work.
Through simulation comparison experiment, as m=10, normal data block synchronization method averagely needs 125 clock cycle to complete to count
According to block synchronization, 10G Ethernets Physical Coding Sublayer rapid data block synchronization method of the present invention only needs to 70 clock cycle and completes
Data block synchronization, speed lift about 44%.
Claims (10)
1. a kind of data block synchrotron, is applied in the network equipment, it is characterised in that the data block synchrotron is often taken turns
Accelerate to read in m 66 data of group, be designated as RX successively0、RX1、…、RXm-1, often read in one group of 66 data RXkAfterwards, k=0,1,
2 ..., m-1, data block synchrotron is to 66 data RXkEvery adjacent two do XOR, obtain RXk66 inspection
Survey result TAG_TEMk, i.e. TAG_TEMk[i]=RXk[i]^RXk[i+1], i=0,1,2 ..., 65, ^ represent XOR, and
66 testing results TAG that accumulative epicycle acceleratesk=TAG_TEM0&TAG_TEM1&…&TAG_TEMk, wherein ＆ represents and computing,
After m 66 data of group are read in, data block synchrotron determines 66 testing results TAG that epicycle acceleratesm-1In from low level
End nearest for 1 position n, so as to maximum probability locking synchronization head position.
2. data block synchrotron as claimed in claim 1, it is characterised in that the data block synchrotron utilizes 66
Position lock determines TAGm-1In from low order end nearest for 1 position n.
3. data block synchrotron as claimed in claim 2, it is characterised in that 66 position locks include multiple
8 locks and an address arbiter.
4. data block synchrotron as claimed in claim 1, it is characterised in that the data block synchrotron utilizes XOR
Computing door is to RXkEvery adjacent two do XOR, read in one group of 66 data RXkAnd obtain RXk66 testing results
TAG_TEMkAfterwards, TAG_TEM is closedkIn for 0 position corresponding to XOR door.
5. data block synchrotron as claimed in claim 1, it is characterised in that the m values are 6,7,8,9 or 10.
6. the 10G Ethernet Physical Coding Sublayers that the data block synchrotron described in a kind of utilization claim 1 is realized are quick
Data block synchronization method, it is characterised in that the method includes：
First step, under LOCK_INT states, puts block_lock=0, represents that now data block is asynchronous, puts test_sh=
0, represent and be ready to read in data block, put AC_en=1, represent and open data block synchrotron, put AC_ready=0, represent
Data block synchrotron does not complete a wheel and accelerates；
Second step, after receiving Rst signals, unconditionally jumps into RESET_CNT states, RESET_CNT shapes by LOCK_INT states
Under state, enumerator sh_cnt, sh_invalid_cnt reset, and prepare to start new round monitoring, and wherein sh_cnt is counted and monitored
Data block number, the invalid data block number of sh_invalid_cnt count synchronization heads；
Third step, when 66 data, i.e. test_sh=1 are read in, jumps into TEST_SH states, under TEST_SH states, judges
Whether effectively the synchronous head of current data block, if the synchronous head of current data block is effective, puts sh_valid=1, otherwise, if working as
The synchronous head of front data block is invalid, then put sh_valid=0, completes to judge rearmounted test_sh=0；
Four steps, as sh_valid=1 and AC_ready=0, enters VALID_SH states, and sh_cnt adds 1, and (1) works as sh_
cnt<When 64, represent that epicycle monitoring not yet terminates, read in next secondary data, be i.e., after test_sh=1, return third step；
(2) as sh_cnt=64 and sh_invalid_cnt=0, then epicycle monitoring continuous monitoring is proceeded to 64 valid data blocks
State 64_GOOD, puts block_lock=1, represents the synchronous success of data block, puts AC_en=0, represent and close data block synchronization
Accelerator, returns second step；(3) as sh_cnt=64 and sh_invalid_cnt>0, then epicycle monitoring terminates, but has and do not surpass
Cross 16 invalid data blocks of synchronous head, it is impossible to determine whether data block is synchronous, needs further to monitor, and returns second step；
5th step, as sh_valid=0 and AC_ready=0, enters state I NVALID_SH, and sh_cnt adds 1, sh_
Invalid_cnt adds 1, and (1), as block_lock=0, now data block synchronously and during synchronous monitoring judges to work as
The asynchronous head of preamble head test position maximum probability, synchronous head test position enter new round monitoring, return to high-order mobile one
Return second step；(2) as block_lock=1 and sh_invalid_cnt=16, judge that now data block is asynchronous, puts
Blok_lock=0, synchronous head test position is to high-order mobile one, and opens data block synchrotron and put AC_en=1,
Return second step；(3) as block_lock=1 and sh_invalid_cnt<When 16 and sh_cnt=64, epicycle monitoring knot
Beam, it is impossible to judge whether data block is synchronous, needs further to be monitored, and returns second step；(4) as block_lock=1 and sh_
invalid_cnt<16 and sh_cnt<When 64, epicycle monitoring does not terminate, and is test_sh=1 in next group of 66 data readings
Afterwards, third step is jumped to；
6th step, work as AC_ready=1, i.e. data block synchrotron complete a wheel accelerate when, enter state AC_LOCK,
Sh_cnt=sh_cnt+m is put, sh_invalid_cnt=0 is put, synchronous head test position is moved to position n, puts AC_ready=
0, prepare to start next round acceleration, when next group of data reading is test_sh=1, return third step.
7. 10G Ethernets Physical Coding Sublayer rapid data block synchronization method as claimed in claim 6, it is characterised in that institute
State data block synchrotron TAG is determined using 66 position locksm-1In from low order end nearest for 1 position n.
8. 10G Ethernets Physical Coding Sublayer rapid data block synchronization method as claimed in claim 7, it is characterised in that institute
Stating 66 position locks includes multiple 8 locks and an address arbiter.
9. 10G Ethernets Physical Coding Sublayer rapid data block synchronization method as claimed in claim 6, it is characterised in that institute
Data block synchrotron is stated using XOR door to RXkEvery adjacent two do XOR, read in one group of 66 digit
According to RXkAnd obtain RXk66 testing results TAG_TEMkAfterwards, TAG_TEM is closedkIn for 0 position corresponding to XOR
Door.
10. 10G Ethernets Physical Coding Sublayer rapid data block synchronization method as claimed in claim 6, it is characterised in that institute
M values are stated for 6,7,8,9 or 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410201789.7A CN103957094B (en) | 2014-05-13 | 2014-05-13 | Data block synchrotron and rapid data block synchronization method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410201789.7A CN103957094B (en) | 2014-05-13 | 2014-05-13 | Data block synchrotron and rapid data block synchronization method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103957094A CN103957094A (en) | 2014-07-30 |
| CN103957094B true CN103957094B (en) | 2017-03-15 |
Family
ID=51334325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410201789.7A Active CN103957094B (en) | 2014-05-13 | 2014-05-13 | Data block synchrotron and rapid data block synchronization method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103957094B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113904756B (en) * | 2021-10-15 | 2023-11-07 | 深圳市紫光同创电子有限公司 | Ethernet system based on 10Gbase-R protocol |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1547361A (en) * | 2003-12-05 | 2004-11-17 | 清华大学 | A method for receiving Ethernet data |
-
2014
- 2014-05-13 CN CN201410201789.7A patent/CN103957094B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1547361A (en) * | 2003-12-05 | 2004-11-17 | 清华大学 | A method for receiving Ethernet data |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103957094A (en) | 2014-07-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10396921B2 (en) | Multi-lane synchronization method, synchronization apparatus and system, and computer storage medium | |
| CN103997465B (en) | A kind of generation CNM method and apparatus | |
| CN105357137A (en) | Message filtering method and applicable FPGA and intelligent substation | |
| CN105554152B (en) | A kind of method and device of data characteristics extraction | |
| CN104579541B (en) | A kind of building method of wireless communication system Medium Access Layer protocol Data Unit | |
| CN103259793A (en) | Method for inspecting deep packets based on suffix automaton regular engine structure | |
| CN102694801B (en) | Method for detecting virus, device and firewall box | |
| Jain | Error characteristics of fiber distributed data interface (FDDI) | |
| CN108123775A (en) | The method and apparatus of transmission packet | |
| CN108235413A (en) | The power optimization mechanism of framer handled by the frame alignment for serializing multiple channels | |
| CN107329915A (en) | Recover the method and system of low speed data by high speed SerDes interfaces | |
| CN103888338B (en) | The traffic sharing method and device of Ethernet MTL microwave transmission link polymerization | |
| CN103957094B (en) | Data block synchrotron and rapid data block synchronization method | |
| CN104871510A (en) | Apparatus and method for encoding mdio into sgmii transmissions | |
| CN103248449B (en) | The symbol of parallel data delimits method and device | |
| US6778551B1 (en) | Collision control systems and methods utilizing an inter-frame gap code counter | |
| JP4988544B2 (en) | Data processing apparatus, data processing method, and program | |
| CN102130744B (en) | Method and device for computing Cyclic Redundancy Check (CRC) code | |
| CN109286471A (en) | CRC check method and device towards SRIO controller | |
| CN107239419A (en) | It is a kind of that the adaptive method of network interface is realized under PowerPC DPAA patterns | |
| CN104426687A (en) | A network storm filtering method applicable for a digital substation secondary device | |
| CN107124201A (en) | A kind of subsurface communication method towards Shui Zhong robots | |
| CN104753640B (en) | A kind of adaptation method and device based on network transmission link | |
| CN101478448B (en) | Control method and apparatus for Ethernet switching equipment | |
| US9742701B2 (en) | Attachment unit interfaces for non-identical data rate links |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |