CN1547361A - A method for receiving Ethernet data - Google Patents
A method for receiving Ethernet data Download PDFInfo
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- CN1547361A CN1547361A CNA2003101171771A CN200310117177A CN1547361A CN 1547361 A CN1547361 A CN 1547361A CN A2003101171771 A CNA2003101171771 A CN A2003101171771A CN 200310117177 A CN200310117177 A CN 200310117177A CN 1547361 A CN1547361 A CN 1547361A
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Abstract
The invention proposes a method for receiving the Ethernet data, which belongs to Ethernet communication technology field. The method receives the synchronous transmitting mode signal from the Ethernet loop; extracts the user data in them and carries on series-parallel transition; carries on the legality judgment to each pair of adjoined parallel data, then carries on judgment of continuity; searches the continuous signal, acquires the position of the synchronous code; the disturbed 64B//66B frame is extracted form the user data in the synchronous transmitting mode signal, then carries on disturbance decoding, then carries on 64B/66B decoding, acquires the Ethernet frame. The method uses the continuity judgment to replace the synchronous state machine in current technology, thus it reduces the chip area occupied by the frame synchronous system greatly.
Description
Technical field the present invention relates to a kind of method that receives Ethernet data, belongs to Ethernet communication technology field, in particular to the technology to reception 10G Ethernet data.
The background technology Ethernet is a kind of widely used computer communication network.The present invention at the 10G Ethernet, be meant the 10G Ethernet that is numbered IEEE802.3ae-2002 agreement defined that Institute of Electrical and Electronics is worked out.According to the regulation of this agreement, the 10G Ethernet is divided into two kinds of different types of 10G wide area network and 10G local area network (LAN).The physical layer of the 10G Ethernet of wan type uses " synchronous digital hierarchy " this Optical synchronization digital transmission network to carry ethernet frame.As shown in Figure 1, concrete bearing mode is, when sending ethernet frame, at first by " destination address domain ", " source address field ", " length type territory ", the ethernet frame that " data field " and " frame effect sequence territory " constitutes is divided into a plurality of " pieces " that bit wide is 64 bits.Then each " piece " encoded with the 64B/66B encoder, forming bit wide is " the 64B/66B frame " of 66 bits.Then " 64B/66B frame " carried out scrambler (being designated hereinafter simply as scrambling).At last the 64B/66B bit stream after the scrambling being put into the synchronous digital hierarchy label is synchronous transfer module unit (hereinafter to be referred as the STM-64C) transmission of 64C.When receiving Ethernet data, the STM-64C that receives is exactly the 64B/66B bit stream of scrambling.At first need the 64B/66B bit stream of scrambling is divided into the 64B/66B frame of scrambling, use descrambler descrambles then, the 64B/66B frame that obtains disturbing, again each 64B/66B frame is carried out the 64B/66B decoding with the 64B/66B decoder, obtain the Ethernet that bit wide is 64 bits " piece ", these " pieces " are joined end to end just is reduced into the ethernet frame that transmitting terminal sends.
Above-mentioned 64B/66B frame assumption diagram as shown in Figure 2.This frame length is fixed as 66 bits, and preceding 2 bits of every frame are synchronous head, are used for indicating the 64B/66B frame start position.The synchronous head of legal 64B/66B frame is binary signal " 01 " or " 10 " (being designated hereinafter simply as the synchronous code-type of 64B/66B frame).And binary signal " 00 " or " 11 " can not constitute legal 64B/66B frame synchronization head.Back 64 bits of 64B/66B frame are information field.
Above-mentioned when receiving Ethernet data, the problem that the 64B/66B bit stream of scrambling is divided into the 64B/66B frame of scrambling belongs to the following frame synchronization problem of introduction in detail that is about to.
The bit stream that transmits in the digital communication system generally has certain frame structure.A kind of common frame structure is: each frame is end to end in the bit stream, and every frame length is fixed, and a kind of special code character that is called as synchronous code-type occurs in certain fixed position of every frame.The said fixing position is called the synchronous code position.The process of seeking the synchronous code position is called frame synchronizing process.The system that finishes frame synchronizing process is called frame synchronization system.The method of seeking the synchronous code position is frame synchornization method.When the synchronous code position has been found in the frame synchronization system identification, claim this system to enter synchronous state.
In existing frame synchornization method, frame synchronization system comprises a finite state machine mostly, and this state machine is operated in search, checks and synchronous these 3 states.In other words, through search and check, frame synchronization system has just reached frame synchronization.At search condition, frame synchronization system uses comparator, searches for synchronous code-type in the bit stream that arrives.The code character that searches may be real synchronous code character, also may be pseudo-code character synchronously.If real synchronous code character then synchronous code-type should occur once more in the position apart from a frame length of this code character.If pseudo-code character synchronously, then pseudo-code character synchronously is extremely low at the probability that the position of the frame length of being separated by occurs once more.In order to differentiate the true and false of this synchronous code character, frame synchronization system enters the check state.At the check state, frame synchronization system is checked the code character that arrives every a frame period, sees whether it remains legal synchronous code-type.If legal, then further proved current search to the position be the synchronous code position.Can further check in this case, assert that perhaps this position is the synchronous code position, frame synchronization system enters synchronous state.If illegal, then illustrate current search to the position be not the synchronous code position, only be for coincidence and last time on this position, occurred synchronous code-type.Frame synchronization system will reenter search condition.At synchronous state, frame synchronization system will continue to check whether the code character on the synchronous code position is legal synchronous code character.If occur the illegal code character synchronously of several times continuously on sync bit, then frame synchronization system returns the search attitude and restarts to search for synchronous code character.Frame synchronization system is called frame synchronizing process by beginning to search the process that enters synchronous state.
Modern digital communication systems often adopts the part parallel technology, and the system of being about to is divided into serial and parallel two parts.When frame synchronizing process when the serial of communication system is partly finished, need to adopt the consecutive frame method for synchronous.When frame synchronizing process when the communication system parallel section is finished, need to adopt the concurrent frame method for synchronous.
As shown in Figure 3, the IEEE802.3ae-2002 agreement to the 64B/66B frame synchornization method the requirement that should satisfy made regulation, but do not stipulate concrete frame synchornization method.
The basic principle of serial and concurrent frame method for synchronous all meets the operation principle of above-mentioned frame synchronization system, and all needs to use comparator and finite state machine.Whether the code stream that comparator is used for relatively arriving is identical with synchronous code-type, and state machine is used for realizing the state transitions process of above-mentioned frame synchronization system.The consecutive frame method for synchronous needs a comparator and a state machine, and the concurrent frame method for synchronous needs a plurality of comparators and a plurality of state machine.In high speed circuit, must adopt the synchronous method of concurrent frame.No matter consecutive frame method for synchronous or concurrent frame method for synchronous, its protection process all is identical, and what diversity ratio was bigger is frame synchronizing process.
In the 10G of 66 bit parallels Ethernet data receiving system, what enter frame synchronization system is that bit wide is the parallel signal of 66 bits at every turn.These 66 positions all may be the synchronous code position.If use the existing Ethernet cut-in method, just need 66 comparators and 66 synchronous state machines, this will have very big chip area expense.In order to solve the existing excessive problem of Ethernet cut-in method chip occupying area, be necessary to propose the smaller Ethernet cut-in method of a kind of area overhead.
Goal of the invention the objective of the invention is to propose a kind of method of new reception Ethernet data, overcome in the method for existing reception 10G Ethernet data, thereby in the 64B/66B frame synchronizing process, use a plurality of synchronous state machines to cause the bigger difficulty of receiving system chip occupying area, solve the problem that receives Ethernet data with the littler method of cost.
The method of the reception Ethernet data that the present invention proposes may further comprise the steps:
(1) reception is from the synchronous transfer module signal of ethernet line;
(2) user data in the above-mentioned synchronous transfer module signal of extraction;
(3) above-mentioned user data is gone here and there and change, make the serial data of 1 bit bit wide convert the parallel data of 66 bit bit wides to;
(4) respectively whether legal every adjacent two parallel data carried out differentiation, carry out whether continuous differentiation again;
(5) above-mentioned continuity signal is searched for, to obtain the position of synchronous code;
(6) according to above-mentioned synchronous code position, extract the 64B/66B frame of scrambling in the user data from above-mentioned (2) step synchronous transfer module signal, carry out descrambling code, carry out the 64B/66B decoding then, obtain ethernet frame.
Whether legal method is to differentiate every adjacent two parallel-by-bit data in the said method: every adjacent two parallel-by-bit data are carried out XOR, if result of calculation is " 1 ", think that then adjacent two parallel-by-bit data are legal; If result of calculation is " 0 ", think that then adjacent two parallel-by-bit data are for illegal.
The method of differentiating every adjacent two parallel-by-bit data continuity in the said method is: in the cycle, it is legal to be in each clock cycle as if the legitimacy differentiation to every adjacent two parallel-by-bit data, then is continuous at given continuous clock; Otherwise be discontinuous.Given continuous clock periodicity can be taken as 64.
In the said method continuous signal being carried out search procedure is: set a search and open the beginning position, search for along the direction that positional value increases progressively, first position of satisfying the continuity differentiation is the synchronous code position.
The method of the reception Ethernet data that the present invention proposes, the method for using synchronous state machine to differentiate in the method replacement prior art of using continuity to differentiate in the 64B/66B frame synchronizing process when receiving the 10G Ethernet data.Thereby significantly reduced the chip area that frame synchronization system takies.
Description of drawings
Fig. 1 is the coding method schematic diagram of 10G Ethernet in the prior art.
Fig. 2 is the 64B/66B frame assumption diagram.
Fig. 3 be 802.3ae-2002 regulation the 64B/66B frame synchornization method the requirement that should satisfy.
Fig. 4 is the end to end situation of 64B/66B frame behind the scrambler in the synchronous transfer module signal in the inventive method.
Fig. 5 is the input data of 66 bit bit wides after the parallelization in the inventive method.
Fig. 6 carries out the embodiment that continuity is differentiated in the inventive method.
Embodiment
The method of the reception Ethernet data that the present invention proposes at first receives the synchronous transfer module signal from ethernet line; Extract the user data in the synchronous transfer module signal; User data is gone here and there and changed, make the serial data of 1 bit bit wide convert the parallel data of 66 bit bit wides to; Respectively whether legal every adjacent two parallel data carried out differentiation, carry out whether continuous differentiation again; Continuity signal is searched for, to obtain the position of synchronous code; According to the synchronous code position, extract the 64B/66B frame of scrambling in the user data from the synchronous transfer module signal, carry out descrambling code, carry out the 64B/66B decoding then, obtain ethernet frame.
Whether legal method is to differentiate every adjacent two parallel-by-bit data in the said method, and every adjacent two parallel-by-bit data are carried out XOR, if result of calculation is " 1 ", thinks that then adjacent two parallel-by-bit data are legal; If result of calculation is " 0 ", think that then adjacent two parallel-by-bit data are for illegal.
The method of differentiating every adjacent two parallel-by-bit data continuity in the said method is: in the cycle, it is legal to be in each clock cycle as if the legitimacy differentiation to every adjacent two parallel-by-bit data, then is continuous at given continuous clock; Otherwise be discontinuous.Given continuous clock periodicity can be taken as 64.
In the said method continuous signal being carried out search procedure is: set a search and open the beginning position, search for along the direction that positional value increases progressively, first position of satisfying the continuity differentiation is the synchronous code position.
The user data that extracts in this method is to constitute by the 64B/66B frame of scrambling is end to end, the bit stream of a synchronous head promptly occurs every 64 bits.What Fig. 4 represented is the 64B/66B bit stream of scrambling and the situation that two synchronous code characters of puppet occurred.This bit stream is made up of the 64B/66B frame of end to end scrambling.The 64B/66B frame of each scrambling comprises the synchronous head of 2 bits and the information field of 64 bit scrambles.Pseudo-code character synchronously may appear in information field.It should be noted that the code character that also may occur meeting synchronous code-type at information field.Be referred to as pseudo-code character synchronously.
User data is gone here and there and changed, make the serial data of 1 bit bit wide convert the parallel data of 66 bit bit wides to, be designated as the 1st, the 2nd ... the 66th, this parallel data is divided into groups, it is the 1st group that the method for grouping is the 1st and the 2nd, and the 2nd and the 3rd is the 2nd group, and the 3rd and the 4th is the 3rd group, the 65th and the 66th is the 65th group, and the 66th and the 1st is the 66th group.Therefore 66 groups have been divided into altogether.As shown in Figure 5.It should be noted that synchronous head should fixedly appear at certain particular group of all parallel datas.Claim that this group is a synchronous head place group, claim the position that is numbered synchronous head of this group.As mentioned above, asynchronous place group pseudo-code character synchronously may appear also.What Fig. 5 represented is the input data of 66 bit bit wides after the parallelization.In the example that Fig. 5 represents, it is illegal that the 1st group of data " 00 " are differentiated the result through legitimacy, and the 2nd, 32,65,66 groups of data results after legitimacy is differentiated are legal.The position of synchronous head is 32, and pseudo-synchronous code character occurred at the 2nd, 65,66 groups.
66 groups of data are differentiated to determine whether respectively organize data constitutes legal synchronous code, drawn 66 legitimacies and differentiate the result.If promptly the 1st group two parallel-by-bit data can constitute legal synchronous code, then the 1st group legitimacy differentiation result is " legal ", if the 1st group two parallel-by-bit data can not constitute legal synchronous code, then the 1st group legitimacy differentiation result is " illegally "; If the 2nd group two parallel-by-bit data can constitute legal synchronous code, then the 2nd group legitimacy differentiation result is " legal ", if the 2nd group two parallel-by-bit data can not constitute legal synchronous code, then the 2nd group legitimacy differentiation result is " illegally ", the rest may be inferred, and the legitimacy that just can obtain whole 66 groups of data is differentiated the result.It should be noted that can be for " legal " except the legitimacy differentiation result of synchronous head place group, and it also is legal that the legitimacy of the pseudo-group at code character place is synchronously differentiated the result.But to continuous abundant above-mentioned parallel data, it is legal that synchronous head place group can remain always, and that pseudo-synchronous code place group can not remain always is legal.Therefore differentiate by further continuity, just can find out synchronous head place group, promptly find the position of synchronous head.The method of carrying out the continuity differentiation is, every group legitimacy is differentiated the result, in the cycle, legal at the continuous clock of giving determined number if legitimacy differentiation result was in each clock cycle, then being somebody's turn to do the continuity differentiation result who organizes is continuously, otherwise the continuity differentiation result that should organize is discontinuous.The quantity in above-mentioned continuous clock cycle is called continuity and differentiates length.Continuity differentiates length and the product of clock cycle is called the continuity differentiation cycle.Fig. 6 has expressed the situation that continuity is differentiated.Because pseudo-code character synchronously may appear in above-mentioned parallel data continuously in certain position, so the clock cycle quantity of consecutive sexuality should be enough big, otherwise is not enough to get rid of the pseudo-position at code character place synchronously.
Then, above-mentioned continuity signal is searched for, to obtain the position of synchronous head.The method of search is: differentiate the cycle at first in continuity, at first set an initial searching position value p, this value is the arbitrary integer between 1 to 66.From then on the direction continuous review continuity judgment signal (p+1) that increases progressively along sequence number is played in the position, continuity judgment signal (p+2) or the like is up to continuity judgment signal 66, continue the direction continuous review continuity judgment signal 1 that increases progressively along sequence number then, continuity judgment signal 2, or the like up to continuity judgment signal (p-1).In this checking process, first its continuity is the continuity judgment signal of " continuously ", and the pairing position of its sequence number is the synchronous code position.Two kinds of situations appear in the possibility of result of checking, have promptly found continuous signal and have not found continuous signal.If the continuous signal of found that is then for to search for successfully; If do not find, then be the search failure.
If the ethernet communication system does not have error code, each search can both be successful.But actual communication systems always has error code.In case within the current continuity differentiation cycle, the error code that system occurs causes synchronous head to become asynchronous code character, the continuity search will be failed.In this case, should be original position still with p, restart another time search.
Then,, from parallel data, extract the 64B/66B frame of scrambling, carry out descrambling code, carry out the 64B/66B decoding again, obtain ethernet frame according to the position of synchronous head.
Fig. 3 represents be the 802.3ae-2002 regulation the 64B/66B frame synchornization method the requirement that should satisfy.The always total search of frame synchronization system, check, synchronous three state.In the search attitude, constantly search for synchronous code character by bit in the 64B/66B bit stream of frame synchronization system behind scrambler.If can find synchronous code character, then frame synchronization system enters the check attitude.Checking attitude, the bit stream that frame synchronization system once arrives every the position detection of 64 bits.If can in continuous 63 times are checked, find legal synchronous code character, just illustrate that this position is a synchronous head, frame synchronization system will enter synchronous state.Otherwise if fail all to find legal synchronous code character in continuous 63 times are checked, just illustrate that this position is not is synchronous head, frame synchronization system will be return the search attitude.At synchronous state, the code character in the protection period that frame synchronization system will constitute in per 64 64B/66B frame periods on the continuous review synchronous code position.Found asynchronous sign indicating number type if having more than 16 inspections, frame synchronization system just returns the search attitude.Otherwise frame synchronization system just rests on synchronous state.
What Fig. 6 represented is to carry out the example that continuity is differentiated.In the represented example of Fig. 6, the position of synchronous head is at the 32nd group.First clock cycle after the continuity differentiation cycle begins, the 2nd, 32,33,65,66 groups of data are legal.Other respectively organize data for illegal.Therefore have only the 2nd, 32,33,65, it is continuously that 66 groups continuity is differentiated the result, and other each groups are for discontinuous.The 2nd clock cycle, keep in continuous 5 groups of data, the data of having only the 2nd, 32,66 groups are legal, and the 33rd, 65 group data are illegal, therefore have only the 2nd, 32,66 groups later still continuous the 2nd clock cycle.Before m clock cycle, the 2nd, 32,66 groups of data keep legal always.And m clock cycle, the 2nd group of data become illegally.Then since m clock cycle, the 2nd group differentiation result becomes discontinuous.In (m+1) individual clock cycle, the 66th group of data are also become illegally by legal, and therefore the 66th group of data are also discontinuous by becoming continuously.To the 64th clock cycle, only there be the 32nd group to keep therefore just can finding the position of synchronous head to be positioned at the 32nd group continuously through search.
Claims (5)
1, a kind of method that receives Ethernet data is characterized in that this method may further comprise the steps:
(1) reception is from the synchronous transfer module signal of ethernet line;
(2) user data in the above-mentioned synchronous transfer module signal of extraction;
(3) above-mentioned user data is gone here and there and change, make the serial data of 1 bit bit wide convert the parallel data of 66 bit bit wides to;
(4) respectively whether legal every adjacent two parallel data carried out differentiation, carry out whether continuous differentiation again;
(5) above-mentioned continuity signal is searched for, to obtain the position of synchronous code;
(6) according to above-mentioned synchronous code position, extract the 64B/66B frame of scrambling in the user data from above-mentioned (2) step synchronous transfer module signal, carry out descrambling code, carry out the 64B/66B decoding then, obtain ethernet frame.
2, the method for claim 1, whether legal method is to it is characterized in that differentiating in the step (4) every adjacent two parallel-by-bit data: every adjacent two parallel-by-bit data are carried out XOR, if result of calculation is " 1 ", think that then adjacent two parallel-by-bit data are legal; If result of calculation is " 0 ", think that then adjacent two parallel-by-bit data are for illegal.
3, the method for claim 1, it is characterized in that the method for differentiating every adjacent two parallel-by-bit data continuity in the step (5) is: at given continuous clock in the cycle, if it is legal that the legitimacy differentiation of adjacent two parallel-by-bit data whenever was in each clock cycle, then is continuous; Otherwise be discontinuous.
4, method as claimed in claim 3 is characterized in that wherein said given continuous clock periodicity is taken as 64.
5, the method for claim 1, it is characterized in that in the step (5) continuous signal being carried out search procedure is: set a search and open the beginning position, search for along the direction that positional value increases progressively, first position of satisfying the continuity differentiation is the synchronous code position.
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| CN 200310117177 CN1275437C (en) | 2003-12-05 | 2003-12-05 | A method for receiving Ethernet data |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100403698C (en) * | 2006-08-08 | 2008-07-16 | 华为技术有限公司 | Method and apparatus for testing ethernet connection damage |
| WO2008086751A1 (en) * | 2007-01-16 | 2008-07-24 | Huawei Technologies Co., Ltd. | Transmission method, system and apparatus of overhead information |
| CN101542960B (en) * | 2007-11-13 | 2011-09-21 | 华为技术有限公司 | Method and system for data synchronization in passive optical networks |
| CN101631064B (en) * | 2008-07-14 | 2013-04-17 | 华为技术有限公司 | Method, device and system for sending and receiving data |
| CN103957094B (en) * | 2014-05-13 | 2017-03-15 | 深圳清华大学研究院 | Data block synchrotron and rapid data block synchronization method |
-
2003
- 2003-12-05 CN CN 200310117177 patent/CN1275437C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100403698C (en) * | 2006-08-08 | 2008-07-16 | 华为技术有限公司 | Method and apparatus for testing ethernet connection damage |
| WO2008086751A1 (en) * | 2007-01-16 | 2008-07-24 | Huawei Technologies Co., Ltd. | Transmission method, system and apparatus of overhead information |
| CN101227450B (en) * | 2007-01-16 | 2013-04-24 | 华为技术有限公司 | Equipment, system and method for transmitting spending information |
| CN101542960B (en) * | 2007-11-13 | 2011-09-21 | 华为技术有限公司 | Method and system for data synchronization in passive optical networks |
| US8208809B2 (en) | 2007-11-13 | 2012-06-26 | Huawei Technologies Co., Ltd. | Method and system for data synchronization in passive optical networks |
| US8705964B2 (en) | 2007-11-13 | 2014-04-22 | Huawei Technologies Co., Ltd. | Method and system for data synchronization in passive optical networks |
| CN101631064B (en) * | 2008-07-14 | 2013-04-17 | 华为技术有限公司 | Method, device and system for sending and receiving data |
| CN103957094B (en) * | 2014-05-13 | 2017-03-15 | 深圳清华大学研究院 | Data block synchrotron and rapid data block synchronization method |
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| CN1275437C (en) | 2006-09-13 |
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