CN103957059A - Modulation driving output stage circuit - Google Patents
Modulation driving output stage circuit Download PDFInfo
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- CN103957059A CN103957059A CN201410143134.9A CN201410143134A CN103957059A CN 103957059 A CN103957059 A CN 103957059A CN 201410143134 A CN201410143134 A CN 201410143134A CN 103957059 A CN103957059 A CN 103957059A
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Abstract
The invention provides a modulation driving output stage circuit. The modulation driving output stage circuit comprises a switch control circuit part and a current generation circuit part. The modulation driving output stage circuit receives a pair of difference input voltages and outputs a pair of difference output currents. The current generation circuit part comprises a first transistor, a second transistor, a first reference current source and a second reference current source. The switch control circuit part comprises a third transistor, a fourth transistor, a first phase inverter and a second inverter. The first difference voltage in the pair of difference input voltages is input into the grid electrode of the third transistor through the first phase inverter, the second difference voltage in the pair of difference input voltages is input into the grid electrode of the fourth transistor through the second phase inverter, the drain electrode of the second transistor outputs the first difference current in the pair of difference output currents, and the drain electrode of the first transistor outputs the second difference current in the pair of difference output currents. The modulation driving output stage circuit can increase the voltage margin of a driver.
Description
Technical field
The present invention relates to a kind of modulation drive circuit, relate in particular to a kind of modulation driver output level circuit being applied in laser driver.
Background technology
Along with scientific and technological progress, optical-fibre communications has entered the every field of wire communication, becomes the main flow of Communication Development.Realize fiber optic network communication, the problem that first will solve be exactly how by signal loading on optical-fibre channel, need to carry out light modulation.
The simplest, the most most widely used modulation strategy is on-off keying (OOK, on-off keying) modulation, is that light beam is opened or turn-offed to logical one or logical zero accordingly according to input data.OOK modulation signal has two kinds of implementations, i.e. external modulation and directly modulation.External modulation is to realize modulation with the light stable power of external modulator change laser output, and whole system complex structure is with high costs, is unfavorable for integrated and miniaturization.Directly modulation is the drive current of directly controlling semiconductor laser by information flow, thereby the variation that obtains power output realizes modulation, this modulation system is simple, can ensure good linear working range and bandwidth, therefore in optical fiber telecommunications system, is widely used.
Traditional modulation driver output level circuit 11 as shown in fig. 1, comprises three transistor M
11, M
12, M
13.Transistor M
13drain electrode be connected in transistor M
11with transistor M
12source electrode, transistor M
13source ground, transistor M
13grid input offset voltage V
mOD.Transistor M
11drain electrode be connected in the output of semiconductor laser LD, the input of semiconductor laser LD is connected in supply voltage VDD.Transistor M
12drain electrode be connected in supply voltage VDD by resistance.Transistor M
11with transistor M
12grid receive a pair of difference input voltage (V
iP, V
iN), transistor M
11with transistor M
12drain electrode export a pair of difference output current to drive semiconductor laser LD.In the time that supply voltage VDD is lower, the nargin of driver may be not enough to ensure transistor M
11, M
12quick switching.In addition, in the time of transmission data, work as V
iPwhile jumping to low level from high level, due to channel charge injection effect and and clock feed-through effect, transistor M
11parasitic capacitance C
gB11, C
gD11can inject negative electrical charge to semiconductor laser LD by drain terminal, thereby increased the fall time of semiconductor laser LD drive current; As the in-phase end V of input voltage
iPduring from low transition to high level, due to clock feed-through effect, transistor M
11parasitic capacitance C
gD11, C
gS11can in path, inject positive charge by drain terminal and source, thereby the rise time of semiconductor laser drive current is increased.
Therefore, those skilled in the art is devoted to develop a kind of modulation driver output level circuit, to solve the defect in conventional art.
Summary of the invention
Because the above-mentioned defect of prior art, technical problem to be solved by this invention is to provide a kind of modulation driver output level circuit, it can increase the voltage margin of driver, to avoid supply voltage driver when low to make the transistorized problem that cannot switch fast because nargin is not enough.
For achieving the above object, the invention provides a kind of modulation driver output level circuit, comprise ON-OFF control circuit part and current generating circuit part, modulation driver output level circuit receives a pair of difference input voltage, exports a pair of difference output current; Current generating circuit part comprises the first transistor, transistor seconds, the first reference current source and the second reference current source, and ON-OFF control circuit part comprises the 3rd transistor, the 4th transistor, the first inverter and the second inverter; The drain electrode of the first transistor connects supply voltage by the first reference current source, and the drain electrode of transistor seconds connects supply voltage by the second reference current source; The 3rd transistor and the 4th transistorized source electrode ground connection respectively, the 3rd transistorized drain electrode is connected in the source electrode of the first transistor, and the 4th transistorized drain electrode is connected in the source electrode of transistor seconds; The first differential voltage in a pair of difference input voltage is input to the 3rd transistorized grid by described the first inverter, and the second differential voltage in a pair of difference input voltage is input to the 4th transistorized grid by the second inverter; The first difference current in a pair of difference output current is exported in the drain electrode of transistor seconds, and the second difference current in a pair of difference output current is exported in the drain electrode of the first transistor.
In preferred embodiments of the present invention, ON-OFF control circuit part also comprises the 5th transistor, the 6th transistor, the 3rd inverter and the 4th inverter, the input of the 3rd inverter is connected in the output of the first inverter, the output of the 3rd inverter is connected in the 5th transistorized grid, the 5th transistorized source electrode and drain electrode are connected to the 3rd transistorized drain electrode, the input of the 4th inverter is connected in the output of the second inverter, the output of the 4th inverter is connected in the 6th transistorized grid, the 6th transistorized source electrode and drain electrode are connected to the 4th transistorized drain electrode.
In preferred embodiments of the present invention, the first transistor, transistor seconds, the 3rd transistor and the 4th transistor are NMOS field effect transistor, and the 5th transistor AND gate the 6th transistor is PMOS field effect transistor.
In preferred embodiments of the present invention, current generating circuit part also comprises the 7th transistor, the 8th transistor, the 9th transistor, the tenth transistor, the 3rd reference current source and the 4th reference current source; The 7th transistorized grid is connected in the output of the 3rd inverter, and the 7th transistorized drain electrode is connected in the source electrode of the first transistor, and the 7th transistorized source electrode is by the 3rd reference current source ground connection; The 8th transistorized grid is connected in the output of the 4th inverter, and the 8th transistorized drain electrode is connected in the source electrode of transistor seconds, and the 8th transistorized source electrode is by the 4th reference current source ground connection; The 9th transistorized source electrode is connected in the 7th transistorized source electrode, and the 9th transistorized drain electrode is connected in supply voltage; The tenth transistorized source electrode is connected in the 8th transistorized source electrode, and the tenth transistorized drain electrode is connected in supply voltage.
In preferred embodiments of the present invention, the 7th transistor, the 8th transistor, the 9th transistor and the tenth transistor are NMOS field effect transistor.
In preferred embodiments of the present invention, the current value I of the first difference current
oP=I
d2-I
rEF2, wherein I
d2for the drain current of transistor seconds, I
rEF2it is the output current of the second reference current source; The current value I of the second difference current
oN=I
d1-I
rEF1, wherein I
d1for the drain current of the first transistor, I
rEF1it is the output current of the first reference current source.
In sum, modulation driver output level circuit provided by the invention, the direct ground connection of the 3rd transistor AND gate the 4th transistorized source electrode, with the voltage remaining that reduces to consume on transistor, thereby has increased the voltage margin of driver; Even in the time that supply voltage is lower, also can ensure transistorized quick switching.
Below with reference to accompanying drawing, the technique effect of design of the present invention, concrete structure and generation is described further, to understand fully object of the present invention, feature and effect.
Brief description of the drawings
Figure 1 shows that traditional modulation driver output level circuit;
Figure 2 shows that the modulation driver output level circuit of a preferred embodiment of the present invention.
Embodiment
The modulation driver output level circuit that is illustrated in figure 2 a preferred embodiment of the present invention, it is the circuit of the right and left symmetry.Modulation driver output level circuit comprises ON-OFF control circuit part 22 and current generating circuit part 21.ON-OFF control circuit part 22 receives difference input voltage (V
iP, V
iN), wherein difference input voltage comprises the first differential voltage V
iPwith the second differential voltage V
iN.Current generating circuit part 21 is connected in ON-OFF control circuit part 22, and under the control of ON-OFF control circuit part 22, exports difference output current (I
oP, I
oN), wherein difference input voltage comprises the first difference current I
oPwith the second difference current I
oN.
In an embodiment of the present invention, current generating circuit part 21 comprises the first transistor M
1, transistor seconds M
2, the 7th transistor M
7, the 8th transistor M
8, the 9th transistor M
9, the tenth transistor M
10, the first reference current source I
rEF1, the second reference current source I
rEF2, the 3rd reference current source I
rEF3and the 4th reference current source I
rEF4.ON-OFF control circuit part 22 comprises the 3rd transistor M
3, the 4th transistor M
4, the 5th transistor M
5, the 6th transistor M
6, the first inverter INV
1, the second inverter INV
2, the 3rd inverter INV
3and the 4th inverter INV
4.Wherein, the first transistor M
1, transistor seconds M
2, the 3rd transistor M
3, the 4th transistor M
4, the 7th transistor M
7, the 8th transistor M
8, the 9th transistor M
9and the tenth transistor M
10be NMOS field effect transistor; The 5th transistor M
5with the 6th transistor M
6be PMOS field effect transistor.So, the present invention is not limited to this.
In an embodiment of the present invention, the brilliant M of the 3rd transistor
3with the 4th transistor M
4respectively ground connection of source electrode.The 3rd transistor M
3drain electrode be connected in the first transistor M
1source electrode, the 4th transistor M
4drain electrode be connected in transistor seconds M
2source electrode.The 3rd transistor M
3grid be connected in the first inverter INV
1output, the first differential voltage V
iPby the first inverter INV
1be input to the 3rd transistor M
3grid.The 4th transistor M
4grid be connected in the second inverter INV
2output, the second differential voltage V
iPby the first inverter INV
1be input to the 3rd transistor M
3grid.The 3rd inverter INV
3input be connected in the first inverter INV
1output, the 3rd inverter INV
3output be connected in the 5th transistor M
5grid and the 7th transistor M
7grid.The 5th transistor M
5source electrode and drain electrode be connected to the 3rd transistor M
3drain electrode.The 4th inverter INV
4input be connected in the second inverter INV
2output, the 4th inverter INV
3output the 6th transistor M
6grid and the 8th transistor M
8grid.The 6th transistor M
6source electrode and drain electrode be connected to the 4th transistor M
4drain electrode.The 7th transistor M
7drain electrode be connected in the first transistor M
1source electrode, the 7th transistor M
7source electrode by the 3rd reference current source I
rEF3ground connection.The 8th transistor M
8drain electrode be connected in transistor seconds M
1source electrode, the 8th transistor M
8source electrode by the 4th reference current source I
rEF4ground connection.The 9th transistor M
9source electrode be connected in the 7th transistor (M
7) source electrode, the 9th transistor M
9drain electrode be connected in supply voltage VDD, the 9th transistor M
9grid receive bias voltage V
bN.The tenth transistor M
10source electrode be connected in the 8th transistor M
8source electrode, the tenth transistor M
10drain electrode be connected in supply voltage VDD, the tenth transistor M
10grid receive bias voltage V
bN.The first transistor M
1drain electrode by the first reference current source I
rEF1connect supply voltage VDD, the first transistor M
1drain electrode export the second difference current I
oN.Transistor seconds M
2drain electrode by the second reference current source I
rEF2connect supply voltage VDD, transistor seconds M
2drain electrode export the first difference current I in a pair of difference output current
oP.
In an embodiment of the present invention, in the time of transmission mathematical logic " 0 ", the first differential voltage V
iPfor low level, the second differential voltage V
iNfor high level.The first differential voltage V
iPvoltage through the first inverter INV
1effect after become high level from low level, i.e. the 3rd transistor M
3grid voltage be high level, the 3rd transistor M
3open; The first differential voltage V
iPthrough the first inverter INV
1with the 3rd inverter INV
3effect after be still low level, i.e. the 7th transistor M
7grid voltage be low level, the 7th transistor M
7close.The second differential voltage V
iNthrough the second inverter INV
2effect after become low level from high level, i.e. the 4th transistor M
4grid voltage be low level, the 4th transistor M
4close; The second differential voltage V
iNthrough the second inverter INV
2with the 4th inverter INV
4effect after be still high level, i.e. the 8th transistor M
8grid voltage be high level, the 8th transistor M
8open.Therefore, the first difference current I
oPthere is no electric current output; But, by the second reference current source I
rEF2, transistor seconds M
2, the 8th transistor M
8, the 4th reference current source I
rEF4the path of composition makes transistor seconds M
2still remain on open mode.The second difference current I
oNthere is electric current output.Due to the first reference current source I in reality
rEF1much smaller than the second difference current I
oN, thereby the second difference current I
oNthe current value of output is I
oN=I
d1-I
rEF1≈ I
d1, wherein I
d1for the first transistor M
1drain current.Now, the 5th transistor M
5raceway groove in assemble positive charge, the 6th transistor M
6raceway groove in assemble negative electrical charge.
In like manner, in the time of transmission mathematical logic " 1 ", the first differential voltage V of input voltage
iPfor high level, the second differential voltage V
iNfor low level.Now, the 4th transistor M
4with the 7th transistor M
7open the 3rd transistor M
3with the 8th transistor M
8close.The second difference current I
oNthere is no electric current output, but, by the first reference current source I
rEF1, the first transistor M
1, the 7th transistor M
7, the 3rd reference current I
rEF3the path of composition makes transistor M
1still remain on open mode.The first difference current I
oPthere is electric current output, and the first difference current I
oPthe current value of output is I
oP=I
d2-I
rEF2≈ I
d2(reference current source I
rEF2much smaller than the first difference current I
oP), wherein I
d2for transistor seconds M
2drain current.Now, the 6th transistor M
6raceway groove in assemble positive charge, the 5th transistor M
5raceway groove in assemble negative electrical charge.
Jumped to by logical zero in the process of logical one in transmission data, with the second differential voltage V
iNfor example, the 4th transistor M
4grid voltage by low transition to high level (the 4th transistor M
4open from closing to become), the 6th transistor M
6grid voltage jump to low level by high level, transmission mathematical logic the 6th transistor M when " 0 "
6the negative electrical charge of assembling in raceway groove is by the 4th transistor M
4absorb, thereby accelerated the 4th transistor M
4opening speed, reduced rise time of difference output current.In like manner, jumped in the process of logical zero the 4th transistor M by logical one in transmission data
4grid voltage jump to low level (the 4th transistor M by high level
4close from opening to become), the 6th transistor M
6grid voltage by low transition to high level, the 4th transistor M
4negative electrical charge in raceway groove is by the 6th transistor M
6the positive charge of assembling absorbs, thereby has accelerated the 4th transistor M
4closing velocity, reduced fall time of difference output current.As from the foregoing, the 5th transistor M5 and the 6th transistor M
6in circuit, be equivalent to " virtual " switch, only need suitable the 5th transistor M that chooses
5, the 6th transistor M
6kind and size so that itself and the 3rd transistor M
3, the 4th transistor M
4match, just can weaken the impact of channel charge injection effect, suppress clock feed-through effect.
In on the other hand, as the 3rd transistor M
3or the 4th transistor M
4while opening, the computing formula of its equivalent resistance is R=1/[μ
nc
ox(V
gS4-V
tH4) W
4/ L
4], wherein, μ
nfor electron mobility, C
oxfor the gate oxide electric capacity of unit are, V
gS4be the 4th transistor M
4voltage between grid and source electrode, V
tH4be the 4th transistor M
4overdrive voltage, W
4be the 4th transistor M
4grid width, L
4be the 4th transistor M
4grid long.Due to the 3rd transistor M
3with the 4th transistor M
4the direct ground connection of source electrode, compare and there is V compared with the traditional modulation driver output level circuit shown in Fig. 1
gS3,4>V
gS11,12, therefore, its equivalent resistance R
oN3,4<R
oN11,12.,, in the time that difference output current size is identical, consume at the 3rd transistor M
3with the 4th transistor M
4on voltage remaining specific consumption at transistor M
11, M
12on voltage remaining little, thereby increased voltage margin.
In sum, modulation driver output level circuit provided by the invention, the 3rd transistor M
3with the 4th transistor M
4the direct ground connection of source electrode, with the voltage remaining that reduces to consume on transistor, thereby increased the voltage margin of driver, even in the time that supply voltage VDD is lower, also can ensure transistorized quick switching; Increase by the 5th transistor M
5with the 6th transistor M
6, weakened the impact of channel charge injection effect, and suppressed clock feed-through effect.In addition, no matter the design of current generating circuit part, makes the first difference current I
oP, the second difference current I
oNwhether there is electric current output, the first transistor M corresponding with it
1, transistor seconds M
2remain at open mode, postpone thereby avoided opening.
More than describe preferred embodiment of the present invention in detail.The ordinary skill that should be appreciated that this area just can design according to the present invention be made many modifications and variations without creative work.Therefore, all technical staff in the art, all should be in by the determined protection range of claims under this invention's idea on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment.
Claims (6)
1. a modulation driver output level circuit, comprises ON-OFF control circuit part (22) and current generating circuit part (21), it is characterized in that, described modulation driver output level circuit receives a pair of difference input voltage (V
iP, V
iN), export a pair of difference output current (I
oP, I
oN); Described current generating circuit part (21) comprises the first transistor (M
1), transistor seconds (M
2), the first reference current source (I
rEF1) and the second reference current source (I
rEF2), described ON-OFF control circuit part (21) comprises the 3rd transistor (M
3), the 4th transistor (M
4), the first inverter (INV
1) and the second inverter (INV
2); Described the first transistor (M
1) drain electrode by described the first reference current source (I
rEF1) connection supply voltage (VDD), described transistor seconds (M
2) drain electrode by described the second reference current source (I
rEF2) connection supply voltage (VDD); Described the 3rd transistor (M
3) and described the 4th transistor (M
4) respectively ground connection of source electrode, described the 3rd transistor (M
3) drain electrode be connected in described the first transistor (M
1) source electrode, described the 4th transistor (M
4) drain electrode be connected in described transistor seconds (M
2) source electrode; The first differential voltage (V in described a pair of difference input voltage
iP) by described the first inverter (INV
1) be input to described the 3rd transistor (M
3) grid, the second differential voltage (V in described a pair of difference input voltage
iN) by the second inverter (INV
2) be input to described the 4th transistor (M
4) grid; Described transistor seconds (M
2) the described a pair of difference output current of drain electrode output in the first difference current (I
oP), described the first transistor (M
1) the described a pair of difference output current of drain electrode output in the second difference current (I
oN).
2. modulation driver output level circuit according to claim 1, is characterized in that, described ON-OFF control circuit part (22) also comprises the 5th transistor (M
5), the 6th transistor (M
6), the 3rd inverter (INV
3) and the 4th inverter (INV
4), described the 3rd inverter (INV
3) input be connected in described the first inverter (INV
1) output, described the 3rd inverter (INV
3) output be connected in described the 5th transistor (M
5) grid, described the 5th transistor (M
5) source electrode and drain electrode be connected to described the 3rd transistor (M
3) drain electrode, described the 4th inverter (INV
4) input be connected in described the second inverter (INV
2) output, described the 4th inverter (INV
4) output be connected in described the 6th transistor (M
6) grid, described the 6th transistor (M
6) source electrode and drain electrode be connected to described the 4th transistor (M
4) drain electrode.
3. modulation driver output level circuit according to claim 2, is characterized in that described the first transistor (M
1), described transistor seconds (M
2), described the 3rd transistor (M
3) and described the 4th transistor (M
4) be NMOS field effect transistor, described the 5th transistor (M
5) and described the 6th transistor (M
6) be PMOS field effect transistor.
4. modulation driver output level circuit according to claim 2, is characterized in that, described current generating circuit part (22) also comprises the 7th transistor (M
7), the 8th transistor (M
8), the 9th transistor (M
9), the tenth transistor (M
10), the 3rd reference current source (I
rEF3) and the 4th reference current source (I
rEF4); Described the 7th transistor (M
7) grid be connected in described the 3rd inverter (INV
3) output, described the 7th transistor (M
7) drain electrode be connected in described the first transistor (M
1) source electrode, described the 7th transistor (M
7) source electrode by described the 3rd reference current source (I
rEF3) ground connection; Described the 8th transistor (M
8) grid be connected in described the 4th inverter (INV
4) output, described the 8th transistor (M
8) drain electrode be connected in described transistor seconds (M
1) source electrode, described the 8th transistor (M
8) source electrode by described the 4th reference current source (I
rEF4) ground connection; Described the 9th transistor (M
9) source electrode be connected in described the 7th transistor (M
7) source electrode, described the 9th transistor (M
9) drain electrode be connected in supply voltage (VDD); Described the tenth transistor (M
10) source electrode be connected in described the 8th transistor (M
8) source electrode, described the tenth transistor (M
10) drain electrode be connected in supply voltage (VDD).
5. modulation driver output level circuit according to claim 4, is characterized in that, described the 7th transistor (M
7), described the 8th transistor (M
8), described the 9th transistor (M
9) and described the tenth transistor (M
10) be NMOS field effect transistor.
6. modulation driver output level circuit according to claim 1, is characterized in that, described the first difference current (I
oP) be: I
oP=I
d2-I
rEF2, wherein I
d2for described transistor seconds (M
2) drain current; Described the second difference current (I
oN) be: I
oN=I
d1-I
rEF1, wherein I
d1for described the first transistor (M
1) drain current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410143134.9A CN103957059B (en) | 2014-04-10 | 2014-04-10 | Modulation driver output level circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410143134.9A CN103957059B (en) | 2014-04-10 | 2014-04-10 | Modulation driver output level circuit |
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| Publication Number | Publication Date |
|---|---|
| CN103957059A true CN103957059A (en) | 2014-07-30 |
| CN103957059B CN103957059B (en) | 2016-05-11 |
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ID=51334297
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114124096A (en) * | 2021-10-20 | 2022-03-01 | 北京无线电测量研究所 | Digital-to-analog conversion chip output structure |
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| WO2007023838A1 (en) * | 2005-08-26 | 2007-03-01 | Rohm Co., Ltd. | Motor drive device, method, and cooling device using the same |
| CN202075655U (en) * | 2011-01-26 | 2011-12-14 | 武汉光华芯科技有限公司 | Band gap reference voltage source circuit with chopping low temperature coefficient |
| CN202210783U (en) * | 2011-09-22 | 2012-05-02 | 四川和芯微电子股份有限公司 | Calculation amplifying circuit |
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|---|---|
| CN103957059B (en) | 2016-05-11 |
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