CN103956996A - High-resolution digital pulse width modulator based on double-frequency and multi-phase clock - Google Patents
High-resolution digital pulse width modulator based on double-frequency and multi-phase clock Download PDFInfo
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Abstract
The invention discloses a high-resolution digital pulse width modulator based on a double-frequency and multi-phase clock to solve the technical problem that an existing high-resolution digital pulse width modulator is low in resolution. According to the technical scheme, the high-resolution digital pulse width modulator comprises a data processing unit Data_pro, a multi-phase clock array Clk11array, a multi-phase clock array Clk22array, a counting unit Cnt1, a counting unit Cnt2, a numerical value equation judging unit Eqd1, a numerical value equation judging unit Eqd2, an and gate logical unit and1, an and gate logical unit and2 and an RS trigger. Two multi-phase clock arrays are obtained by carrying out phase shifting, frequency doubling and and processing on two clock signals with different frequencies. The counting clock at the corresponding phase position to carry out the logic operation according to input digital signals to obtain an output pulse width modulation signal with the corresponding duty ratio, and the resolution ratio of the digital pulse width modulator is increased.
Description
Technical field
The present invention relates to a kind of high-resolution digital pulse width modulator, particularly relate to a kind of high-resolution digital pulse width modulator based on double frequency multiphase clock.
Background technology
In DC-DC converter, raising switching frequency is conducive to switching power supply and realizes miniaturization and lighting.For digital DC-DC converter, for fear of the generation of Limit Cycle Phenomena, require the resolution of digital pulse-width modulator (DPWM:Digital Pulse Width Modulation) higher than the resolution of ADC.For example, the DC-DC converter for switching frequency up to several MHz, its switch periods is only hundreds of nanoseconds, this has proposed great challenge to design high-resolution DPWM.
The common method that realizes DPWM comprises counter process and postpones collimation method.In order to realize high-resolution DPWM, as adopted counter process, require the clock frequency of counter up to several GHz, as adopted, postpone collimation method, require high-precision delay cell and large-scale delay line.In addition, also can utilize FPGA to realize DPWM, often adopt the method that counter combines with multiphase clock to realize.
With reference to Fig. 4.Document " FPGA based Digital Control with High-Resolution Synchronous DPWM and High-Speed Embedded A/D Converter; IEEE Applied Power Electronics Conference and Exposition – APEC; pp:1360-1366,2009 " discloses a kind of mixed type DPWM structure realizing based on FPGA.This DPWM utilizes the Clock management module generation of FPGA inside to have 8 phase clocks of same frequency, thereby with lower counter clock frequency, realizes the DPWM of high-resolution.This mixed type DPWM utilizes counter (N-bits Counter) to carry out after coarse adjustment pulsewidth, and recycling 8 phase clocks carry out fine tuning, thereby avoid using high-frequency count clock.But there is following shortcoming in the method: along with the further raising of digital DC-DC converter switches frequency, still exigent counter clock frequency, the multiphase clock number that FPGA internal direct is practiced midwifery raw is in addition relatively less, cannot meet the desired split-second precision resolution of DPWM in high-frequency digital DC-DC converter.
Summary of the invention
In order to overcome the low deficiency of existing high-resolution digital pulse width modulator resolution, the invention provides a kind of high-resolution digital pulse width modulator based on double frequency multiphase clock.This modulator comprise data processing unit Data_pro, multiphase clock array Clk11array, multiphase clock array Clk22array, counting unit Cnt1, counting unit Cnt2, numerical value equate identifying unit Eqd1, numerical value equate identifying unit Eqd2, with gate logic unit and1, with gate logic unit and2 and rest-set flip-flop RS trigger.The present invention utilizes two frequencies differences but close clock signal is processed by these two clock signals are carried out respectively to phase shift, frequency multiplication and logical AND, obtains the multiphase clock array of two different frequencies.Then according to supplied with digital signal, select the counting clock of respective phase to carry out logical operation, produce set SET and the reset RESET control signal of rest-set flip-flop, finally obtain the output pulse width modulation signal of corresponding duty ratio, can improve the resolution of digital pulse-width modulator.
The technical solution adopted for the present invention to solve the technical problems is: a kind of high-resolution digital pulse width modulator based on double frequency multiphase clock, is characterized in: comprise data processing unit Data_pro, multiphase clock array Clk11array, multiphase clock array Clk22array, counting unit Cnt1, counting unit Cnt2, numerical value equate identifying unit Eqd1, numerical value equate identifying unit Eqd2, with gate logic unit and1, with gate logic unit and2 and rest-set flip-flop RS trigger.
Supplied with digital signal data_in[P0:0] after data processing unit Data_pro processes, the data data_inR[P1:0 of controlled rest-set flip-flop input R] and the data data_inS[P2:0 of input S], supplied with digital signal data_in[P0:0], data data_inR[P1:0] and data data_inS[P2:0 be decimal system positive integer.
Data data_inR[P1:0] be divided into high power and position data data_inRH[P1:Q] and low power and position data data_inRL[Q-1:0]; Data data_inS[P2:0] be divided into high power and position data data_inSH[P2:Q] and low power and position data data_inSL[Q-1:0].
The input signal of multiphase clock array Clk11array is that frequency is f
1, the cycle is T
1clock signal C lk1, first produce frequency and be f
1but phase place differs T successively
1the N of/N clock signal C lk11[0～(N-1)], wherein the duty ratio of each clock signal is 1/N.Produce again frequency and be N * f
1but phase place differs T successively
1m the clock signal C lk11Nx[0 of/(N * M)～(M-1)], the duty ratio of each clock signal is 1/M.Then, by this N clock signal C lk11[0～(N-1)] and M clock signal C lk11Nx[0～(M-1)] and carry out respectively logical AND processing, obtaining frequency is f
1, phase place differs T successively
1n * M clock signal array Clk11array[0～(N * M-1) of/(N * M)].
Multiphase clock array Clk11array[0～(N * M-1)] another input signal be data_inRL[Q-1:0], select wherein 1 clock signal output corresponding in multiphase clock array.
The input signal of multiphase clock array Clk22array is that frequency is f
2, the cycle is T
2clock signal C lk2, first produce frequency and be f
2but phase place differs T successively
2the N of/N clock signal C lk22[0～(N-1)], wherein the duty ratio of each clock signal is 1/N.Produce again frequency and be N * f
2but phase place differs T successively
2m the clock signal C lk22Nx[0 of/(N * M)～(M-1)], the duty ratio of each clock signal is 1/M.Then, by this N clock signal C lk22[0～(N-1)] and M clock signal C lk22Nx[0～(M-1)] and carry out respectively logical AND processing, obtaining frequency is f
2, phase place differs T successively
2n * M clock signal array Clk22array[0～(N * M-1) of/(N * M)].
Multiphase clock array Clk22array[0～(N * M-1)] another input signal be data_inSL[Q-1:0], select wherein 1 clock signal output corresponding in multiphase clock array.
At system initial time, counting unit Cnt2 is since 0 counting, clock signal array Clk22array[0～(N * M-1) wherein] in the phase place clock signal C lk22array[0 that is 0] be counting clock, when the count value of counting unit Cnt2 equals high power and position data data_inSH[P2:Q] time, numerical value equates that the output of identifying unit Eqd2 module becomes 1 from 0, as input signal data_inSL[Q-1:0] corresponding multiphase clock array Clk22array[0～(N * M-1)] in clock signal high level while arriving, become 1 with gate logic unit and2 output, the S end that is rest-set flip-flop RS trigger is set to 1, output pulse width modulation signal DPWM_out exports high level.
Simultaneously, at system initial time, counting unit Cnt1 is since 0 counting, Clk11array[0～(N * M-1) wherein] in the phase place clock signal C lk11array[0 that is 0] be counting clock, when the count value of counting unit Cnt1 equals high power and position data data_inRH[P1:Q] time, numerical value equates that the output of identifying unit Eqd1 module becomes 1 from 0, as input signal data_inRL[Q-1:0] corresponding multiphase clock array Clk11array[0～(N * M-1)] in clock signal high level while arriving, become 1 with gate logic unit and1 output, the R end that is rest-set flip-flop RS trigger is set to 1, output pulse width modulation signal DPWM_out output low level.
Described multiphase clock array Clk11array is different with the frequency of multiphase clock array Clk22array, has N * M phase clock simultaneously, and the duty ratio of each phase clock is 1/ (N * M).
Described supplied with digital signal data_in[P0:0] be directly proportional to the duty ratio of output pulse width modulation signal DPWM_out.
The invention has the beneficial effects as follows: this modulator comprise data processing unit Data_pro, multiphase clock array Clk11array, multiphase clock array Clk22array, counting unit Cnt1, counting unit Cnt2, numerical value equate identifying unit Eqd1, numerical value equate identifying unit Eqd2, with gate logic unit and1, with gate logic unit and2 and rest-set flip-flop RS trigger.The present invention utilizes two frequencies differences but close clock signal is processed by these two clock signals are carried out respectively to phase shift, frequency multiplication and logical AND, obtains the multiphase clock array of two different frequencies.Then according to supplied with digital signal, select the counting clock of respective phase to carry out logical operation, produce set SET and the reset RESET control signal of rest-set flip-flop, finally obtain the output pulse width modulation signal of corresponding duty ratio, improved the resolution of digital pulse-width modulator.
Below in conjunction with the drawings and specific embodiments, the present invention is elaborated.
Accompanying drawing explanation
Fig. 1 is the circuit diagram that the present invention is based on the high-resolution digital pulse width modulator of double frequency multiphase clock.
Fig. 2 is embodiment of the present invention multiphase clock array Clk11array[0～7], wherein, N=4, M=2.
Fig. 3 is the relation curve between embodiment of the present invention input data and output pulse duty factor, f
sw=2MHz, f
1=50MHz, f
2=52MHz, N=4, M=4, duty cycle range is 10%～90%.
Fig. 4 is the circuit diagram of the mixed type DPWM structure of background technology based on FPGA realization.
Embodiment
Following examples are with reference to Fig. 1-3.
The high-resolution digital pulse width modulator that the present invention is based on double frequency multiphase clock comprises the multiphase clock array (Clk11array of data processing unit (Data_pro), two different frequencies, Clk22array), two counting unit (Cnt1, Cnt2), two numerical value equate identifying unit (Eqd1, Eqd2), two and gate logic unit (and1, and2) and a rest-set flip-flop (RS trigger).Data_in[P0:0] be the digital signal of input DPWM, DPWM_out is the pulse width modulating signal of DPWM output, data_in[P0:0] be directly proportional to the duty ratio of DPWM_out.The signal frequency of two multiphase clock array Clk11array and Clk22array is different, but all has N * M phase clock, and the duty ratio of each phase clock is 1/ (N * M).Above-mentioned two multiphase clock arrays are used Clk11array[0～(N * M-1) below] and Clk22array[0～(N * M-1)] represent.
The present invention is based on the operation principle of the high-resolution digital pulse width modulator of double frequency multiphase clock.
If the switch motion cycle of Switching Power Supply is T
sw(frequency is f
sw), the cycle of Clk1 and Clk2 clock signal is respectively T
1(frequency is f
1) and T
2(frequency is f
2), T
swwith T
1and T
2between pass be:
T
sw＝K
1×T
1 (1)
T
sw＝K
2×T
2 (2)
In formula, K
1, K
2for positive integer, establish T here
1>T
2(be f
1<f
2), K
1<K
2.
The duty ratio data data_in[P0:0 of input] after data processing unit (Data_pro) is processed, the data data_inR[P1:0 of two input R of controlled rest-set flip-flop and S] and data_inS[P2:0], here P0, P1, P2 are decimal system positive integer, and the pass of these three data is:
data_inR＝int(data_in/K
2)+mod(data_in/K
2) (3)
data_inS＝mod(data_in/K
2) (4)
In formula, int () represents bracket function, and mod () represents MOD function.
Make 2
q=N * M, Q, N, M are positive integer here, data_inR[P1:0] can be divided into high power and position data data_inRH[P1:Q] and low power and position data data_inRL[Q-1:0]; Data_inS[P2:0] also can be divided into high power and position data data_inSH[P2:Q] and low power and position data data_inSL[Q-1:0].
Multiphase clock array Clk11array[0～(N * M-1)] input signal be that (frequency is f to clock signal C lk1
1, the cycle is T
1).If multiphase clock array Clk11array[0～(N * M-1)] minimum phase be spaced apart t
1, T
1=N * M * t
1.First produce frequency and be f
1but phase place differs T successively
1the N of/N clock signal C lk11[0～(N-1)], wherein the duty ratio of each clock signal is 1/N.Produce again frequency and be N * f
1but phase place differs T successively
1m the clock signal C lk11Nx[0 of/(N * M)～(M-1)], the duty ratio of each clock signal is 1/M.Then, by this N clock signal C lk11[0～(N-1)] and M clock signal C lk11Nx[0～(M-1)] and carry out respectively logical AND processing, can obtain frequency is f
1, but phase place differs T successively
1n * M clock signal array Clk11array[0～(N * M-1) of/(N * M)].
Multiphase clock array Clk11array[0～(N * M-1)] another input signal be data_inRL[Q-1:0], according to the size of these input data, select wherein 1 clock signal output corresponding in multiphase clock array.
Multiphase clock array Clk22array[0～(N * M-1)] input signal be that (frequency is f to clock signal C lk2
2, the cycle is T
2).If multiphase clock array Clk22array[0～(N * M-1)] minimum phase be spaced apart t
2, T
2=N * M * t
2.First produce frequency and be f
2but phase place differs T successively
2the N of/N clock signal C lk22[0～(N-1)], wherein the duty ratio of each clock signal is 1/N.Produce again frequency and be N * f
2but phase place differs T successively
2m the clock signal C lk22Nx[0 of/(N * M)～(M-1)], the duty ratio of each clock signal is 1/M.Then, by this N clock signal C lk22[0～(N-1)] and M clock signal C lk22Nx[0～(M-1)] and carry out respectively logical AND processing, can obtain frequency is f
2, but phase place differs T successively
2n * M clock signal array Clk22array[0～(N * M-1) of/(N * M)].
Multiphase clock array Clk22array[0～(N * M-1)] another input signal be data_inSL[Q-1:0], according to the size of these input data, select wherein 1 clock signal output corresponding in multiphase clock array.
Fig. 2 has provided a N=4, and the multi-phase clock signal of M=2 produces example.Here the frequency of supposing input clock signal Clk1 is f
1, the cycle is T
1.4 clock signal C lk11[0～3] phase place differ successively T
1/ 4, duty ratio is 1/4.2 clock signal C lk114x[0～1] frequency be 4f
1, phase place differs T successively
1/ 8, duty ratio is 1/2.By above two clock signal array Clk11[0～3] and Clk114x[0～1] carry out respectively logical AND operation, can obtain 8 frequencies and be f
1, phase place differs T successively
1/ 8, duty ratio is 1/8 clock array Clk11array[0～7].
At system initial time, counter Cnt2 is since 0 counting, Clk22array[0～(N * M-1) wherein] in the phase place clock signal C lk22array[0 that is 0] be counting clock, when the count value of Cnt2 equals data_inSH[P2:Q] time, the output of Eqd2 module becomes " 1 " from " 0 ", as data_inSL[Q-1:0] corresponding Clk22array[0～(N * M-1)] in clock signal high level while arriving, become " 1 " with door (and2) output, the S end that is rest-set flip-flop is set to " 1 ", and DPWM output becomes high level.
Simultaneously, at system initial time, counter Cnt1 is since 0 counting, Clk11array[0～(N * M-1) wherein] in the phase place clock signal C lk11array[0 that is 0] be counting clock, when the count value of Cnt1 equals data_inRH[P1:Q] time, the output of Eqd1 module becomes " 1 " from " 0 ", as data_inRL[Q-1:0] corresponding Clk11array[0～(N * M-1)] in clock signal high level while arriving, become " 1 " with door (and1) output, the R end that is rest-set flip-flop is set to " 1 ", therefore, DPWM output becomes low level from high level.
DPWM is output as the time width t of high level
pwith whole switch periods T
swratio be duty ratio.
The system initial time of setting up departments is t
0, the output Q rising edge t constantly that arrives
upcan be expressed as:
t
up＝t
0+data_inSH×T
2+data_inSL×t
2＝t
0+data_inS×t
2 (5)
The arrival of output Q trailing edge is t constantly
dwcan be expressed as
t
dw＝t
0+data_inRH×T
1+data_inRL×t
1＝t
0+data_inR×t
1 (6)
The high level pulse width t of DPWM output
pfor
The adjustable minimum pulse width of DPWM, i.e. its temporal resolution (time resolution) t
minfor
In the present invention, owing to having adopted N * M multi-phase clock signal, and utilized cycle poor of two different frequency clock signal C lk1 and Clk2, thereby can realize the more DPWM of high time resolution.Fig. 3 has provided the input data data_in of DPWM and the relation (simulated conditions: f between DPWM output pulse duty factor (10%～90%)
sw=2MHz, f
1=50MHz, f
2=52MHz, N=4, M=4, duty cycle range is 10%～90%).In addition, except multiphase clock array, remaining circuit is all operated under low-frequency clock, and therefore the power consumption of whole DPWM circuit is less.
Claims (3)
1. the high-resolution digital pulse width modulator based on double frequency multiphase clock, is characterized in that: comprise data processing unit Data_pro, multiphase clock array Clk11array, multiphase clock array Clk22array, counting unit Cnt1, counting unit Cnt2, numerical value equate identifying unit Eqd1, numerical value equate identifying unit Eqd2, with gate logic unit and1, with gate logic unit and2 and rest-set flip-flop RS trigger;
Supplied with digital signal data_in[P0:0] after data processing unit Data_pro processes, the data data_inR[P1:0 of controlled rest-set flip-flop input R] and the data data_inS[P2:0 of input S], supplied with digital signal data_in[P0:0], data data_inR[P1:0] and data data_inS[P2:0 be decimal system positive integer;
Data data_inR[P1:0] be divided into high power and position data data_inRH[P1:Q] and low power and position data data_inRL[Q-1:0]; Data data_inS[P2:0] be divided into high power and position data data_inSH[P2:Q] and low power and position data data_inSL[Q-1:0];
The input signal of multiphase clock array Clk11array is that frequency is f
1, the cycle is T
1clock signal C lk1, first produce frequency and be f
1but phase place differs T successively
1the N of/N clock signal C lk11[0～(N-1)], wherein the duty ratio of each clock signal is 1/N; Produce again frequency and be N * f
1but phase place differs T successively
1m the clock signal C lk11Nx[0 of/(N * M)～(M-1)], the duty ratio of each clock signal is 1/M; Then, by this N clock signal C lk11[0～(N-1)] and M clock signal C lk11Nx[0～(M-1)] and carry out respectively logical AND processing, obtaining frequency is f
1, phase place differs T successively
1n * M clock signal array Clk11array[0～(N * M-1) of/(N * M)];
Multiphase clock array Clk11array[0～(N * M-1)] another input signal be data_inRL[Q-1:0], select wherein 1 clock signal output corresponding in multiphase clock array;
The input signal of multiphase clock array Clk22array is that frequency is f
2, the cycle is T
2clock signal C lk2, first produce frequency and be f
2but phase place differs T successively
2the N of/N clock signal C lk22[0～(N-1)], wherein the duty ratio of each clock signal is 1/N; Produce again frequency and be N * f
2but phase place differs T successively
2m the clock signal C lk22Nx[0 of/(N * M)～(M-1)], the duty ratio of each clock signal is 1/M; Then, by this N clock signal C lk22[0～(N-1)] and M clock signal C lk22Nx[0～(M-1)] and carry out respectively logical AND processing, obtaining frequency is f
2, phase place differs T successively
2n * M clock signal array Clk22array[0～(N * M-1) of/(N * M)];
Multiphase clock array Clk22array[0～(N * M-1)] another input signal be data_inSL[Q-1:0], select wherein 1 clock signal output corresponding in multiphase clock array;
At system initial time, counting unit Cnt2 is since 0 counting, clock signal array Clk22array[0～(N * M-1) wherein] in the phase place clock signal C lk22array[0 that is 0] be counting clock, when the count value of counting unit Cnt2 equals high power and position data data_inSH[P2:Q] time, numerical value equates that the output of identifying unit Eqd2 module becomes 1 from 0, as input signal data_inSL[Q-1:0] corresponding multiphase clock array Clk22array[0～(N * M-1)] in clock signal high level while arriving, become 1 with gate logic unit and2 output, the S end that is rest-set flip-flop RS trigger is set to 1, output pulse width modulation signal DPWM_out exports high level,
Simultaneously, at system initial time, counting unit Cnt1 is since 0 counting, Clk11array[0～(N * M-1) wherein] in the phase place clock signal C lk11array[0 that is 0] be counting clock, when the count value of counting unit Cnt1 equals high power and position data data_inRH[P1:Q] time, numerical value equates that the output of identifying unit Eqd1 module becomes 1 from 0, as input signal data_inRL[Q-1:0] corresponding multiphase clock array Clk11array[0～(N * M-1)] in clock signal high level while arriving, become 1 with gate logic unit and1 output, the R end that is rest-set flip-flop RS trigger is set to 1, output pulse width modulation signal DPWM_out output low level.
2. the high-resolution digital pulse width modulator based on double frequency multiphase clock according to claim 1, it is characterized in that: described multiphase clock array Clk11array is different with the frequency of multiphase clock array Clk22array, have N * M phase clock, the duty ratio of each phase clock is 1/ (N * M) simultaneously.
3. the high-resolution digital pulse width modulator based on double frequency multiphase clock according to claim 1, is characterized in that: described supplied with digital signal data_in[P0:0] be directly proportional to the duty ratio of output pulse width modulation signal DPWM_out.
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| US10841016B2 (en) | 2019-01-09 | 2020-11-17 | Nxp Usa, Inc. | Apparatuses and methods involving independent modulations of a digital clock signal for different frequency domains |
| CN110719089A (en) * | 2019-11-07 | 2020-01-21 | 亚瑞源科技（深圳）有限公司 | Method for controlling digital pulse width modulation resolution |
| CN110719089B (en) * | 2019-11-07 | 2022-07-01 | 亚瑞源科技（深圳）有限公司 | Method for controlling digital pulse width modulation resolution |
| CN111555738A (en) * | 2020-05-29 | 2020-08-18 | 上海中核维思仪器仪表有限公司 | Ultra-low power consumption pulse width modulation coding chip |
| CN111555738B (en) * | 2020-05-29 | 2021-05-28 | 上海中核维思仪器仪表有限公司 | Ultra-low power consumption pulse width modulation coding chip |
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