CN110719089B - Method for controlling digital pulse width modulation resolution - Google Patents
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Abstract
A method for controlling digital pulse width modulation resolution is applied to a digital pulse width modulation generator. The method divides the first counter pulse width clock by the first pulse width modulation period clock to generate a first resolution, and then generates a second resolution if the modulation command is confirmed to be received, and generates a third resolution if the modulation command is not confirmed to be received. Wherein the second resolution is greater than the first resolution, and the second resolution is less than the third resolution. The invention can improve the accuracy of controllable resolution without increasing the maximum operating frequency of the electronic element, so that the user can obtain the required output resolution more easily and avoid the limit ring oscillation phenomenon of the output voltage and the ripple phenomenon of the output current, thereby achieving the purposes of convenient operation, power consumption cost saving and output signal quality improvement.
Description
The technical field is as follows:
the present invention relates to a method for controlling resolution, and more particularly, to a method for controlling resolution of digital pulse width modulation applied to a digital pulse width modulation generator.
Background
In an analog circuit, the value of an analog signal can be changed continuously, almost any value can be extracted in time and the amplitude of the value, and the input and the output are changed linearly. Analog circuits have a number of problems, such as the control signals being prone to drift over time, difficult to adjust, power consumption, susceptibility to noise and environmental interference, etc. Unlike analog circuits, digital circuits take values within a predetermined range, and the output at any time can only be ON or OFF (or referred to as high or low), so that the voltage or current is transmitted to the load according to the ON and OFF of the repetitive pulse sequence. The control method for the repetitive pulse sequence is a Digital Pulse Width Modulation (DPWM) technique, which is a method for digitally encoding an analog signal by modulating a duty ratio (duty ratio) of a square wave using a resolution-adjustable counter, thereby implementing the digital encoding of the analog signal.
However, in order to achieve the required output resolution and avoid limit cycles (limit cycles) of the output voltage, the conventional DPWM usually requires the electronic devices (e.g., CPU, DSP, etc.) to operate at a very high frequency, but the price of the electronic devices suitable for high frequency is high, and the electronic devices consume much power when operating at a high frequency. There is another conventional method, called a dither method, which uses averaging of fast jitter of a plurality of duty cycles within a specific period to achieve equivalent improvement of the resolution of the DPWM, but the dither method is prone to generate higher output voltage and current ripple (ripple).
Therefore, how to design a method for controlling the resolution of digital pulse width modulation, especially under the condition of not increasing the maximum operating frequency of the electronic device, the accuracy of controllable resolution is increased, so that the user can obtain the required output resolution more easily, which is an important subject of research.
The invention content is as follows:
the present invention provides a method for controlling digital pulse width modulation resolution, which can improve the accuracy of controllable resolution without increasing the maximum operating frequency of electronic components, so that the user can obtain the required output resolution more easily, and simultaneously avoid the limit ring oscillation phenomenon of the output voltage and the ripple phenomenon of the output current, thereby achieving the purposes of convenient operation, saving power consumption cost and improving the quality of the output signal.
The technical scheme adopted by the invention is as follows: a method for controlling digital pwm resolution, applied to a digital pwm generator, the method comprising: generating a first counter pulse width clock and a first pulse width modulation period clock, and dividing the value of the first counter pulse width clock by the value of the first pulse width modulation period clock to generate a first resolution; when the modulation instruction is confirmed to be received, the first counter pulse width clock pulse is kept unchanged, a second pulse width modulation periodic clock pulse is generated after the value of the first pulse width modulation periodic clock pulse subtracts a first specific value, and the value of the first counter pulse width clock pulse is divided by the value of the second pulse width modulation periodic clock pulse to generate a second resolution; and when the modulation command is confirmed not to be received, the first pulse width modulation period clock pulse is kept unchanged, the value of the first counter pulse width clock pulse is increased by a second specific value to generate a second counter pulse width clock pulse, and the value of the second counter pulse width clock pulse is divided by the value of the first pulse width modulation period clock pulse to generate a third resolution; the second resolution is greater than the first resolution, and the second resolution is less than the third resolution.
Further, in the method for digital pulse width modulation resolution, a control quantity comprising a plurality of bits is received; and cutting the last bit in the control quantity, and using the last bit in the control quantity as the modulation command.
Further, in the method for digital pulse width modulation resolution, the first specific value is the least significant bit of the duty cycle of the first pulse width modulation periodic clock, and the second specific value is the least significant bit of the duty cycle of the first counter pulse width clock.
Compared with the prior art, the invention has the following beneficial effects:
in the method for controlling the digital PWM resolution according to the present invention, for the digital PWM generator, the first resolution is generated by dividing a value of a first counter pulse width clock (duty clock) by a value of a first pulse width modulation period clock (PWM period). Basically, the pulse width modulation period clock in the conventional method is fixed, so the resolution is completely determined by the counter pulse width clock, and the conventional method can only change the resolution by adjusting the counter pulse width clock. However, the conventional method is limited to the maximum operation frequency of the pulse width modulation periodic clock, and thus the accuracy of the controllable resolution cannot be improved.
The present invention controls the first counter pulse width clock and the first pulse width modulation period clock by the modulation command, and can create the second resolution with a value range between the first resolution and the third resolution in a Pulse Frequency Modulation (PFM) manner with a required minimum amplitude without changing the adjustable maximum value of the first pulse width modulation period clock (i.e. the maximum operating frequency of the electronic element).
Therefore, the invention can improve the accuracy of the controllable resolution (namely the digital pulse width modulation resolution) by properly configuring the modulation command, the first specific value and the second specific value, can enable the smaller adjustment amplitude to approach or match the required output resolution, and enables a user to avoid the limit ring oscillation phenomenon of the output voltage and the ripple phenomenon of the output current while more easily obtaining the required output resolution, thereby achieving the purposes of convenient operation, power consumption cost saving and output signal quality improvement. Furthermore, the control of the small-amplitude Pulse Frequency Modulation (PFM) also helps to disperse electromagnetic interference (EMI) in the frequency spectrum, which helps to mitigate the effect of EMI.
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FIG. 1 is a flow chart of a method for controlling digital pulse width modulation resolution according to the present invention;
FIG. 2 is a diagram illustrating a first embodiment of a method for controlling digital pulse width modulation resolution according to the present invention;
FIG. 3A is a diagram illustrating a second embodiment of a method for controlling digital pulse width modulation resolution according to the present invention;
FIG. 3B is a diagram illustrating a third embodiment of a method for controlling digital pulse width modulation resolution according to the present invention;
FIG. 4A is a diagram illustrating a fourth embodiment of a method for controlling digital pulse width modulation resolution according to the present invention;
FIG. 4B is a diagram illustrating a fifth embodiment of the method for controlling resolution of digital pulse width modulation according to the present invention.
The specific implementation mode is as follows:
the following description is given of embodiments of the present invention with reference to specific embodiments, and other advantages and effects of the present invention will be apparent to those skilled in the art from the disclosure of the present invention. The invention is capable of other and different embodiments and its several details are capable of modification and various changes in form and detail can be made without departing from the spirit and scope of the invention.
It should be understood that the structures, ratios, sizes, and numbers of elements shown in the drawings and described in the specification are only used for understanding and reading the present disclosure, and are not used to limit the conditions of the present disclosure, so they have no technical significance, and any structural modifications, ratio changes or size adjustments should fall within the scope of the present disclosure without affecting the function and the achievable purpose of the present disclosure.
The first embodiment is as follows: FIG. 1 is a flowchart illustrating a method for controlling digital pulse width modulation resolution according to the present invention. The method for controlling the resolution of Digital Pulse Width Modulation (DPWM) is mainly applied to a DPWM generator, and comprises the following steps: generating a first counter pulse width clock (duty clock) and a first pulse width modulation period clock (PWM period clock), and dividing the value of the first counter pulse width clock by the value of the first pulse width modulation period clock to generate a first resolution (step S01);
then, a control variable including a plurality of bits is received (step S02). Then, the first to last bit in the control quantity is cut (step S03), and the second to last bit in the control quantity is used as the modulation command (step S04). Then, whether a modulation command is received is confirmed (step S05);
when it is determined that the modulation command is received (step 05, yes), the first counter pulse width clock remains unchanged, and the value of the first pulse width modulation period clock is subtracted by the first specific value to generate a second pulse width modulation period clock (step S06). At this time, the value of the first counter pulse width clock is divided by the value of the second pulse width modulation period clock to generate a second resolution (step S07). Wherein the second resolution is greater than the first resolution;
when it is determined that the modulation command is not received (i.e., no in step 05), the first pwm period clock remains unchanged, and the value of the first counter pulse width clock is incremented by a second specific value to generate a second counter pulse width clock (step S08). At this time, the value of the second counter pulse width clock is divided by the value of the first pulse width modulation period clock to generate the third resolution (step S09). Wherein the second resolution is less than the third resolution. After confirming that the modulation command is not received and the third resolution is generated (step S09), if an abort command (not shown) is not explicitly received or the operation is stopped, the method for controlling the digital pwm resolution according to the present invention re-determines whether the modulation command is received (step S05). In an embodiment of the present invention, the Digital Pulse Width Modulation (DPWM) generator allows 9-bit input, the control amount can be 11-bit, and the prior art processing method directly cuts two bits of the reciprocal to generate the DPWM generator compatible with 9-bit input. The present invention cuts off only the last bit in the control quantity, and the last bit in the control quantity can be used as the modulation command. For example, when the last bit in the control amount is 0, it is determined that the modulation command has not been received, and when the last bit in the control amount is 1, it is determined that the modulation command has been received.
In the method for controlling the digital pulse width modulation resolution according to the present invention, for the digital pulse width modulation generator, the first resolution is generated by dividing the value of the first counter pulse width clock (duty clock) by the value of the first pulse width modulation period clock (PWM period). Basically, the pulse width modulation period clock in the conventional method is fixed, so the resolution is completely determined by the counter pulse width clock, and the conventional method can only change the resolution by adjusting the counter pulse width clock. However, the conventional method is limited to the maximum operation frequency of the pulse width modulation periodic clock, and thus the accuracy of the controllable resolution cannot be improved. The invention controls the first counter pulse width clock and the first pulse width modulation period clock through the modulation instruction, and can create the second resolution with the value range between the first resolution and the third resolution in the way of Pulse Frequency Modulation (PFM) with the required minimum amplitude under the condition of not changing the adjustable maximum value of the first pulse width modulation period clock (namely the maximum operating frequency of the electronic element). In the first embodiment of the present invention, the first specific value may be a Least Significant Bit (LSB) of a duty cycle (duty cycle) of the first pwm period clock, and the second specific value may be a LSB of a duty cycle of the first counter pulse width clock. That is, when the last bit in the controlled variable is 1, the modulation command is considered to have been received, and the last bit in the controlled variable is the least significant bit while the last bit in the controlled variable is being truncated.
Fig. 2 is a schematic diagram illustrating a method for controlling digital pwm resolution according to a first embodiment of the present invention. In the first embodiment of the present invention, the first counter pulse width clock is 20clocks, the first pwm cycle clock is 100clocks, and both the first specific value and the second specific value are 1 clock. As in fig. 2 (a), the first resolution is 20% at this time.
When it is determined that no modulation command is received, the first PWM cycle clock (i.e., 100clocks) remains unchanged (i.e., the maximum operating frequency of the DPWM generator is maintained), and the value of the first counter pulse width clock (i.e., 20clocks) is increased by a second specific value (i.e., 1clock) to generate a second counter pulse width clock (i.e., 21 clocks). Then, as shown in fig. 2 (c), the value of the second counter pulse width clock (i.e., 21clocks) is divided by the value of the first pwm cycle clock (i.e., 100clocks) to generate the third resolution (i.e., 21/100-21%). After confirming that the modulation command is not received and generating the third resolution, if no pause command is explicitly received or the operation is stopped, whether the modulation command is received or not is confirmed again.
When a modulation command is received, the first counter pulse width clock (i.e., 20clocks) remains unchanged, and the first specific value (i.e., 1clock) is subtracted from the first pulse width modulation cycle clock (i.e., 100clocks) to generate a second pulse width modulation cycle clock (i.e., 99 clocks). Then, as shown in fig. 2 (b), the value of the first counter pulse width clock (i.e., 20clocks) is divided by the value of the second pwm cycle clock (i.e., 99clocks) to generate the second resolution (i.e., 20/99 ═ 20.2%).
By analogy, a resolution of 21.2% of (d) in fig. 2 and 22% of (e) in fig. 2 at the next stage can be obtained on the basis of (c) in fig. 2. The first embodiment of the present invention creates 20.2% and 21.2% more resolution than the conventional method without increasing the maximum operating frequency of the DPWM generator, which only provides 20%, 21%, and 22% resolution.
The second embodiment is as follows:
referring to FIG. 3A and FIG. 3B,
as shown in fig. 3A, the second embodiment of the present invention is substantially the same as the first embodiment, except that the first counter pulse width clock is 50 clocks.
When it is determined that no modulation command is received, the first PWM cycle clock (i.e., 100clocks) remains unchanged (i.e., the maximum operating frequency of the DPWM generator is maintained), and the value of the first counter pulse width clock (i.e., 50clocks) is increased by a second specific value (i.e., 1clock) to generate a second counter pulse width clock (i.e., 51 clocks). Then, as shown in fig. 3A (c), the value of the second counter pulse width clock (i.e., 51clocks) is divided by the value of the first pwm cycle clock (i.e., 100clocks) to generate the third resolution (i.e., 51/100-51%). After confirming that the modulation command is not received and generating the third resolution, if no pause command is explicitly received or the operation is stopped, whether the modulation command is received or not is confirmed again.
When the modulation command is confirmed, the first counter pulse width clock (i.e., 50clocks) remains unchanged, and the first specific value (i.e., 1clock) is subtracted from the first pulse width modulation cycle clock (i.e., 100clocks) to generate a second pulse width modulation cycle clock (i.e., 99 clocks). Then, as shown in fig. 3A (b), the value of the first counter pulse width clock (i.e., 50clocks) is divided by the value of the second pwm cycle clock (i.e., 99clocks) to generate the second resolution (i.e., 50/99-50.9%).
By analogy, the resolution at the next stage can be obtained on the basis of (c) in fig. 3A as 51.5% of (d) in fig. 3A and 52% of (e) in fig. 3A. The second embodiment of the present invention creates 50.9% and 51.5% more resolution than the conventional method without increasing the maximum operating frequency of the DPWM generator, which only provides 50%, 51%, and 52% resolution.
The third concrete implementation mode:
as shown in fig. 3B, the third embodiment of the present invention is substantially the same as the second embodiment described above, except that the first specific value and the second specific value are both 2 clocks.
When it is determined that no modulation command is received, the first PWM cycle clock (i.e., 100clocks) remains unchanged (i.e., the maximum operating frequency of the DPWM generator is maintained), and the value of the first counter pulse width clock (i.e., 50clocks) is incremented by a second specific value (i.e., 2clocks) to generate a second counter pulse width clock (i.e., 52 clocks). Then, as shown in fig. 3B (c), the value of the second counter pulse width clock (i.e., 52clocks) is divided by the value of the first pwm cycle clock (i.e., 100clocks) to generate the third resolution (i.e., 52/100-52%). After confirming that the modulation command is not received and generating the third resolution, if no pause command is explicitly received or the operation is stopped, whether the modulation command is received or not is confirmed again.
When a modulation command is received, the first counter pulse width clock (i.e., 50clocks) remains unchanged, and the first counter pulse width clock (i.e., 100clocks) is subtracted from the first counter pulse width clock (i.e., 2clocks) to generate a second counter pulse width modulation cycle clock (i.e., 98 clocks). Then, as shown in fig. 3B (B), the value of the first counter pulse width clock (i.e., 50clocks) is divided by the value of the second pwm cycle clock (i.e., 98clocks) to generate the second resolution (i.e., 50/98-51.02%).
By analogy, the resolution at the next stage can be obtained on the basis of (c) in fig. 3B to be 53.06% of (d) in fig. 3B and 54% of (e) in fig. 3B. The third embodiment of the present invention creates 51.02% and 53.06% better resolution than the conventional method without increasing the maximum operating frequency of the DPWM generator, which only provides 50%, 52%, and 54% resolution.
The fourth concrete implementation mode: please refer to fig. 4A and fig. 4B.
As shown in FIG. 4A, the fourth embodiment of the present invention is substantially the same as the first embodiment, except that the first counter pulse width clock is 80 clocks.
When it is determined that no modulation command is received, the first PWM cycle clock (i.e., 100clocks) remains unchanged (i.e., the maximum operating frequency of the DPWM generator is maintained), and the value of the first counter pulse width clock (i.e., 80clocks) is increased by a second specific value (i.e., 1clock) to generate a second counter pulse width clock (i.e., 81 clocks). Then, as shown in fig. 4A (c), the value of the second counter pulse width clock (i.e., 81clocks) is divided by the value of the first pwm cycle clock (i.e., 100clocks) to generate the third resolution (i.e., 81/100-81%). After confirming that the modulation command is not received and generating the third resolution, if no pause command is explicitly received or the operation is stopped, whether the modulation command is received or not is confirmed again.
When the modulation command is confirmed to be received, the first counter pulse width clock (i.e. 80clocks) is maintained, and the value of the first pulse width modulation cycle clock (i.e. 100clocks) minus the first specific value (i.e. 1clock) generates the second pulse width modulation cycle clock (i.e. 99 clocks). Then, as shown in fig. 4A (b), the value of the first counter pulse width clock (i.e., 80clocks) is divided by the value of the second pwm cycle clock (i.e., 99clocks) to generate the second resolution (i.e., 80/99-80.8%).
By analogy, the resolution at the next stage is 81.8% of (d) in fig. 4A and 82% of (e) in fig. 4A can be obtained on the basis of (c) in fig. 4A. The fourth embodiment of the present invention creates 80.8% and 81.8% more resolution than the conventional method without increasing the maximum operating frequency of the DPWM generator, which only provides 80%, 81% and 82% resolution.
The fifth concrete implementation mode:
as shown in fig. 4B, the fifth embodiment of the present invention is substantially the same as the fourth embodiment, except that the first specific value and the second specific value are both 2 clocks.
When it is determined that no modulation command is received, the first PWM cycle clock (i.e., 100clocks) remains unchanged (i.e., the maximum operating frequency of the DPWM generator is maintained), and the value of the first counter pulse width clock (i.e., 80clocks) is increased by a second specific value (i.e., 2clocks) to generate a second counter pulse width clock (i.e., 82 clocks). Then, as shown in fig. 4B (c), the value of the second counter pulse width clock (i.e., 82clocks) is divided by the value of the first pwm cycle clock (i.e., 100clocks) to generate the third resolution (i.e., 82/100-82%). After confirming that the modulation command is not received and generating the third resolution, if the pause command is not explicitly received or the operation is stopped, whether the modulation command is received is confirmed again.
When the modulation command is confirmed, the first counter pulse width clock (i.e., 80clocks) remains unchanged, and the first specific value (i.e., 2clocks) is subtracted from the first pulse width modulation cycle clock (i.e., 100clocks) to generate the second pulse width modulation cycle clock (i.e., 98 clocks). Then, as shown in fig. 4B (B), the value of the first counter pulse width clock (i.e., 80clocks) is divided by the value of the second pwm cycle clock (i.e., 98clocks) to generate the second resolution (i.e., 80/98-81.63%).
By analogy, the resolution at the next stage can be obtained on the basis of (c) in fig. 4B as 83.67% of (d) in fig. 4B and 84% of (e) in fig. 4B. The fifth embodiment of the present invention creates 81.63% and 83.67% more resolution than the conventional method without increasing the maximum operating frequency of the DPWM generator, which only provides 80%, 82%, and 84% resolution.
The sixth specific implementation mode:
in addition, if the first specific value and the second specific value are not properly configured (e.g., the first specific value is half of the value of the first pwm period clock, and the second specific value is half of the value of the first counter pulse width clock), the resolution adjustment may be out of order, and even the limit ring oscillation phenomenon of the output voltage and the ripple phenomenon of the output current may be caused. For example, in a sixth embodiment (not shown), the first counter pulse width clock is 20clocks and the first PWM cycle clock is 100 clocks. The first specified value is half the value of the first pwm period clock (i.e., 10clocks) and the second specified value is half the value of the first counter pulse width clock (i.e., 50 clocks). At this time, the first resolution is 20%, and the second resolution is 13.33%. The first resolution of the second step (i.e., the next step) is 30% and the second resolution of the next step is 20%. The first resolution of the third step (i.e., the next step) is 40%, and the second resolution of the next step is 26.67%. Only 20%, 30% and 40% resolution can be provided in the conventional manner. However, after receiving the modulation command, the adjustment sequence may be 20% → 13.33% → 30% → 20% → 40% → 26.67%. It can be seen from the above values that, during such modulation, the values show a phenomenon of sudden change (sudden change of high and low oscillations in the waveform diagram), and the modulated values are more and more divergent (13.33% differs from 20% by 6.67%, 20% differs from 30% by 10%, and 26.67% differs from 40% by 13.33%) than the values obtained in the conventional manner, which may cause a limit cycle oscillation phenomenon of the output voltage and a ripple phenomenon of the output current. For this purpose, the first specific value should be less than half the value of the first pulse width modulation period clock, and the second specific value should be less than half the value of the first counter pulse width clock.
Therefore, the invention can improve the accuracy of the controllable resolution (namely the digital pulse width modulation resolution) by properly configuring the modulation command, the first specific value and the second specific value, can enable the smaller adjustment amplitude to approach or match the required output resolution, and enables a user to avoid the limit ring oscillation phenomenon of the output voltage and the ripple phenomenon of the output current while more easily obtaining the required output resolution, thereby achieving the purposes of convenient operation, power consumption cost saving and output signal quality improvement. Further, the control of the small-amplitude Pulse Frequency Modulation (PFM) also helps to disperse electromagnetic interference (EMI) in the frequency spectrum, which helps to mitigate the effects of electromagnetic interference (EMI).
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (5)
1. A method for controlling digital pulse width modulation resolution is applied to a digital pulse width modulation generator, and is characterized in that: the method comprises the following steps:
generating a first counter pulse width clock and a first pulse width modulation period clock, and dividing the value of the first counter pulse width clock by the value of the first pulse width modulation period clock to generate a first resolution;
when the modulation instruction is confirmed to be received, the first counter pulse width clock pulse is kept unchanged, a second pulse width modulation periodic clock pulse is generated after the value of the first pulse width modulation periodic clock pulse subtracts a first specific value, and the value of the first counter pulse width clock pulse is divided by the value of the second pulse width modulation periodic clock pulse to generate a second resolution; and when the modulation command is not received, the first pulse width modulation period clock pulse is kept unchanged, the value of the first counter pulse width clock pulse is increased by a second specific value to generate a second counter pulse width clock pulse, and the value of the second counter pulse width clock pulse is divided by the value of the first pulse width modulation period clock pulse to generate a third resolution;
wherein the second resolution is greater than the first resolution, and the second resolution is less than the third resolution.
2. The method of claim 1, wherein the step of controlling the digital pulse width modulation resolution comprises:
receiving a control quantity comprising a plurality of bits; and cutting the last bit in the control quantity, and using the last bit in the control quantity as the modulation command.
3. The method of claim 1, wherein the step of controlling the digital pulse width modulation resolution comprises:
the first specific value is the least significant bit of the duty cycle of the first PWM periodic clock, and the second specific value is the least significant bit of the duty cycle of the first counter PWM periodic clock.
4. The method of claim 1, wherein the step of controlling the digital pulse width modulation resolution comprises: the first specific value is equal to the second specific value.
5. The method of claim 1, wherein the step of controlling the digital pulse width modulation resolution comprises: the first specific value is less than half of the value of the first pulse width modulation period clock, and the second specific value is less than half of the value of the first counter pulse width clock.
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| CN101689852A (en) * | 2007-06-28 | 2010-03-31 | 密克罗奇普技术公司 | System, method and apparatus having improved pulse width modulation frequency resolution |
| TW201104382A (en) * | 2009-07-27 | 2011-02-01 | Univ Nat Taiwan | Spread spectrum clock generator with programmable spread spectrum |
| CN103956996A (en) * | 2014-04-29 | 2014-07-30 | 西北工业大学 | High-resolution digital pulse width modulator based on double-frequency and multi-phase clock |
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