CN103956890B - A kind of three-phase four-arm photovoltaic combining inverter drain current suppressing method - Google Patents

Abstract

The invention discloses a method for suppressing the leakage current of a three-phase four-arm photovoltaic grid-connected inverter. Respectively with the triangular carrier V _C through the comparator to obtain the logic signals S _a , S _b , S _c , and then make the conduction signal _ST1 corresponding to the three phases of A, B and C; the conduction signal _ST2 and the conduction signal _ST3 respectively Turning on in turns, the control logic signals S _a , S _b , and S _c obtain the switching signals of the three-phase four-arm photovoltaic grid-connected inverter through the logic circuit. The beneficial effect of the present invention is that the system switching signal generation does not require complex space vector modulation, the switching signal generating circuit only needs basic logic circuits, and can be realized by using analog components, the realization process is simple and easy, and at the same time, the common mode voltage of the system can be kept constant, thereby Realize effective suppression of system leakage current.

Description

A method for suppressing the leakage current of a three-phase four-leg photovoltaic grid-connected inverter

technical field

The invention belongs to the field of power electronic conversion, and relates to an inverter control technology from DC power input to AC power output, in particular to a method for suppressing leakage current of a three-phase four-arm photovoltaic grid-connected inverter.

Background technique

Non-isolated three-phase photovoltaic grid-connected inverters are small in size and high in efficiency, and have good application prospects. However, using the traditional three-phase four-leg photovoltaic grid-connected inverter topology and modulation method will lead to a large leakage current in the system. The German VDE-0126-1-1 standard stipulates that if the peak leakage current of the photovoltaic system is greater than 300mA, the photovoltaic grid-connected inverter must be disconnected from the grid within 0.3S. Because the leakage current will cause many hazards, such as causing electromagnetic interference, it will also pose a potential threat to personal safety. Therefore, it is of great significance to solve the leakage current problem of the three-phase four-leg photovoltaic grid-connected inverter.

One of the current leakage current solutions for photovoltaic systems is to ensure a constant common-mode voltage of the system through a modulation strategy. Modulation strategies can be divided into two categories: space vector modulation strategies and carrier modulation strategies. The Chinese patent application number is 201210108752.5, and its title is "A Modulation Method for Reducing Common Mode Voltage of Three-phase PWM Converter". The application uses space vector modulation technology to improve system common mode voltage performance, although the common mode voltage decreases It is one-sixth of the DC bus voltage, but the common-mode voltage cannot be guaranteed to be constant. The Chinese patent application number is 201110292043.8, and its name is "A Control Method for Equal Small Space Vector Carrier Modulation Multilevel Converter". The carrier is compared to get the switch signal. Although this method can improve the output waveform and reduce the harmonic content, it still cannot guarantee the constant common-mode voltage of the system, so the effective suppression of the leakage current cannot be realized.

Contents of the invention

In order to solve the problems existing in the prior art, the object of the present invention is to provide a carrier modulation strategy for suppressing the leakage current of a three-phase four-leg photovoltaic grid-connected inverter. The voltage is constant, so that the leakage current is effectively suppressed.

In order to achieve the above-mentioned purpose of the invention, the present invention is achieved through the following technical solutions:

A three-phase four-arm photovoltaic grid-connected inverter leakage current suppression method, which includes the following steps:

(1) The carrier modulation strategy for the leakage current suppression of the three-phase four-leg photovoltaic grid-connected inverter is realized by the switching signal modulation method, and the modulation wave Respectively and triangular carrier V _C through comparator 1, comparator 2, comparator 3 to obtain logic signals S _a , S _b , S _c ;

(2) The logic circuit after sending the logic signals S _a , S _b , S _c to the comparator obtains the switch signal S _1a S _2a S _1b S _2b S _1c S _2c S _1d S _2d , the specific process is:

Logic signals S _a , S _b and S _c pass through OR gate 1 to obtain logic signal a, logic signals S _a , S _b and S _c pass through AND gate 1 to obtain logic signal b at the same time, and logic signal a and logic signal b pass through exclusive OR gate 1 to get the logic signal c, and the logic signal c gets the logic signal d through the NOT gate 1;

The logic signal S _a and the logic signal d pass through the exclusive OR gate 2 to obtain the logic signal e, the logic signal S _b and the logic signal d pass through the exclusive OR gate 3 to obtain the logic signal f, and the logic signal S _c and the logic signal d pass through the exclusive OR gate 4 to obtain logic signal g;

The turn-on enable signal generator has three working states, and the corresponding three output states are as follows:

1) The turn-on enable signal generator sets the turn-on signal _ST1 to 1, the turn-on signal ST2 to 0, and the turn-on signal _ST3 to 0 within the [0~ _T ] period;

The logic signal e obtains the switch signal S _1a ;

The switching signal S _1a is passed through the NOT gate 2 to obtain the switching signal S _2a;

The logic signal S _b obtains the switching signal S _1b ;

The switching signal S _1b is passed through the NOT gate 3 to obtain the switching signal S _2b ;

The logic signal S _c obtains the switch signal S _1c ;

The switching signal S _1c is passed through the NOT gate 4 to obtain the switching signal S _2c ;

The switch signal S _1a , the switch signal S _1b and the switch signal S _1c pass through the XOR gate 5 to obtain the switch signal S _1d ;

The switching signal S _1d is passed through the NOT gate 5 to obtain the switching signal S _2d ;

2) The turn-on enable signal generator sets the turn-on signal _ST1 to be 0, the turn-on signal ST2 to be 1, and the turn-on signal S _T3 to be 0 within the period [ _T ~2T];

The logic signal S _a obtains the switching signal S _1a ;

The switching signal S _1a is passed through the NOT gate 2 to obtain the switching signal S _2a ;

The logic signal f obtains the switch signal S _1b ;

The switching signal S _1b is passed through the NOT gate 3 to obtain the switching signal S _2b ;

The logic signal S _c obtains the switch signal S _1c ;

The switching signal S _1c is passed through the NOT gate 4 to obtain the switching signal S _2c ;

The switch signal S _1a , the switch signal S _1b and the switch signal S _1c pass through the XOR gate 5 to obtain the switch signal S _1d ;

The switching signal S _1d is passed through the NOT gate 5 to obtain the switching signal S _2d ;

3) The turn-on enable signal generator sets the turn-on signal _ST1 to be 0, the turn-on signal _ST2 to be 0, and the turn-on signal _ST3 to be 1 within the [2T～3T] period;

The logic signal S _a obtains the switching signal S _1a ;

The switching signal S _1a is passed through the NOT gate 2 to obtain the switching signal S _2a ;

The logic signal S _b obtains the switching signal S _1b ;

The switching signal S _1b is passed through the NOT gate 3 to obtain the switching signal S _2b ;

The logic signal g obtains the switch signal S _1c ;

The switching signal S _1c is passed through the NOT gate 4 to obtain the switching signal S _2c ;

The switch signal S _1a , the switch signal S _1b and the switch signal S _1c pass through the XOR gate 5 to obtain the switch signal S _1d;

The switching signal S _1d passes through the NOT gate 5 to obtain the switching signal S _2d .

The switching signal modulation method belongs to the carrier modulation method, and the carrier used is a single carrier. There is no need to judge the sector where the reference vector is located, and there is no need to calculate the vector action time and other complex operations;

Due to the adoption of the above technical solution, compared with the prior art, the present invention has the beneficial effect that the system switch signal generation does not require complicated space vector modulation, and the switch signal generation circuit only needs basic logic circuits, which can be realized by analog components, and the realization process is simple It is easy to implement, and at the same time, it can keep the common mode voltage of the system constant, so as to realize the effective suppression of the leakage current of the system.

Description of drawings

Figure 1 is a schematic diagram of a three-phase four-leg photovoltaic grid-connected inverter

Fig. 2 is the schematic diagram of the switching signal carrier modulation strategy proposed by the present invention

detailed description

The specific implementation manners of the present invention will be described in further detail below in conjunction with the accompanying drawings.

A method for suppressing leakage current of a three-phase four-leg photovoltaic grid-connected inverter: the method includes the following steps:

(1) Figure 1 shows the schematic diagram of a three-phase four-leg photovoltaic grid-connected inverter. First, the modulation wave is given $v_b^{*},v_c^{*};$

(2) Fig. 2 shows the switch signal carrier modulation strategy principle diagram that the present invention proposes, by modulating wave Respectively and triangular carrier V _c through comparator 1, comparator 2, comparator 3 to get the logic signal $S_b,S_c;$

(3) The simple logic circuit after sending the logic signals S _a , S _b , S _c to the comparator obtains the switch signal S _1a S _2a S _1b S _2b S _1c S _2c S _1d S _2d , the specific process is:

Logic signals S _a , S _b and S _c pass through OR gate 1 to obtain logic signal a, logic signals S _a , S _b and S _c pass through AND gate 1 to obtain logic signal b at the same time, and logic signal a and logic signal b pass through exclusive OR gate 1 to get the logic signal c, and the logic signal c passes through the NOT gate 1 to get the logic signal d.

The logic signal S _a and the logic signal d pass through the exclusive OR gate 2 to obtain the logic signal e, the logic signal S _b and the logic signal d pass through the exclusive OR gate 3 to obtain the logic signal f, and the logic signal S _c and the logic signal d pass through the exclusive OR gate 4 to obtain logic signal g.

The turn-on enable signal generator has three working states, and the corresponding three output states are as follows:

1) The turn-on enable signal generator sets the turn-on signal _ST1 to 1, the turn-on signal ST2 to 0, and the turn-on signal _ST3 to 0 within the [0~ _T ] period;

The logic signal e obtains the switch signal S _1a ;

The switching signal S _1a is passed through the NOT gate 2 to obtain the switching signal S _2a ;

The logic signal S _b obtains the switching signal S _1b ;

The switching signal S _1b is passed through the NOT gate 3 to obtain the switching signal S _2b ;

The logic signal S _c obtains the switch signal S _1c ;

The switching signal S _1c is passed through the NOT gate 4 to obtain the switching signal S _2c ;

The switch signal S _1a , the switch signal S _1b and the switch signal S _1c pass through the XOR gate 5 to obtain the switch signal S _1d ;

The switching signal S _1d is passed through the NOT gate 5 to obtain the switching signal S _2d ;

2) The turn-on enable signal generator sets the turn-on signal _ST1 to be 0, the turn-on signal ST2 to be 1, and the turn-on signal S _T3 to be 0 within the period [ _T ~2T];

The logic signal S _a obtains the switching signal S _1a ;

The switching signal S _1a is passed through the NOT gate 2 to obtain the switching signal S _2a ;

The logic signal f obtains the switch signal S _1b ;

The switching signal S _1b is passed through the NOT gate 3 to obtain the switching signal S _2b ;

The logic signal S _c obtains the switch signal S _1c ;

The switching signal S _1c is passed through the NOT gate 4 to obtain the switching signal S _2c ;

The switch signal S _1a , the switch signal S _1b and the switch signal S _1c pass through the XOR gate 5 to obtain the switch signal S _1d ;

The switching signal S _1d is passed through the NOT gate 5 to obtain the switching signal S _2d ;

3) The turn-on enable signal generator sets the turn-on signal _ST1 to be 0, the turn-on signal _ST2 to be 0, and the turn-on signal _ST3 to be 1 within the [2T～3T] period;

The logic signal S _a obtains the switching signal S _1a ;

The switching signal S _1a is passed through the NOT gate 2 to obtain the switching signal S _2a ;

The logic signal S _b obtains the switching signal S _1b ;

The switching signal S _1b is passed through the NOT gate 3 to obtain the switching signal S _2b ;

The logic signal g obtains the switch signal S _1c ;

The switching signal S _1c is passed through the NOT gate 4 to obtain the switching signal S _2c ;

The switch signal S _1a , the switch signal S _1b and the switch signal S _1c pass through the XOR gate 5 to obtain the switch signal S _1d ;

The switching signal S _1d is passed through the NOT gate 5 to obtain the switching signal S _2d ;

Table 1 shows the relationship between different switch states and the system common-mode voltage V _CM , and the switch states shown in Table 1 are realized by the carrier modulation strategy proposed by the present invention in FIG. 2 .

It can be seen from Table 1 that there are 8 kinds of switch states, among which the first and eighth are the cases where the switch states are zero states, and the second to seventh are the cases where the switch states are valid states. It can be seen from Table 1 that the two zero states appear three times in the table, this is because if only the switch state of one of the three bridge arms is changed when the two zero states of 000 and 111 appear, that is, the The high and low levels of the bridge arm will cause the output voltage of the inverter to be unbalanced. Therefore, by adding a simple auxiliary circuit, the three-phase bridge arm and the logic signal d pass through the XOR gate to obtain the corresponding switch signal every T time, that is, the turn-on enable signal generator in Figure 2 switches the conduction signal every T time , corresponding to phases A, B, and C, respectively.

In summary, the 8 switching signals can be divided into 3 situations:

1) In the [0~ _T ] cycle, the conduction signal _ST1 is 1, the conduction signal ST2 is 0, and the conduction signal _ST3 is 0, as shown in the first row and the tenth row in Table 1, through Logic transformation, change the 000 state to 100 state, 111 state to 011 state, and keep the other states in the table unchanged. Take the first line as an example, at this time the switching signals S _1a , S _2b , S _2c , S _1d are all 1, switch signals S _2a , S _1b , S _1c , S _2d are all 0, at this time V _AN =V _DN =V _dc , V _BN =V _CN =0, where V _dc is the photovoltaic cell The voltage at both ends of the board is calculated according to the common-mode voltage formula: V _CM =(V _AN +V _BN +V _CN +V _DN )/4, and the common-mode voltage V _CM =V _dc /2 can be obtained. Similarly, the common-mode voltage can also be guaranteed to be constant in the other seven switching states.

2) In the [ _T ~2T] cycle, the conduction signal _ST1 is 0, the conduction signal ST2 is 1, and the conduction signal _ST3 is 0, as shown in the second row and the eleventh row in Table 1, through Logic transformation, change the 000 state to 010 state, 111 state to 101 state, and keep other states in the table unchanged. Take the second line as an example, at this time the switching signals S _2a , S _1b , S corresponding to the switching tube of the main circuit _2c , S _1d are all 1, the switching signals S _1a , S _2b , S _1c , S _2d are all 0, at this time V _AN =V _CN =0, V _BN =V _DN =V _dc , according to the common mode voltage calculation formula : V _CM =(V _AN +V _BN +V _CN +V _DN )/4, the common mode voltage V _CM =V _dc /2 can be obtained. Similarly, the common-mode voltage can also be guaranteed to be constant in the other seven switching states.

3) In the [2T～3T] period, it is given that the conduction signal _ST1 is 0, the conduction signal _ST2 is 0, and the conduction signal _ST3 is 1, as shown in the third row and the 12th row in Table 1, Through logic conversion, the 000 state is changed to 001 state, the 111 state is changed to 110 state, and the other states in the table remain unchanged. Taking the third row as an example, at this time, the switching signals S _2a and S _2b corresponding to the switching tubes of the main circuit, S _1c , S _1d are all 1, switch signals S _1a , S _1b , S _2c , S _2d are all 0, at this time V _AN =V _BN =0, V _CN =V _DN =V _dc , calculated according to common mode voltage Formula: V _CM =(V _AN +V _BN +V _CN +V _DN )/4, the common mode voltage V _CM =V _dc /2 can be obtained. Similarly, the common-mode voltage can also be guaranteed to be constant in the other seven switching states.

Regardless of whether the logic signals S _a , S _b , or S _c are 0 or 1, the logic conversion is performed through the logic circuit, and the conduction signal _ST1 , the conduction signal ST2 and the conduction signal _ST3 are turned on in turn in different _T periods , and sent to the logic circuit respectively, all the zero states can be turned into effective switching states, and the common mode voltage can be guaranteed to be V _CM =(V _AN +V _BN +V _CN +V _DN )/4=V _dc /2.

To sum up, combining the switching states shown in Table 1 and the logic circuit shown in Figure 2, the common-mode voltage of the system can be kept constant, so as to ensure that the leakage current is effectively suppressed.

Table 1

Claims (2)

1. A method for suppressing leakage current of a three-phase four-arm photovoltaic grid-connected inverter, characterized in that: the method includes the following steps: (1) The carrier modulation strategy for the leakage current suppression of the three-phase four-leg photovoltaic grid-connected inverter is realized by the switching signal modulation method, and the modulation wave Respectively and triangular carrier V _C through comparator 1, comparator 2, comparator 3 to obtain logic signals S _a , S _b , S _c ; (2) The logic circuit after sending the logic signals S _a , S _b , S _c to the comparator obtains the switch signal S _1a S _2a S _1b S _2b S _1c S _2c S _1d S _2d , the specific process is: Logic signals S _a , S _b and S _c pass through OR gate 1 to obtain logic signal a, logic signals S _a , S _b and S _c pass through AND gate 1 to obtain logic signal b at the same time, and logic signal a and logic signal b pass through exclusive OR gate 1 to get the logic signal c, and the logic signal c gets the logic signal d through the NOT gate 1; The logic signal S _a and the logic signal d pass through the exclusive OR gate 2 to obtain the logic signal e, the logic signal S _b and the logic signal d pass through the exclusive OR gate 3 to obtain the logic signal f, and the logic signal S _c and the logic signal d pass through the exclusive OR gate 4 to obtain logic signal g; The turn-on enable signal generator has three working states, and the corresponding three output states are as follows: 1) The turn-on enable signal generator sets the turn-on signal _ST1 to 1, the turn-on signal ST2 to 0, and the turn-on signal _ST3 to 0 within the [0~ _T ] period; The logic signal e obtains the switch signal S _1a ; The switching signal S _1a is passed through the NOT gate 2 to obtain the switching signal S _2a ; The logic signal S _b obtains the switching signal S _1b ; The switching signal S _1b is passed through the NOT gate 3 to obtain the switching signal S _2b ; The logic signal S _c obtains the switch signal S _1c ; The switching signal S _1c is passed through the NOT gate 4 to obtain the switching signal S _2c ; The switch signal S _1a , the switch signal S _1b and the switch signal S _1c pass through the XOR gate 5 to obtain the switch signal S _1d ; The switching signal S _1d is passed through the NOT gate 5 to obtain the switching signal S _2d ; 2) The turn-on enable signal generator sets the turn-on signal _ST1 to be 0, the turn-on signal ST2 to be 1, and the turn-on signal S _T3 to be 0 within the period [ _T ~2T]; The logic signal S _a obtains the switching signal S _1a ; The switching signal S _1a is passed through the NOT gate 2 to obtain the switching signal S _2a ; The logic signal f obtains the switch signal S _1b ; The switching signal S _1b is passed through the NOT gate 3 to obtain the switching signal S _2b ; The logic signal S _c obtains the switch signal S _1c ; The switching signal S _1c is passed through the NOT gate 4 to obtain the switching signal S _2c ; The switch signal S _1a , the switch signal S _1b and the switch signal S _1c pass through the XOR gate 5 to obtain the switch signal S _1d ; The switching signal S _1d is passed through the NOT gate 5 to obtain the switching signal S _2d ; 3) The turn-on enable signal generator sets the turn-on signal _ST1 to be 0, the turn-on signal _ST2 to be 0, and the turn-on signal _ST3 to be 1 within the [2T～3T] period; The logic signal S _a obtains the switching signal S _1a ; The switching signal S _1a is passed through the NOT gate 2 to obtain the switching signal S _2a ; The logic signal S _b obtains the switching signal S _1b ; The switching signal S _1b is passed through the NOT gate 3 to obtain the switching signal S _2b ; The logic signal g obtains the switch signal S _1c ; The switching signal S _1c is passed through the NOT gate 4 to obtain the switching signal S _2c ; The switch signal S _1a , the switch signal S _1b and the switch signal S _1c pass through the XOR gate 5 to obtain the switch signal S _1d ; The switching signal S _1d passes through the NOT gate 5 to obtain the switching signal S _2d . 2. A method for suppressing leakage current of a three-phase four-leg photovoltaic grid-connected inverter according to claim 1, characterized in that: The switching signal modulation method is a carrier modulation method, the carrier used is a single carrier, and there is no need to judge the sector where the reference vector is located, and it is not necessary to calculate the vector action time.