CN103944786A - Self-adaptive count clock data detection method - Google Patents
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Abstract
The invention discloses a self-adaptive count clock data detection method. According to the self-adaptive count clock data detection method, a clock frequency input by a single external load is recognized in real time by means of a local clock according to a three-item counting method involving high level count, low level count and the sum of the high level count and the low level count, and thus automatic recognition of the data of the load is achieved; then, data of two loads are recognized automatically according to a logical combination algorithm, and thus self-adaptive switching of the clock data of the two loads is achieved according to countless switching commands in the system design. Self-adaptive recognition of the data of one of the multiple loads is achieved after expansion, and selection of the clock data of one of the multiple loads is achieved. The self-adaptive count clock data detection method is also suitable for the situations that externally input clock signals are broken clock signals, or constant-level signals or noise wave signals, and the antijamming capability is high.
Description
Technical field
The invention belongs to technical field of satellite communication, particularly, relate to a kind of self adaptation counting clock data detection method, the method is applicable to the self adaptation identification of single channel load, is also applicable to the self adaptation identification of two-way or the above load of two-way.
Background technology
No. nine satellites of remote sensing are first reconnaissance spacecraft constellation systems of China, remote sensing X satellite is the follow-up star of No. nine satellites of remote sensing, there is change in the state of the art of whole star, increased AIS (Automatic identification System ship automatic identification system) loading device, mode of operation adopts the working method with programmable integrated process time-sharing multiplex.For this reason, also there is change in the design of the data processor unit interface of data transmission subsystem, increase AIS input interface, AOS (the senior system in-orbit of Advanced orbiting system) is encoded process before, need to carry out self adaptation real-time selection to AIS and programmable integrated process two-way load data, and traditional Interface design algorithm is by the direct reception & disposal single channel of local clock load data, cannot automatically identify by Dui Gai road load clock data; Switch two paths of data if need, switch by several pipe switching commands, cannot realize the automatic identification of two-way load clock data.
Summary of the invention
The technical problem to be solved in the present invention is, for the deficiencies in the prior art, to provide a kind of self adaptation counting clock data detection method.
In self adaptation counting clock data detection method according to the present invention, utilize local clock to identify in real time by three item count methods (be high level counting, low level counting and low and high level counting and) the external load input clock frequency of single channel, thereby realize the autonomous classification of Dui Gai road load data; Further by logical combination algorithm, can carry out self adaptation identification to two-way load clock data, solve countless pipe switching commands in system and the two-way load clock data self adaptation switching problem that carries out.Multiselect one load data self-adaptive identification method after expansion, selects problem for the load clock data that solves multiselect one.
The technical scheme that the present invention solves the problems of the technologies described above employing comprises:
A kind of self adaptation counting clock data detection method, comprises the following steps:
(1) input clock of single channel load is carried out to Fractional-N frequency, produce frequency-dividing clock; And utilize local clock to sample to frequency-dividing clock, and produce two delayed clocks, i.e. the first delayed clock and the second delayed clock, wherein, the value of divider ratio N is determined according to following formula:
and the value of N is got power side's value of 2;
(2) rising edge that utilizes local clock is sampled when high level and the low level respectively to the second delayed clock, produce respectively the first count value and the second count value, judgement is when the first delayed clock is in rising edge, and the second delayed clock is in the trailing edge moment, whether this first count value is greater than the first counting threshold value and is less than the second counting threshold value, produce the first flag signal corresponding to judged result, and definition is in the time that the first count value is greater than the first counting threshold value and is less than the second counting threshold value, this the first flag signal is high level ' 1 ', otherwise be low level ' 0 ', and,
Judgement when the first delayed clock in trailing edge and the second delayed clock in the rising edge moment, whether the second count value is greater than the first counting threshold value and is less than the second counting threshold value, produce the second flag signal corresponding to judged result, and definition second flag signal in the time that the second count value is greater than the first counting threshold value and is less than the second counting threshold value is high level ' 1 ', otherwise is low level ' 0 ';
Wherein, nominal count value
first counting threshold value=nominal count value-n, the situation that is less than 50% corresponding to input clock duty ratio; Second counting threshold value=nominal count value+n, the situation that is greater than 50% corresponding to input clock duty ratio; The value of amount of redundancy n equals 0.05 times of nominal count value, corresponding to the redundancy requirement of input clock duty ratio 5%, and n>=2;
(3) described the first flag signal and the second flag signal are carried out to logical "or" computing, produce the 3rd flag signal;
(4) judgement is when local clock is during in rising edge, the first count value and the second count value and whether be greater than the second counting threshold value, and produce the 4th flag signal according to judged result, and definition when the first count value and the second count value when being greater than the second counting threshold value, the 4th flag signal is high level ' 0 ', otherwise is low level ' 1 ';
(5) described the 3rd flag signal and the 4th flag signal are carried out to logic "and" operation, produce the effective flag signal of clock, if the effective flag signal of this clock is high level ' 1 ', show that this road load input clock is normal, if the effective flag signal of this clock is low level ' 0 ', show that this road load input clock is abnormal;
(6) according to the synchronism of clock and data, and according to the normal or abnormal judged result of step (5) Zhong Duigai road load input clock, realize the autonomous classification of Dui Gai road load data.
Further, in the situation that thering is M road load input clock, first process according to step (1)-(5) Dui Mei road load input clock, obtain the effective flag signal of M clock that Yu Ge road load input clock is corresponding; Then the effective flag signal of this M clock is carried out to logic " also " computing, produce the effective flag signal of M bit, if the m position signal of the effective flag signal of this M bit is high level, show that m road load clock data is effective, wherein, m=1,2,3 ... M, and M is greater than 1 positive integer; Then, carry out the autonomous classification of load data according to step (6).
The method according to this invention has useful technique effect, comprising:
In the method according to the invention, owing to can the external input clock frequency of single channel being detected in real time, cover the situation as far as possible of clock breaking moment, can independently carry out data identification; The self adaptation switching problem of the two-way load clock data of having realized countless pipe switching commands in system and carry out.By further expanding, method of the present invention is applicable to the time-sharing multiplex of multichannel load data, has solved the self adaptation identification problem of multiselect one load data.It is the situations such as disconnected clock, constant level or clutter that method of the present invention is also applicable to external input clock signal, and antijamming capability is strong.
Brief description of the drawings
Fig. 1 is the design principle block diagram of remote sensing X satellite data processor FPGA when two-way load self-adapting data is identified;
Fig. 2 is the design cycle block diagram that produces the FPGA of the effective flag signal of single channel load input clock;
Fig. 3 is the sequential relationship schematic diagram that produces the effective flag signal of single channel load input clock.
Embodiment
Below in conjunction with the drawings and specific embodiments, self adaptation counting clock data detection method according to the present invention is further described in detail.
The method according to this invention is based on following design principle:
Method of the present invention realizes by FPGA software algorithm, utilize local clock to identify in real time (or detection) to the external load input clock frequency of single channel by three item count methods (be high level counting, low level counting and low and high level counting and), produce the effective flag signal of a high level.Due to clock and data synchronous, by identification clock, can realize autonomous classification and the detection of Dui Gai road load data.
The self-defined nominal count value of this algorithm
consider have ± 5% variation surplus of universal timepiece duty ratio, the value of definition amount of redundancy n is 0.05 times of nominal count value COUNT, and n>=2, thus, can instead release the designing requirement of nominal count value COUNT>=40.Again by
and the value of N is got power side's value of 2, as 1,2,4,8,16,32,64 etc., can determine the value of divider ratio N.When self-defined duty ratio is less than 50%, the first counting threshold value L=nominal count value COUNT-n; When duty ratio is greater than 50%, the second counting threshold value R=nominal count value COUNT+n.
Please refer to Fig. 2 and Fig. 3, self adaptation counting clock data detection method according to the present invention comprises the following steps:
(1) input clock of single channel load is carried out to Fractional-N frequency, produce frequency-dividing clock; And utilize local clock to sample to frequency-dividing clock, and produce two delayed clocks, i.e. the first delayed clock and the second delayed clock, wherein, the value of divider ratio N is determined according to following formula:
and the value of N is got power side's value of 2;
(2) rising edge that utilizes local clock is sampled when high level and the low level respectively to the second delayed clock, produce respectively the first count value and the second count value, judgement when the first delayed clock in rising edge and the second delayed clock in the trailing edge moment, whether this first count value is greater than the first counting threshold value and is less than the second counting threshold value, if its value is greater than the first counting threshold value and is less than the second counting threshold value, produce the first flag signal of high level, otherwise produce low level the first flag signal; And, judgement when the first delayed clock in trailing edge and the second delayed clock in the rising edge moment, whether the second count value is greater than the first counting threshold value and is less than the second counting threshold value, if its value is greater than the first counting threshold value and is less than the second counting threshold value, produce the second flag signal of high level, otherwise, produce low level the second flag signal;
Wherein, nominal count value
first counting threshold value=nominal count value-n, the situation that is less than 50% corresponding to input clock duty ratio; Second counting threshold value=nominal count value+n, the situation that is greater than 50% corresponding to input clock duty ratio; The value of amount of redundancy n equals 0.05 times of nominal count value, corresponding to the redundancy requirement of input clock duty ratio 5%, and n>=2;
(3) the first flag signal and the second flag signal are carried out to logical "or" computing, produce the 3rd flag signal;
(4) judgement is when local clock is during in rising edge, the first count value and the second count value and whether be greater than the second counting threshold value, if its value is greater than the second counting threshold value, produce low level the 4th flag signal, otherwise, the 4th flag signal of generation high level;
(5) the 3rd flag signal and the 4th flag signal are carried out to logic "and" operation, produce the effective flag signal of clock, if the effective flag signal of this clock is high level ' 1 ', show that this road load input clock is normal, if the effective flag signal of this clock is low level ' 0 ', show that this road load input clock is abnormal;
(6) according to the synchronism of clock and data, and according to the normal or abnormal judged result of step (5) Zhong Duigai road load input clock, realize the autonomous classification of Dui Gai road load data.
Input clock interrupts situation analysis: when input load clock interrupts between low period, low level the second count value can continue to add up and be greater than the second counting threshold value; In like manner, while interruption between high period, the first count value of high level can continue to add up and be greater than the second threshold count, therefore, no matter in which kind of situation, when clock interrupts, low and high level count value is greater than the second counting threshold value with meeting owing to adding up, thereby make the 4th flag signal independently be reset to low level, and FPGA is the synchronous processing modes based on clock rise/fall edge to the sampling processing of data, therefore, realize the autonomous classification to clock, be equivalent to realize the autonomous classification to data.
Based on said method, for the situation with two-way load input clock data, realize by the following method the self adaptation identification of two-way load clock data:
(11) utilize step (1)-(5) in above-mentioned self adaptation counting clock data detection method to carry out self adaptation identification to first via load clock signal, finally produce the effective flag signal of the first clock aflag;
(12) similarly, utilize step (1)-(5) in above-mentioned self adaptation counting clock data detection method to carry out self adaptation identification to the second tunnel load clock signal, finally produce the effective flag signal of second clock zflag;
(13) two clock effective flag signal aflag and zflag are carried out to logic " also " computing, produce the effective flag signal of dibit clock flag, in the time that the effective flag signal of this dibit clock flag signal is " 10 ", show that first via load clock data signal is effective; And in the time that the effective flag signal of this dibit clock flag signal is " 01 ", showing that the second tunnel load clock data signal is effective,, " 00 ", " 11 ", according to real work demand self-defining for other logical combination mode of operation.
Similarly, multiselect one load clock data self adaptation identification is the expansion to the identification of two-way load clock data self adaptation, is applicable to multichannel (as M road) load time division multiplexing mode of operation.FPGA design adopts M process module parallel data tupe, that is:
(21) utilize above-mentioned self adaptation counting clock data detection method respectively the input clock of each road input load to be identified, produce the effective flag signal of clock on this road;
(22) the effective flag signal of this M road clock is carried out to logic " also " computing, the final effective flag signal of the M bit flag that produces, flag=flag_1flag_2flag_3 ... flag_m ... flag_M, wherein, corresponding high level figure place Na road load clock data is effective.
Below, taking remote sensing XX satellite data transmission subsystem data processor stand-alone application as example, the method according to this invention is further described in detail.
When remote sensing X satellite data processor is identified two-way load self-adapting data, the design principle of FPGA as shown in Figure 1, need be identified the external load AIS data of two-way and integrated treatment machine data automatically with the clock of local 20MHz.Wherein, the input clock frequency of AIS load is 9.1584MHz, and the input clock frequency of programmable integrated process load is 200KHz.
1, the input clock self adaptation of AIS load counting detects
According to divider ratio
get divider ratio N=64, the nominal count value of AIS load
amount of redundancy n=70 × 0.05=3.5 ≈ 4, the first counting threshold value L=70-4=66, the second counting threshold value R=70+4=74.
Produce FPGA design cycle block diagram according to the effective flag signal of the single channel load input clock shown in Fig. 2, it is as follows that the effective flag signal of input clock of AIS load produces working mechanism:
(1) input clock of Dui Gai road load carries out 64 frequency divisions, produces frequency-dividing clock apclk, and utilizes local clock to sample to frequency-dividing clock apclk, produces respectively two delayed clocks, i.e. the first delayed clock apclk1 and the second delayed clock apclk2;
(2) rising edge that utilizes local clock the second delayed clock apclk2 during in high level sampling produce the first count value cntal_H, and judgement is when the first delayed clock is in rising edge and the second delayed clock during in trailing edge, whether the value of the first count value cntal_H is greater than the first counting threshold value L and is less than the second counting threshold value R, in this way, produce the first flag signal aflag_h of high level; Otherwise, produce low level the first flag signal aflag_h;
Simultaneously, the rising edge that utilizes local clock the second delayed clock apclk2 during in low level sampling produce the second count value cntal_L, and judgement: when the first delayed clock is in trailing edge and the second delayed clock during in rising edge, whether the value of the second count value cntal_L is greater than the first counting threshold value L and is less than the second counting threshold value R, in this way, produce the second flag signal aflag_l of high level; Otherwise, produce low level the second flag signal aflag_l.
(3) the first flag signal aflag_h and the second flag signal aflag_l are carried out to logical "or" computing, generate the 3rd flag signal aflag_m signal;
(4) judgement is when local clock is during in rising edge, and whether the first count value cntal_H and the second count value cntal_L sum cntal_sum are greater than the second counting threshold value R, in this way, produce low level the 4th flag signal aflag_s; Otherwise, the 4th flag signal aflag_s of generation high level;
(5) the 3rd flag signal aflag_m and the 4th flag signal aflag_s are carried out to logic "and" operation, generate the effective flag signal of AIS load clock aflag, in the time that the effective flag signal of this clock aflag is high level ' 1 ', show that AIS load input clock is normal, and in the time that the effective flag signal of this clock aflag is low level ' 0 ', show that AIS load input clock is abnormal.
2, the input clock self adaptation of programmable integrated process load counting detects
According to divider ratio
get divider ratio N=1, without frequency division processing, the nominal count value of programmable integrated process
self-defined amount of redundancy n=50 × 0.05=2.5 ≈ 3, the first counting threshold value ZL=50-3=47, the second counting threshold value ZR=50+3=53.
According to the design cycle block diagram of the FPGA of the effective flag signal of generation single channel load input clock shown in Fig. 2, it is as follows that the effective flag signal of the input clock of programmable integrated process load produces working mechanism:
(1) utilize local clock to sample to the input clock of programmable integrated process, produce two delayed clocks, that is, and the first delayed clock zpclk1 and the second delayed clock zpclk2;
(2) rising edge that utilizes local clock is sampled when the high level to the second delayed clock zpclk2, produce the first count value zcntal_H, and judgement is when the first delayed clock is in rising edge and the second delayed clock during in trailing edge, whether the value of the first count value zcntal_H is greater than the first counting threshold value ZL and is less than the second counting threshold value ZR, in this way, produce first of high level and know position signal zflag_h; Otherwise, produce low level the first flag signal zflag_h;
Simultaneously, the rising edge that utilizes local clock is sampled when the low level to the second delayed clock zpclk2, produce the second count value zcntal_L, and judgement is when the first delayed clock is in trailing edge and the second delayed clock during in rising edge, whether the value of the second count value is greater than the first counting threshold value ZL and is less than the second counting threshold value ZR, in this way, produce second of high level and know position signal zflag_l; Otherwise, produce low level the second flag signal zflag_l;
(3) the first flag signal zflag_h and the second flag signal zflag_l are carried out to logical "or" computing, generate the 3rd flag signal zflag_m;
(4) judgement is when local clock is during in rising edge, and whether the first count value zcntal_H and the second count value zcntal_L sum zcntal_sum are greater than the second counting threshold value ZR, in this way, produce low level the 4th flag signal zflag_s; Otherwise, the 4th flag signal zflag_s of generation high level;
(5) the 3rd flag signal zflag_m and the 4th flag signal zflag_s are carried out to logic "and" operation, generate the effective flag signal of programmable integrated process load clock zflag, in the time that the effective flag signal of this clock zflag is high level, show that the input clock data of programmable integrated process load are normal; And in the time that the effective flag signal of this clock zflag is low level, show the input clock data exception of programmable integrated process load.
3, the self adaptation of AIS and programmable integrated process two-way load data identification
Carry out logic " also " computing by the effective flag signal aflag to two load and zflag, produce the effective flag signal of dibit flag, in the time that the effective flag signal of this dibit flag is " 10 ", show that AIS load clock data signal is effective; And in the time that the effective flag signal of this dibit flag is " 01 ", show that programmable integrated process load clock data signal is effective, and other logical combination mode of operation, " 00 ", " 11 " are according to real work demand self-defining.
Self adaptation identification for multiselect one load clock data: utilize above-mentioned self adaptation counting clock data detection method respectively the input clock of each road input load to be identified, and the effective flag signal of the clock that produces this road flag_m, wherein m=1,2 ... M, M is input load sum; By the effective flag signal of this M road clock is carried out to logic " also " computing, produce the effective flag signal of M bit flag, wherein, only have a corresponding high level ' 1 ' in the effective flag signal of M bit flag, corresponding high level figure place Na road load clock data is effective.For example, when, the effective flag signal of M bit flag is " 10000 ... 000 ", show that first via load clock data is effective; If when " 00000 ... 001 ", show that M road load clock data is effective.
In the method according to the invention, owing to can the external input clock frequency of single channel being detected in real time, cover the situation as far as possible of clock breaking moment, can independently carry out data identification; The self adaptation switching problem of the two-way load clock data of having realized countless pipe switching commands in system and carry out.By further expanding, method of the present invention is applicable to the time-sharing multiplex of multichannel load data, has solved the self adaptation identification problem of multiselect one load data.It is the situations such as disconnected clock, constant level or clutter that method of the present invention is also applicable to external input clock signal, and antijamming capability is strong.
At this, it should be noted that, the content of not describing in detail in this specification, is that description and the prior art that those skilled in the art pass through in this specification can realize, and therefore, does not repeat.In addition,, although the present invention comes from the development of remote sensing satellite data transmission subsystem data processor product Interface design, its design philosophy and implementation method are applicable to ground data transmission applications completely.
The foregoing is only the preferred embodiments of the present invention, be not used for limiting the scope of the invention.For a person skilled in the art, do not paying under the prerequisite of creative work, can make some amendments and replacement to the present invention, within all such modifications and replacement all should be encompassed in protection scope of the present invention.
Claims (2)
1. a self adaptation counting clock data detection method, is characterized in that, comprises the following steps:
(1) input clock of single channel load is carried out to Fractional-N frequency, produce frequency-dividing clock; And utilize local clock to sample to frequency-dividing clock, and produce two delayed clocks, i.e. the first delayed clock and the second delayed clock, wherein, the value of divider ratio N is determined according to following formula:
and the value of N is got power side's value of 2;
(2) rising edge that utilizes local clock is sampled when high level and the low level respectively to the second delayed clock, produce respectively the first count value and the second count value, judgement is when the first delayed clock is in rising edge, and the second delayed clock is in the time of trailing edge, whether this first count value is greater than the first counting threshold value and is less than the second counting threshold value, produce the first flag signal corresponding to judged result, and definition is in the time that the first count value is greater than the first counting threshold value and is less than the second counting threshold value, this the first flag signal is high level ' 1 ', otherwise be low level ' 0 ', and,
Judgement is when the first delayed clock is in trailing edge and the second delayed clock during in rising edge, whether the second count value is greater than the first counting threshold value and is less than the second counting threshold value, produce the second flag signal corresponding to judged result, and definition second flag signal in the time that the second count value is greater than the first counting threshold value and is less than the second counting threshold value is high level ' 1 ', otherwise is low level ' 0 ';
Wherein, nominal count value
first counting threshold value=nominal count value-n, the situation that is less than 50% corresponding to input clock duty ratio; Second counting threshold value=nominal count value+n, the situation that is greater than 50% corresponding to input clock duty ratio; The value of amount of redundancy n equals 0.05 times of nominal count value, corresponding to the redundancy requirement of input clock duty ratio 5%, and n>=2;
(3) described the first flag signal and the second flag signal are carried out to logical "or" computing, produce the 3rd flag signal;
(4) judgement is when local clock is during in rising edge, the first count value and the second count value and whether be greater than the second counting threshold value, and produce the 4th flag signal according to judged result, and definition when the first count value and the second count value when being greater than the second counting threshold value, the 4th flag signal is high level ' 0 ', otherwise is low level ' 1 ';
(5) described the 3rd flag signal and the 4th flag signal are carried out to logic "and" operation, produce the effective flag signal of clock, if the effective flag signal of this clock is high level ' 1 ', show that this road load input clock is normal, if the effective flag signal of this clock is low level ' 0 ', show that this road load input clock is abnormal;
(6) according to the synchronism of clock and data, and according to the normal or abnormal judged result of step (5) Zhong Duigai road load input clock, realize the autonomous classification of Dui Gai road load data.
2. self adaptation counting clock data detection method according to claim 1, it is characterized in that, in the situation that thering is M road load input clock, first process according to step (1)-(5) Dui Mei road load input clock, obtain the effective flag signal of M clock that Yu Ge road load input clock is corresponding; Then the effective flag signal of this M clock is carried out to logic " also " computing, produce the effective flag signal of M bit, if the m position signal of the effective flag signal of this M bit is high level, show that m road load clock data is effective, wherein, m=1,2,3 ... M, and M is greater than 1 positive integer; Then, carry out the autonomous classification of load data according to step (6).
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108120971A (en) * | 2017-12-12 | 2018-06-05 | 中国特种设备检测研究院 | Desired signal recognition methods, device, ground tracking equipment and system |
| CN109597457A (en) * | 2018-12-03 | 2019-04-09 | 安徽皖兴通信息技术有限公司 | A kind of clock detection method and device based on programmable logic device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002056475A2 (en) * | 2001-01-10 | 2002-07-18 | Adc Telecommunications Israel Ltd. | Phase locked loop |
| CN101018052A (en) * | 2006-02-10 | 2007-08-15 | 凌阳科技股份有限公司 | A clock frequency detection and conversion device |
| CN101582732A (en) * | 2009-06-10 | 2009-11-18 | 中兴通讯股份有限公司 | Clock detection method and device |
| CN101771527A (en) * | 2009-12-16 | 2010-07-07 | 南京弘毅电气自动化有限公司 | Clock extraction device and method for asynchronous communication |
-
2014
- 2014-04-28 CN CN201410174642.3A patent/CN103944786B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002056475A2 (en) * | 2001-01-10 | 2002-07-18 | Adc Telecommunications Israel Ltd. | Phase locked loop |
| CN101018052A (en) * | 2006-02-10 | 2007-08-15 | 凌阳科技股份有限公司 | A clock frequency detection and conversion device |
| CN101582732A (en) * | 2009-06-10 | 2009-11-18 | 中兴通讯股份有限公司 | Clock detection method and device |
| CN101771527A (en) * | 2009-12-16 | 2010-07-07 | 南京弘毅电气自动化有限公司 | Clock extraction device and method for asynchronous communication |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108120971A (en) * | 2017-12-12 | 2018-06-05 | 中国特种设备检测研究院 | Desired signal recognition methods, device, ground tracking equipment and system |
| CN108120971B (en) * | 2017-12-12 | 2021-01-29 | 中国特种设备检测研究院 | Expected signal identification method and device, ground tracking equipment and system |
| CN109597457A (en) * | 2018-12-03 | 2019-04-09 | 安徽皖兴通信息技术有限公司 | A kind of clock detection method and device based on programmable logic device |
| CN109597457B (en) * | 2018-12-03 | 2022-04-19 | 安徽皖兴通信息技术有限公司 | Clock detection method and device based on programmable logic device |
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