CN203324700U

CN203324700U - Universal multi-input timing system

Info

Publication number: CN203324700U
Application number: CN201320354493XU
Authority: CN
Inventors: 王晓; 仇新宏; 张可; 余娟; 尹涛; 王红光
Original assignee: ANHUI JIYUAN POWER SYSTEM TECHNOLOGY Co Ltd
Current assignee: ANHUI JIYUAN POWER SYSTEM TECHNOLOGY Co Ltd
Priority date: 2013-06-20
Filing date: 2013-06-20
Publication date: 2013-12-04
Anticipated expiration: 2023-06-20

Abstract

The utility model discloses an universal multi-input timing system. A core processing module comprises a DSP module and a FPGA module, wherein the DSP module and the FPGA module are in data transmission in an UART manner. The universal multi-input timing system is characterized in that the universal multi-input timing system further comprises a TD3015T dual-mode module which is connected with the FPGA module, and an optical B code module which is connected with the FPGA module, wherein the TD3015T dual-mode module is provided with a dual-mode antenna and a NEMA serial port data filter. The universal multi-input timing system is used to provide a multi-choice and multi-backup clock synchronization scheme based on the Beidou, the GPS and optical B codes for users, so the timing system can be used to provide timing signals having advantages of accuracy, reliability, and stable performance.

Description

A kind of general many inputs time dissemination system

Technical field

Embodiment of the present utility model relates to the Clock Synchronization Technology field of electric device, and more specifically, embodiment of the present utility model relates to a kind of many inputs time dissemination system of the general clock synchronous that relates to the Big Dipper, GPS, light B code.

Background technology

Along with the development of automated control technology, the application of Automation of Electric Systems control technology is also more and more extensive.Due to the singularity of electric system, the action consistency of device requires very high, otherwise just agree to cause huge potential safety hazard.Thus, very strict to the requirement of device in electric system.

Simultaneously, along with the development of satellite communication technology, electric device generally adopts the method time synchronized of satellite time transfer and B code, high-precision to realize, detect accurately and reliably and control.Existing employing GPS or big-dipper satellite or B code provide the electric time synchronizer of time source at present.

But, due to the limitation of technology, still there are a lot of weak points in current time service device or equipment, especially can not guarantee at every moment to provide accurately and reliably, the time signal of stable performance.Thus, for the research of electric system Service of Timing, still among constantly exploring.

Summary of the invention

The utility model has overcome the deficiencies in the prior art, a kind of embodiment of general many inputs time dissemination system is provided, for the user provides the more options based on the Big Dipper, GPS and light B code, the clock synchronous scheme of many backups, to expect that the solution time service device can not provide accurately and reliably, the problems such as time signal of stable performance.

For solving above-mentioned technical matters, a kind of embodiment of the present utility model by the following technical solutions:

A kind of general many inputs time dissemination system, core processing module comprises DSP module and FPGA module, carry out data transmission by the UART mode between described DSP module and FPGA module, the light B code module that core processing module also comprises the TD3015T bimodulus module be connected with the FPGA module and is connected with the FPGA module, described TD3015T bimodulus module arranges dual-mode antenna and NEMA serial data filtrator.

Further technical scheme is: in described FPGA module, fifo module is set, described fifo module is connected with NEMA serial data filtrator.

Further technical scheme is: described FPGA module arranges string translation interface, and described string translation interface are connected on the DSP module.

Further technical scheme is: described smooth B code module is that optical fiber is connected with the connected mode between the FPGA module.

Further technical scheme is: described FPGA inside modules arranges the PPS/10M synchronization module.

Further technical scheme is: described FPGA module is the XC3S50AN of Spartan3AN series.

Further technical scheme is: described DSP module is TMS320F2812.

Compared with prior art, one of the beneficial effects of the utility model are: general many inputs time dissemination system is for the user provides the clock synchronous scheme of more options based on the Big Dipper, GPS and light B code, many backups, makes that time dissemination system can provide accurately and reliably, the time signal of stable performance.

The accompanying drawing explanation

The structural representation that Fig. 1 is the general many inputs time dissemination system of the utility model.

Embodiment

In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.

As shown in Figure 1, the core processing module of general many inputs time dissemination system comprises DSP module 108 and FPGA module 104, carry out data transmission by the UART mode between DSP module 108 and FPGA module 104, the core processing module of many input time dissemination systems also comprises TD3015T bimodulus module 102 and the light B code module 109 be connected with FPGA module 104, and TD3015T bimodulus module 102 arranges dual-mode antenna 101 and NEMA serial data filtrator 103.DSP module 108 is selected the TMS320F2812 of TI company, and FPGA module 104 has been selected the XC3S50AN of the match Spartan3AN of company of SEL series.

Circuit is divided by function can be divided into feed circuit, crystal oscillator is tamed circuit, reset circuit, DSP circuit and FPGA circuit.

Feed circuit: the board of general many inputs time dissemination system adopts single 12V power supply, for guaranteeing the board normal operation, also needs other 4 kinds of voltages, is respectively 5V, 3.3V, 1.8V and 1.2V, for compatible two calibration cell crystal oscillators, also needs to have the 12V power supply in addition.Wherein 3.3V is mainly the I/O of DSP module, I/O and the power supply of other interface chips of FPGA module; 1.8V be the kernel power supply of DSP module, the kernel power supply that 1.2V is the FPGA module.12V is depressured to 5V and adopts non-isolation DC-DC TPS5430 to realize, 3.3V, 2.5V, 1.2V Voltage-output have been selected TPS75003, have selected the power supply of TPS73601 as 1.8V.

Crystal oscillator is tamed the digital to analog converter that circuit: DAC is general many input time dissemination systems, DAC selects DAC8560IDDGKT, it is 16 Voltage-output type DAC chips of SPI serial transmission, and there is the electrification reset function inside, can guarantee zero output before not receiving valid data.The center voltage of crystal oscillator is 2.5V, centre frequency 10MHz, and the inner integrated 2.5V reference voltage of DAC, after the DAC output voltage, through two stage amplifer, the first order is 2 times of amplifications, the second level is for following.

Reset circuit: what board design adopted is the asynchronous reset mode, and the power-on reset signal of the IC that at first resets is received on the FPGA module, by FPAG module reflex bit DSP module, and DSP module other the interface chip that resets again then.That the IC that resets selects is SP706TEN, and SP706TEN is the 3.3V watchdog chip, has electrification reset, hand-reset and watchdog reset function, and detection voltage is 3.08V.

The DSP circuit: the processor adopted on the core processing plate is TMS320F2812, TMS320F2812 adopts Harvard's bus structure, dominant frequency can reach 150MHz, the FLASH of inner integrated 256KB, the external RAM interface can expand to 2MB, if the timing program storage is just with inner FLASH space, ram space adopts IS61LV51216 to expand.

The FPGA circuit: that the FPGA module is selected is the XC3S250E of the match Spartan-3E of company of SEL series, the PQFP208 encapsulation, because the FPGA module does not have very strong fan-out capability, so output signal has added one-level Buffer in the middle of FPGA output later, being in order to increase driving force on the one hand, is that the 3.3V signal is moved to 5V on the other hand, because output board is all single 5V power supply, so, after output signal is moved to 5V, output board can reduce a kind of voltage.Select the driver of the SN74ABT16245 of TI company as output, the drive current of high level can reach 32mA, and the driving force that low spot is flat can reach 64mA.

Fifo module 106 is set in FPGA module 104, and fifo module 106 is connected with the NEMA serial data filtrator 103 of TD3015T bimodulus module 102; FPGA module 104 also is provided with string translation interface 107, and described string translation interface 107 are connected on DSP module 108; The built-in PPS/10M synchronization module 105 of FPGA module 104.DSP module 108 receives by the NMEA serial ports message that TD3015T bimodulus module 102 is sent, and message information comprises GGA locating information and the simplest navigation transmitting data information of RMC.The GGA locating information comprises receiver location, relevant data while surveying.If only the satellites such as BD, GPS, GLONASS, Galileo are used for to location compute, the transmission identifier is BD, GP, GL, GA etc., if used the satellite of a plurality of systems to obtain location compute, transmits identifier GN.DSP module 108 need to solve Hour Minute Second information, positioning states whether effective information and day month year information in the RMS message.

The interface of DSP module 108 mainly comprises FPGA module interface, network interface, active and standby machine communication interface.Wherein the FPGA module interface adopts the EMIF bus interface of DSP module 108, and active and standby machine communication interface is to adopt DSP module 108 UART own to design.

DSP module 108 is designed to guarantee real-time, do not adopt operating system, DSP module 108 is carrying out after initialization completes entering the MainLoop endless loop to peripheral hardware, interrupt the second that receives FPGA module 104 at circulation time, then in interrupting second, regularly completes appointed task.

The data bus of DSP module 108 and FPGA module 104 is used the peripheral hardware XINTF Interface realization of DSP module 108.

PPS/10M synchronization module 105 block diagrams mainly are divided into five parts, are respectively PPS tracking mode module, PPS regeneration phase modulation module, OCXO phase demodulation module, PPS multichannel output module and crystal/rubidium clock 10M and select module.

Between DSP module 108 and TD3015T bimodulus module 102, be to adopt the UART mode to transmit data, FPGA module 104 is processed the IRIG-B signal of light B code module 109 optical fiber inputs, and filter out GGA information and RMS information in the NEMA serial data filtrator 103 of TD3015T bimodulus module 102, and pre-exist in fifo module 106, then in the mode of interrupting, notify DSP module 108 to fetch data, and by string translation interface 107 data transmission in DSP module 108.DSP module 108 need to solve Hour Minute Second information, positioning states whether effective information and day month year information in the RMS message.The PPS/10M synchronization module 106 of FPGA module 104 inside is processed outside multichannel PPS clock source, and DSP module 108 is tamed the 10M crystal as the PPS benchmark by Information Selection one tunnels such as clock source quality; Can, according to the taming before result function of keep time, externally in the situation of PPS clock source with reference to loss, still can export PPS and 10M clock in the situation that externally the PPS clock source is lost.

Although with reference to explanatory embodiment of the present utility model, the utility model is described here, but, should be appreciated that, those skilled in the art can design a lot of other modification and embodiments, and these are revised and within embodiment will drop on the disclosed principle scope and spirit of the application.More particularly, in the scope of, accompanying drawing open in the application and claim, can carry out multiple modification and improvement to building block and/or the layout of subject combination layout.Except modification that building block and/or layout are carried out with improving, to those skilled in the art, other purposes will be also obvious.

Claims

1. general many inputs time dissemination system, core processing module comprises DSP module and FPGA module, carry out data transmission by the UART mode between described DSP module and FPGA module, it is characterized in that: the light B code module that also comprises the TD3015T bimodulus module be connected with the FPGA module and be connected with the FPGA module, described TD3015T bimodulus module arranges dual-mode antenna and NEMA serial data filtrator.

2. a kind of general many inputs time dissemination system according to claim 1, it is characterized in that: in described FPGA module, fifo module is set, described fifo module is connected with NEMA serial data filtrator.

3. a kind of general many inputs time dissemination system according to claim 1 is characterized in that: described FPGA module arranges string translation interface, and described string translation interface are connected on the DSP module.

4. a kind of general many inputs time dissemination system according to claim 1, it is characterized in that: described smooth B code module is that optical fiber is connected with the connected mode between the FPGA module.

5. a kind of general many inputs time dissemination system according to claim 1, it is characterized in that: described FPGA inside modules arranges the PPS/10M synchronization module.

6. a kind of general many inputs time dissemination system according to claim 1, it is characterized in that: described FPGA module is the XC3S50AN of Spartan3AN series.

7. a kind of general many inputs time dissemination system according to claim 1, it is characterized in that: described DSP module is TMS320F2812.