CN103928361A - Method for monitoring deviation of pattern in chip protection area - Google Patents
Method for monitoring deviation of pattern in chip protection area Download PDFInfo
- Publication number
- CN103928361A CN103928361A CN201310012746.XA CN201310012746A CN103928361A CN 103928361 A CN103928361 A CN 103928361A CN 201310012746 A CN201310012746 A CN 201310012746A CN 103928361 A CN103928361 A CN 103928361A
- Authority
- CN
- China
- Prior art keywords
- protection zone
- metal wire
- chip protection
- chip
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a method for monitoring the deviation of a pattern in a chip protection area. An allowable size range is set, the distance of the edge of a photoetching pattern to a metal wire closest to the photoetching pattern in a the chip protection area is measured on photoresistance, and serves as the deviation degree of the pattern on a current layer relative to the pattern on a previous layer in the chip protection area, a next step working procedure is executed if the distance falls into the allowable size range, reworking is carried out if the distance exceeds the allowable size range until the distance falls into the allowable size range, and thus damage caused by pattern deviation to the metal wire in subsequent working procedures can be avoided.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, be specifically related to the method for a kind of chip monitoring protection zone pattern shift.
Background technology
Chip manufacturing flow process can generally be divided into several steps such as wafer-process operation (Wafer Fabrication), wafer probing operation (Wafer Probe), structure dress operation (Packaging), test step (Initial Test and Final Test).Wherein wafer-process operation and wafer probing operation are leading portion (Front End) operation, and structure fills operation, test step is back segment (Back End) operation.
Wafer-process operation is mainly on wafer, to make circuit and electronic component (as transistor, electric capacity, logic switch etc.), its handling procedure is conventionally relevant with the technology using with product category, but general basic step is first wafer suitably to be cleaned, be oxidized and chemical vapour deposition (CVD) on its surface again, then carry out the step repeatedly such as film, exposure, development, etching, implanted ions, metal sputtering, finally on wafer, complete several layers of circuit and element processing and make.
After last process, on wafer, just formed little lattice one by one, i.e. crystal grain, generally, for ease of test, raises the efficiency, and makes the product of same kind, specification in same wafer; But also can make as required the product of several different cultivars, specification.With pin survey (Probe) instrument, each crystal grain is being detected to its electrical characteristic, and after underproof crystal grain is put signs on, wafer is being cut, be divided into many independent crystal grain, by its electrical characteristic classification, pack in different pallets, underproof crystal grain is given up again.
Packaging process is that single crystal grain is fixed on the chip base of plastic cement or pottery system, and the pin that some lead wire ends that etch on crystal grain are stretched out with base bottom is connected, using the use as being connected with external circuitry plate, finally cover plastic cement cover plate, shut with glue.Its objective is to protect crystal grain to avoid being subject to mechanical scratch or high temperature destruction, just made an integrated circuit (IC) chip to this.
Last procedure of chip manufacturing is test, and it can be divided into again general test and special test, and the former is placed in the chip after encapsulation under various environment and tests its electrical characteristic, as consumed power, the speed of service, pressure withstanding degree etc.Chip after tested, is divided into different brackets according to its electrical characteristic.Special test is according to the technical parameter of client's specific demand, from close parameter specification, kind, takes out segment chip, does targetedly test specially, sees the specific demand that whether can meet client, so that whether determine must be as client's design specialized chip.After sticking the label of the marks such as specification, model and the date of production and packed, the qualified product of general test can dispatch from the factory.The parameter situation not reaching depending on it by the chip of test is decided to be degradation product or waste product.
The etching (Fuse ETCH) of chip protection zone is the procedure in chip manufacturing flow process, after being positioned at the metal formation of back segment metal interconnection, before the test before chip cutting.This procedure is to etch a circle groove in the periphery of chip area, forms a protection zone, the moat effect of performance groove, the damage of the stress producing in scribe line while preventing chip cutting to chip area.
Pattern shift (overlay, be called for short OVL, when layer photoetching pattern is with respect to the degrees of offset of front layer pattern) generation, be that first photoetching process will aim at owing to will using 20 multiple tracks photo-mask processs in whole chip manufacturing flow process, do an aligning by working as layer pattern and front layer pattern, after photoetching process completes, measure the actual numerical value of this aligning at measurement board, namely so-called drift, drift is 0 the best, means when layer pattern and front layer pattern perfect alignment.Drift about more bad more greatly, exceed certain numerical value, will be risky, need photoetching to do over again, remove photoresist, then photoetching again.
In scribe line, be designed with various test modules (Test Key), be used for carrying out wafer and permit Acceptance Tests (Wafer Acceptance Test is called for short WAT), these test modules all connect out by metal wire (Metal Line).The metal wire of relatively more close chip area; be easy to be damaged by the etching of chip protection zone; particularly in the time that the image shift of chip protection zone photoetching is more; chip protection zone can be less to the distance of metal wire; the possibility of damaging metal wire will be higher; and the damage of metal wire can cause WAT test abnormal.The photoetching of chip protection zone is never monitored pattern shift; for on-line monitoring part; industry is only measured the critical size (Critical Dimension is called for short CD) of the photoetching of chip protection zone and etching at present, does not have the method for measurement of effective pattern shift.
Therefore,, for above-mentioned technical problem, be necessary to provide the method for a kind of effective chip monitoring protection zone pattern shift, to overcome above-mentioned defect.
Summary of the invention
In view of this, the object of the present invention is to provide the method for a kind of chip monitoring protection zone pattern shift, realize effective on-line monitoring.
For achieving the above object, the invention provides following technical scheme:
The method of chip monitoring of the present invention protection zone pattern shift, comprises the steps:
1, when photoetching chip protection zone, on photoresistance, form after the photoengraving pattern of chip protection zone, measurement object using chip protection zone photoengraving pattern left side to the distance X apart from its nearest metal wire as pattern shift, measure by scanning electron microscopy, if meet A≤X≤B, enter next step operation;
Wherein, the minimum range that A allows to nearest metal wire for left side, chip protection zone, the ultimate range that B allows to nearest metal wire for left side, chip protection zone, B=X
1+ Y-C, X
1for left side, chip protection zone is to the designed distance of nearest metal wire, Y is the designed distance of right side, chip protection zone to nearest metal wire, the minimum range that C allows to nearest metal wire for right side, chip protection zone;
If 2 X<A or X>B, need to do over again, remove photoresistance, revise after etching condition, photoetching makes its A≤X≤B again.
X<A, left side, chip protection zone has the danger that contacts and damage its nearest metal wire;
X>B, right side, chip protection zone has the danger that contacts and damage its nearest metal wire.
Preferably, described A value scope is 0.7 μ m ~ 1 μ m.
Preferably, described C value scope is 0.7 μ m ~ 1 μ m.
The method of chip monitoring of the present invention protection zone pattern shift arrives the distance from its nearest metal wire by photoengraving pattern edge, measuring chip protection zone; as judging the degrees of offset of chip protection zone when the relatively front layer pattern of layer pattern, thus the damage to metal wire that can avoid subsequent handling to cause because of pattern shift.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing relevant of the present invention in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the locations of structures schematic diagram of conventional Yu Qi both sides, one single chip protection zone metal wire;
Fig. 2 is the locations of structures schematic diagram of Yu Qi both sides, the multiple chips protection zone metal wire of routine;
Fig. 3 is the locations of structures signal partial enlarged drawing of border circular areas 4 chip protection zones and its left side metal wire in Fig. 2.
Embodiment
The method that the invention discloses a kind of chip monitoring protection zone pattern shift, comprises the following steps:
1, when photoetching chip protection zone, on photoresistance, form after the photoengraving pattern of chip protection zone, measurement object using chip protection zone photoengraving pattern left side to the distance X apart from its nearest metal wire as pattern shift, measure by scanning electron microscopy, if meet A≤X≤B, enter next step operation;
Wherein, the minimum range that A allows to nearest metal wire for left side, chip protection zone, the ultimate range that B allows to nearest metal wire for left side, chip protection zone, B=X
1+ Y-C, X
1for left side, chip protection zone is to the designed distance of nearest metal wire, Y is the designed distance of right side, chip protection zone to nearest metal wire, the minimum range that C allows to nearest metal wire for right side, chip protection zone;
If 2 X<A or X>B, need to do over again, remove photoresistance, revise after etching condition, photoetching makes its A≤X≤B again.
Preferably, described A value scope is 0.7 μ m ~ 1 μ m.
Preferably, described C value scope is 0.7 μ m ~ 1 μ m.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is described in detail, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite of not making creative work, belongs to the scope of protection of the invention.
As shown in Figure 1, etch the groove of a circle rectangle in the periphery of chip area, form the chip protection zone 1 of a sealing, the moat effect of performance groove, the damage of the stress producing in scribe line while preventing chip cutting to chip area.There are respectively metal wire 2 and the metal wire 3 of parallel distribution with it in the left and right sides of groove, and with chip protection zone 1 at a distance of certain distance, left side is the metal wire 2 nearest apart from chip protection zone, right side is the metal wire 3 nearest apart from chip protection zone.
As shown in Figure 2, form by multiple independently chip areas are regularly arranged, each chip protection zone and the adjacent interlaced with each other distribution that is arranged in parallel of metal wire, with to be tested and cutting.
Fig. 3 is the partial enlarged drawing of the chip protection zone of border circular areas 4 in Fig. 2 metal wire adjacent with left side, first carry out the definition of some numerical value, by chip protection zone photoengraving pattern left side to being made as numerical value X apart from the distance of its nearest metal wire, as the measurement object of pattern shift; The minimum range that numerical value A allows to nearest metal wire for left side, chip protection zone, this distance rule of thumb obtains, and the scope of numerical value A is 0.7 μ m ~ 1 μ m conventionally; The ultimate range that numerical value B allows to nearest metal wire for left side, chip protection zone, can be calculated and be obtained by following formula, B=X
1+ Y-C, X
1for left side, chip protection zone is to the designed distance of nearest metal wire; Y is the designed distance of right side, chip protection zone to nearest metal wire; the minimum range that C allows to nearest metal wire for right side, chip protection zone; this distance also rule of thumb obtains; the scope of logical constant value C is 0.7 μ m ~ 1 μ m, and numerical value B is determined jointly by designed distance and the numerical value C of product self.
Measure numerical value X by scanning electron microscopy, draw corresponding numerical value X by the instant image operation of arresting, if meet A≤X≤B, it is qualified to be judged to be.When meeting this condition, the etching of back to back chip protection zone, metal wire can not be damaged, and ensuing WAT test step just can not occur abnormal yet, and whole operation also can go on very smoothly;
If X<A or X>B, be judged to be defective.In the time of X<A, left side, chip protection zone has the danger that contacts and damage its nearest metal wire; In the time of X>B; right side, chip protection zone has the danger that contacts and damage its nearest metal wire; under both of these case; ensuing WAT test step all can occur extremely; now need to do over again, remove photoresistance, revise after etching condition; again photoetching, measures numerical value X until meet A≤X≤B by scanning electron microscopy.
Whole scanning electron microscopy measures numerical value X and carries out decision process and moves in circles, if meet qualified next step operation that enters of A≤X≤B, if X<A or X>B are defective, do over again until measure and meet A≤X≤B, if the sample of doing over again has not possessed re-workability, be decided to be waste product.
The method of chip monitoring of the present invention protection zone pattern shift; the equal on-fixed value of the numerical value A setting and numerical value B; need to jointly determine according to the experience of the designed distance of product and processing; the method of this on-line monitoring; need in good time renewal input numerical value A and numerical value B, adjusted selection by those skilled in the art according to actual conditions.
In sum; the method of chip monitoring of the present invention protection zone pattern shift arrives the distance from its nearest metal wire by photoengraving pattern edge, measuring chip protection zone; as judging the degrees of offset of chip protection zone when the relatively front layer pattern of layer pattern, thus the damage to metal wire that can avoid subsequent handling to cause because of pattern shift.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned example embodiment, and in the situation that not deviating from spirit of the present invention or essential characteristic, can realize the present invention with other concrete form.Therefore, no matter from which point, all should regard embodiment as exemplary, and be nonrestrictive, scope of the present invention is limited by claims instead of above-mentioned explanation, is therefore intended to all changes that drop in the implication and the scope that are equal to important document of claim to include in the present invention.Any Reference numeral in claim should be considered as limiting related claim.
In addition, be to be understood that, although this specification is described according to execution mode, but be not that each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should make specification as a whole, and the technical scheme in each embodiment also can, through appropriately combined, form other execution modes that it will be appreciated by those skilled in the art that.
Claims (3)
1. a method for chip monitoring protection zone pattern shift, is characterized in that, comprises the steps:
When a, photoetching chip protection zone, on photoresistance, form after the photoengraving pattern of chip protection zone, measurement object using chip protection zone photoengraving pattern left side to the distance X apart from its nearest metal wire as pattern shift, measure by scanning electron microscopy, if meet A≤X≤B, enter next step operation;
Wherein, the minimum range that A allows to nearest metal wire for left side, chip protection zone, the ultimate range that B allows to nearest metal wire for left side, chip protection zone, B=X
1+ Y-C, X
1for left side, chip protection zone is to the designed distance of nearest metal wire, Y is the designed distance of right side, chip protection zone to nearest metal wire, the minimum range that C allows to nearest metal wire for right side, chip protection zone;
If b X<A or X>B, need to do over again, remove photoresistance, revise after etching condition, photoetching makes its A≤X≤B again.
2. method according to claim 1, is characterized in that: described A scope is 0.7 μ m ~ 1 μ m.
3. method according to claim 1, is characterized in that: described C scope is 0.7 μ m ~ 1 μ m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310012746.XA CN103928361B (en) | 2013-01-14 | 2013-01-14 | A kind of method monitoring chip protection zone pattern shift |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310012746.XA CN103928361B (en) | 2013-01-14 | 2013-01-14 | A kind of method monitoring chip protection zone pattern shift |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103928361A true CN103928361A (en) | 2014-07-16 |
| CN103928361B CN103928361B (en) | 2016-12-28 |
Family
ID=51146540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310012746.XA Active CN103928361B (en) | 2013-01-14 | 2013-01-14 | A kind of method monitoring chip protection zone pattern shift |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103928361B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61131540A (en) * | 1984-11-30 | 1986-06-19 | Nec Corp | Semiconductor device |
| KR20050066829A (en) * | 2003-12-27 | 2005-06-30 | 동부아남반도체 주식회사 | Wafer edge area test module |
| CN102109771A (en) * | 2011-01-27 | 2011-06-29 | 上海宏力半导体制造有限公司 | Method for detecting semiconductor device |
| CN102566315A (en) * | 2012-01-18 | 2012-07-11 | 上海华力微电子有限公司 | Method for detecting offset of focus of lithography machine |
-
2013
- 2013-01-14 CN CN201310012746.XA patent/CN103928361B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61131540A (en) * | 1984-11-30 | 1986-06-19 | Nec Corp | Semiconductor device |
| KR20050066829A (en) * | 2003-12-27 | 2005-06-30 | 동부아남반도체 주식회사 | Wafer edge area test module |
| CN102109771A (en) * | 2011-01-27 | 2011-06-29 | 上海宏力半导体制造有限公司 | Method for detecting semiconductor device |
| CN102566315A (en) * | 2012-01-18 | 2012-07-11 | 上海华力微电子有限公司 | Method for detecting offset of focus of lithography machine |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103928361B (en) | 2016-12-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103163442B (en) | Wafer test method | |
| KR100860135B1 (en) | Method and apparatus for controlling photolithography overlay registration incorporating feedforward overlay information | |
| KR100267463B1 (en) | Method of measurement of yield loss chips and poor chips classified by a type according to defected chips on the wafer | |
| US7492049B2 (en) | Multi-layer registration and dimensional test mark for scatterometrical measurement | |
| KR20070070903A (en) | Semiconductor wafer analysis system | |
| JP2008166691A (en) | Teg pattern, testing method of semiconductor element using the pattern | |
| CN107561875B (en) | Overlay error measurement and problem assessment method | |
| CN105740540A (en) | Method for searching characteristic graphs of layouts in mask design | |
| CN107045259B (en) | Mask plate containing monitoring pattern and monitoring method | |
| CN100533163C (en) | Crystal wafer for testing aging and electricity performances and construction thereof | |
| CN103928361A (en) | Method for monitoring deviation of pattern in chip protection area | |
| CN102522360B (en) | Lithography alignment precision detection method | |
| CN104134619A (en) | Method for detecting alignment degree between polycrystalline silicon and connecting hole through insufficient etching defect | |
| CN103913943A (en) | Photomask detection method | |
| US20070072315A1 (en) | Method and system for reliability similarity of semiconductor devices | |
| US10102615B2 (en) | Method and system for detecting hotspots in semiconductor wafer | |
| CN103531499B (en) | The method of matching degree between monitoring e-beam scanners | |
| CN104882393A (en) | Off-line monitoring method of photoetching antireflection layer | |
| TWI514492B (en) | Method of varifying map shift in electrical testing of wafer | |
| CN104201131A (en) | Method for evaluating defect of deficiency of polycrystalline silicon gate | |
| CN1983559A (en) | Method of patterning substrate | |
| US6778876B1 (en) | Methods of processing substrates based upon substrate orientation | |
| CN113496908B (en) | Semiconductor device detection method, semiconductor device and electronic equipment | |
| US11037842B2 (en) | Semiconductor device with inspection patterns | |
| JPH11126736A (en) | Apparatus and system for managing manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |