CN103915315B - Mim capacitor and forming method thereof - Google Patents
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Abstract
A kind of MIM capacitor and forming method thereof, the forming method of described MIM capacitor includes: providing substrate, described part of substrate is positioned at first area, and part of substrate is positioned at second area；Substrate surface in described first area forms the first electrode layer；Insulating barrier is formed in described first electrode layer surface and substrate surface；The second electrode lay is formed at described surface of insulating layer；The 3rd dielectric layer is formed on the second electrode lay surface and surface of insulating layer；Concurrently form the first through hole and the second through hole, wherein, described first through hole sequentially passes through the first electrode layer of the 3rd dielectric layer, insulating barrier and first area, described second through hole sequentially passes through the insulating barrier of the 3rd dielectric layer, the second electrode lay and second area, and the 3rd thickness of dielectric layers that the 3rd thickness of dielectric layers that runs through of the first through hole and the second through hole run through is identical.The forming method of described MIM capacitor can reduce the difficulty forming the connector being connected with MIM capacitor upper/lower electrode.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to a kind of MIM capacitor and forming method thereof.
Background technology
Capacity cell is usually used in the integrated circuits such as RFCO2 laser, monolithic microwave IC as electronic passive device.Common capacity cell includes metal-oxide semiconductor (MOS) (MOS) electric capacity, capacitance of PN junction and MIM(metal-insulator-metal, is called for short MIM) electric capacity etc..Wherein, MIM capacitor provides the electrology characteristic being relatively better than mos capacitance and capacitance of PN junction in some special applications, and this is that operationally electrode easily produces cavitation layer owing to mos capacitance and capacitance of PN junction are both limited by itself structure, causes that its frequency characteristic reduces.And MIM capacitor can provide good frequency and temperature correlated characteristic.
Refer to Fig. 1, for the cross-sectional view of the MIM capacitor of prior art.
Described structure includes: dielectric layer 10, it is positioned at the lower metal layer 11 on dielectric layer 10 surface, it is positioned at lower metal layer 11 and the interlayer dielectric layer 20 on dielectric layer 10 surface, it is formed at the MIM capacitor 27 in interlayer dielectric layer 20, described MIM capacitor includes capacitor lower electrode 24, upper electrode 26 and capacitance dielectric layer 25, is positioned at the upper metal layers 31 on interlayer dielectric layer 20 surface.The upper electrode 26 of described MIM capacitor is connected with upper strata metal 31 by connector 22, and the bottom electrode 24 of MIM capacitor is connected with lower metal layer 11 by connector 21.And described interlayer dielectric layer 20 also has connector 23, connect upper metal layers 31 and lower metal layer 11.
As can be seen from Figure 1, the degree of depth and the position of described connector 22, connector 21 and connector 23 are different from, if etch the through hole of described connector 22 and connector 23 simultaneously, owing to etching depth difference is bigger, the through hole easily making formation connector 22 penetrates electrode 26, directly it is connected with capacitance dielectric layer 25 or bottom electrode 24, so that MIM capacitor lost efficacy.If separately etching described through hole, then need to increase processing step, improve process costs.
More forming methods about MIM capacitor, refer to the U.S. patent documents that publication number is US2008/0290459A1.
Summary of the invention
The problem that this invention address that is to provide a kind of MIM capacitor and forming method thereof, reduces the process costs forming MIM capacitor, reduces the etching difficulty of the through hole being connected with MIM capacitor upper/lower electrode.
For solving the problems referred to above, technical scheme proposes the forming method of a kind of MIM capacitor, and described method includes: providing substrate, adjacent first area and second area, described part of substrate is positioned at first area, and part of substrate is positioned at second area；The first electrode layer is formed on the surface of the substrate of described first area；Insulating barrier is formed in described first electrode layer surface and substrate surface；The second electrode lay is formed at described surface of insulating layer, described the second electrode lay includes Part I and the Part II being connected with Part I, described Part I is positioned at the surface of insulating layer of second area and exposes the insulating barrier of described first electrode layer surface of part, described Part II is positioned at the surface of insulating layer of second area, and the thickness of described the second electrode lay is identical with the thickness of material and the first electrode layer and material；Form the 3rd dielectric layer on the second electrode lay surface and surface of insulating layer and planarize described 3rd dielectric layer；Concurrently form the first through hole and the second through hole, wherein, described first through hole sequentially passes through the first electrode layer of the 3rd dielectric layer, insulating barrier and first area, described second through hole sequentially passes through the insulating barrier of the 3rd dielectric layer, the second electrode lay and second area, and the 3rd thickness of dielectric layers that the 3rd thickness of dielectric layers that runs through of the first through hole and the second through hole run through is identical.
Optionally, also including the 3rd region, described part of substrate is positioned at the 3rd region, and the substrate surface in first area and the 3rd region concurrently forms the first electrode layer.
Optionally, also include: concurrently forming the first through hole, the second through hole and third through-hole, described third through-hole sequentially passes through first electrode layer in the 3rd dielectric layer, insulating barrier and the 3rd region.
Optionally, described substrate includes: first medium layer and be positioned at the first metal layer of first medium layer of first area and be positioned at second metal level of first medium layer in the 3rd region, the surface of described the first metal layer and the surface of the second metal level flush with the surface of first medium layer, and are positioned at the second dielectric layer of described first medium layer surface, the first metal layer surface and the second layer on surface of metal；Described first through hole, the second through hole and third through-hole also extend through described second dielectric layer.
Optionally, the thickness of described first electrode layer is 10 nanometers ~ 40 nanometers, and the thickness of the second electrode lay is 10 nanometers ~ 40 nanometers.
Optionally, the material of described first electrode layer is TiN, Ti, TaN, Ta, WN, W or TiW, and the material of the second electrode lay is TiN, Ti, TaN, Ta, WN, W or TiW.
Optionally, the material of described insulating barrier is high K medium material.
Optionally, the thickness of described insulating barrier is 1 nanometer ~ 5 nanometers.
Optionally, also including, fill described first through hole, the second through hole and third through-hole, form the first connector, the second connector and the 3rd connector, the material filling described first connector, the second connector and the 3rd connector is Cu, W or Al.
Optionally, also include, form the 3rd metal level being connected with the second connector and the 3rd connector at the 3rd dielectric layer surface.
For solving the problems referred to above, technical scheme also proposed a kind of MIM capacitor, including: substrate, adjacent first area and second area, described part of substrate is positioned at first area, and part of substrate is positioned at second area；It is positioned at the first electrode layer of the substrate surface of first area；It is positioned at the insulating barrier of the first electrode layer and substrate surface；It is positioned at the second electrode lay of surface of insulating layer, described the second electrode lay includes Part I and the Part II being connected with Part I, described Part I is positioned at the surface of insulating layer of second area and exposes the insulating barrier of described first electrode layer surface of part, described Part II is positioned at the surface of insulating layer of second area, and the thickness of described the second electrode lay is identical with the thickness of material and the first electrode layer and material；Being positioned at the 3rd dielectric layer of the second electrode lay surface and surface of insulating layer, described 3rd dielectric layer surface is smooth；First connector, described first connector runs through the first electrode layer of the 3rd dielectric layer, insulating barrier and first area；Second connector, described second connector runs through the insulating barrier of the 3rd dielectric layer, the second electrode lay and second area.
Optionally, the first electrode layer of the substrate surface in the 3rd region and described 3rd region is also included.
Optionally, also including: the 3rd connector, described 3rd connector runs through first electrode layer in the 3rd dielectric layer, insulating barrier and the 3rd region.
Optionally, described substrate includes: first medium layer and be positioned at the first metal layer of first medium layer of first area and be positioned at second metal level of first medium layer in the 3rd region, and the surface of described the first metal layer and the second metal level flushes with the surface of first medium layer；It is positioned at the second dielectric layer of described first medium layer, the first metal layer and the second layer on surface of metal；Described first connector, the second connector and the 3rd connector also extend through described second dielectric layer.
Optionally, the thickness of described first electrode layer is 10 nanometers ~ 40 nanometers, and the thickness of the second electrode lay is 10 nanometers ~ 40 nanometers.
Optionally, the material of described first electrode layer is TiN, Ti, TaN, Ta, WN, W or TiW, and the material of the second electrode lay is TiN, Ti, TaN, Ta, WN, W or TiW.
Optionally, the material of described insulating barrier is high K medium material.
Optionally, the thickness of described insulating barrier is 1 nanometer ~ 5 nanometers.
Optionally, also include: be positioned at the 3rd metal level being connected with the second connector and the 3rd connector of the 3rd dielectric layer surface.
Optionally, the material of described first connector, the second connector and the 3rd connector is Cu, W or Al.
Compared with prior art, the invention have the advantages that
Technical scheme, form the insulating barrier covering substrate and the first electrode layer, form the second electrode lay again, described the second electrode lay includes Part I and the Part II being connected with Part I, described Part I is positioned at the surface of insulating layer of second area and exposes the insulating barrier of described first electrode layer surface of part, described Part II is positioned at the surface of insulating layer of second area, and the thickness of described the second electrode lay is identical with the thickness of material and the first electrode layer and material.By choosing the position forming the first through hole, the second through hole and third through-hole, the first through hole making formation sequentially passes through the first electrode layer of the 3rd dielectric layer, insulating barrier and first area, and the second through hole sequentially passes through the insulating barrier of the 3rd dielectric layer, the second electrode lay and second area.Owing to the degree of depth of the first through hole and the second through hole is consistent, and the first electrode layer is all identical with the thickness of the second electrode lay and material, and the 3rd thickness of dielectric layers that the 3rd thickness of dielectric layers that runs through of the first through hole and the second through hole run through is identical.Need the degree of depth of etching and the material that need to etch and the number of plies all identical so forming described first through hole and the second through hole, and insulating barrier and the first electrode layer and the second electrode lay are compared, thickness is only small, the impact of etching is little, so, it is possible to adopt identical etching technics to form described first through hole and the second through hole simultaneously.
Further, described part of substrate is also located at the 3rd region, substrate surface in the 3rd region also forms the first electrode layer, it is sequentially etched first electrode layer in the 3rd dielectric layer, insulating barrier and the 3rd region, form the etching technics of third through-hole also with to form the first through hole, the second through hole identical, it is possible to concurrently form the first through hole, the second through hole and third through-hole.After filling described third through-hole formation the 3rd connector, described 3rd connector can as the device above the 3rd dielectric layer and the interconnection structure of device in substrate.
Further, first electrode layer of first area, insulating barrier and the second electrode lay are respectively as the bottom electrode of MIM capacitor, capacitance dielectric layer and upper electrode, fill described first through hole, described first connector that second through hole is formed, second connector not with the bottom electrode of electric capacity or upper electrode is vertical is connected, but connect in the side of the first connector and the second connector, thus avoiding in prior art, formed in the surface of capacitance electrode etching and the upper electrode of MIM capacitor causes over etching by the process of through hole and penetrate the upper electrode of MIM capacitor and be directly connected with capacitance dielectric layer, avoid affecting the performance of MIM capacitor.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of MIM capacitor in prior art；
Fig. 2 to Figure 11 is the generalized section of the forming process of MIM capacitor in embodiments of the invention.
Detailed description of the invention
As described in the background art, in prior art, being formed in the method for MIM capacitor, the connector etching depth being connected with electric capacity upper/lower electrode is inconsistent, is easily caused the over etching of electrode on electric capacity in the process forming connector through hole.
The forming method of transistor that the present invention proposes, electrode and bottom electrode on the connection electric capacity formed, the degree of depth of connector all identical with etching condition, it is possible to concurrently form, save processing step, and do not have over etching phenomenon.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Described embodiment is only a part for the embodiment of the present invention, rather than they are whole.When describing the embodiment of the present invention in detail, for purposes of illustration only, schematic diagram can disobey general ratio makes partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.Additionally, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.According to described embodiment, those of ordinary skill in the art is obtainable other embodiments all under the premise without creative work, broadly fall into protection scope of the present invention.Therefore the present invention is not by the restriction of following public specific embodiment.
Refer to Fig. 2, it is provided that substrate, adjacent first area I, second area II and the three region III, described part of substrate is positioned at first area I, and part of substrate is positioned at second area II, and part of substrate is positioned at the 3rd region III.
In the present embodiment, described substrate includes substrate (not shown) and is positioned at the first medium layer 100 of substrate surface, described first medium layer 100 as the interlayer dielectric layer of semiconductor device, at the bottom of isolation liner with follow-up on the substrate square become device cell.The metal interconnection structures such as connector can also be formed with in described first medium layer 100.The material of described first medium layer 100 is silicon oxide, silicon nitride, low-K dielectric material or super low-K dielectric material.
Described substrate also includes the first metal layer 101 being positioned at the first medium layer 100 of first area I, is positioned at the second metal level 102 of the first medium layer 100 of the 3rd region III；Wherein the first metal layer 101 surface, the second metal level 102 surface flush with first medium layer 100 surface.
Described the first metal layer 101 or the second metal level 102, as metal interconnecting layer, by metal interconnection structure (not shown) such as the connectors of formation in first medium layer 100, are connected by described the first metal layer 101 and the second metal level 102 with the device in substrate.The material of described the first metal layer 101 and the second metal level 102 is Cu, W or Al.
The formation process of described the first metal layer 101 and the second metal level 102 is: form Patterned masking layer on described first medium layer 100 surface, described Patterned masking layer exposes the position needing to form the first metal layer 101 and the second metal level 102, using described Patterned masking layer as mask, etch described first medium layer 100, groove (mark) is formed on described first medium layer 100 surface, metal material is deposited in described groove, described metal material is filled full groove and covers first medium layer surface, described metal material is planarized, form the first metal layer 101 and the second metal level 102.
Described substrate also includes the second dielectric layer 103 covering described the first metal layer the 101, second metal level 102 and first medium layer 100 surface, and the material of described second dielectric layer 103 is silicon oxide or silicon nitride.The formation process of described second dielectric layer 103 can be chemical vapour deposition (CVD).
Refer to Fig. 3, form the first electrode material layer 200 on the surface of described second dielectric layer 103；
The material of described first electrode material layer 200 includes TiN, Ti, TaN, Ta, WN, W or TiW, and the technique forming described first electrode material layer 200 is physical vapour deposition (PVD), chemical vapour deposition (CVD) or sputtering.The thickness of described first electrode material layer 200 is 10 nanometers ~ 40 nanometers.
Refer to Fig. 4, graphically described first electrode material layer 200(refer to Fig. 3), form the first electrode layer 202 on second dielectric layer 103 surface of first area I, form the first electrode layer 202 ' on second dielectric layer 103 surface of the 3rd region III.
Concrete, described first electrode layer (202, 202 ') forming method is: refer to Fig. 3 at described first electrode material layer 200() surface is formed has the mask layer (not shown) of opening, opening along described mask layer, using plasma etching technics etches described first electrode material layer, form the first opening 203, it is positioned at the first electrode layer 202 of the substrate surface of first area I and first electrode layer 202 ' on second dielectric layer 103 surface of the 3rd region III, wherein, second opening 203 exposes the surface of the described second dielectric layer 103 of second area II, then described mask layer is removed.
Refer to Fig. 5, form the insulating barrier 300 covering described first electrode layer (202,202 ') and described second dielectric layer 103.
Concrete, the material of described insulating barrier 300 is high K dielectric material, including: HfO2、TiO2、 HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3, one or more in BaSrTiO, the thickness of described insulating barrier 300 is uniform, is 1 nanometer ~ 5 nanometers, and the position connected on second dielectric layer 103 surface of second area II and the first electrode layer 202 surface is stepped.The follow-up capacitance dielectric layer as MIM capacitor of described insulating barrier 300.
The formation process forming described insulating barrier 300 is chemical vapour deposition (CVD), ald or sputtering.Compared with general insulant, described insulating barrier 300 adopts the capacitance density that high K dielectric material can improve MIM capacitor.
In other embodiments of the invention, before forming described insulating barrier 300, one layer of passivation layer can also be initially formed in described first electrode layer 202 surface, the surface of second dielectric layer 103 and the sidewall surfaces of the first opening 203, then form insulating barrier 300 in described passivation layer surface.The material of described passivation layer includes Al2O3, SiN or SiO2Deng material, described passivation layer is possible to prevent the ion in insulating barrier 300 to spread in the first electrode layer 202 and cause capacity fall off, reduces the performance of electric capacity.The thickness of described passivation layer is 10 angstroms ~ 1 nanometer.
Refer to Fig. 6, form the second electrode material layer 400 on described insulating barrier 300 surface.
The material of described second electrode material layer 400 includes one or more in TiN, Ti, TaN, Ta, WN, W or TiW, and the formation process of described second electrode material layer 400 is physical vapour deposition (PVD), chemical vapour deposition (CVD) or sputtering.The thickness of described second electrode material layer 400 is 10 nanometers ~ 40 nanometers.And the material of described second electrode material layer 400 is identical with the material of the first electrode layer 202 and thickness respectively with thickness, make the material of the second electrode lay being subsequently formed identical with the material of thickness and the first electrode layer and thickness.
In other embodiments of the invention, before forming described second electrode material layer 400, it is also possible to first form one layer of passivation layer on described insulating barrier 300 surface, then form the second electrode material layer 400 in described passivation layer surface.The material of described passivation layer includes Al2O3, SiN or SiO2Deng material, described passivation layer is possible to prevent the ion in insulating barrier to spread in the second electrode lay and cause capacity fall off, reduces the performance of electric capacity.The thickness of described passivation layer is 10 angstroms ~ 1 nanometer.
Refer to Fig. 7, graphically described second electrode material layer 400(refer to Fig. 6), form the second electrode lay 401, wherein, the described the second electrode lay 401 of part is positioned at first area I, the described the second electrode lay 401 of part is positioned at second area II, be positioned at the second electrode lay 401 of first area I expose described in be positioned at the partial insulative layer 300 of first area I
Concrete, the method forming described the second electrode lay 401 is: refer to Fig. 6 at described second electrode material layer 400() surface is formed has the mask layer of opening, residue the second electrode material layer 400(that the opening of described mask layer exposes outside the second electrode lay 401 position refer to Fig. 6), opening along described mask layer, using plasma etching technics etches described second electrode material layer 400(and refer to Fig. 6), form the second electrode lay 401, then remove described mask layer.
It should be noted that the described the second electrode lay 401 of part being positioned at first area I partly overlaps in vertical direction with the first electrode layer 202 of the substrate surface being positioned at first area I, insulating barrier 300.First electrode layer 202 of described lap as the bottom electrode of MIM capacitor, insulating barrier 300 as the capacitance dielectric layer of MIM capacitor, the second electrode lay 401 as the upper electrode of MIM capacitor.
Refer to Fig. 8, form the 3rd dielectric layer 500 of planarization at insulating barrier 300 and the second electrode lay 401 surface.
The material of described 3rd dielectric layer 500 is silicon oxide or silicon nitride.The formation process of described 3rd dielectric layer 500 can be chemical vapour deposition (CVD).The concrete method forming described 3rd dielectric layer 500 is: adopt chemical vapor deposition method, after described insulating barrier 300 and the second electrode lay 401 surface formation of deposits the 3rd layer of dielectric material, adopt chemical mechanical milling tech to planarize described 3rd layer of dielectric material, form the 3rd dielectric layer 500 of planarization.
Refer to Fig. 9, formed on described 3rd dielectric layer 500 surface and there is the mask layer 600 of opening, along described mask layer 600 Open Side Down etching, form the first through hole the 701, second through hole 702 and third through-hole 703 at substrate surface.
Concrete, the position of described first through hole 701 is chosen for and can sequentially pass through described 3rd dielectric layer 500, insulating barrier the 300, first electrode layer 202 and second dielectric layer 103, and described first through hole 701 exposes the part surface of the first metal layer 101；The position of described second through hole 702 is chosen for and can sequentially pass through the 3rd dielectric layer 500, the second electrode lay 401, insulating barrier 300 and second dielectric layer 103, and described second through hole 702 exposes the part surface of first medium layer 100 of second area II；The position of described third through-hole 703 is chosen for and can sequentially pass through the 3rd dielectric layer 500, insulating barrier the 300, first electrode layer 202 ' and second dielectric layer 103, and described third through-hole 703 exposes the part surface of the second metal level 102.
Form described first through hole 701, the technique of the second through hole 702 and third through-hole 703 is plasma etching, the bottom of described first through hole 701 is positioned at the first metal layer 101 surface, with the first electrode layer 202 that the first through hole 701 sidewall is connected and the insulating barrier 300 above it, the second electrode lay 401 forms MIM capacitor, described the first electrode layer 202 being connected with the first through hole 701 sidewall is as the bottom electrode of MIM capacitor, the insulating barrier 300 being connected with the first through hole 701 sidewall is as the capacitance dielectric layer of MIM capacitor, the second electrode lay 401 being connected with the first through hole 701 sidewall is as the upper electrode of MIM capacitor.
Owing to the surface of described first medium layer 100 flushes with the surface of the first metal layer the 101, second metal level 102, so, described first through hole the 701, second through hole 702 is identical with the etching depth of third through-hole 703, it is possible to etching forms described first through hole the 701, second through hole 702 and third through-hole 703 simultaneously.And, embodiments of the invention are by arranging each modular construction of device and choosing the position of first through hole the 701, second through hole 702 and third through-hole 703, make etch described first through hole 701 time from top to bottom, be sequentially etched the second dielectric layer 103 of the 3rd dielectric layer 500, insulating barrier the 300, first electrode layer 202 and first area I；When etching described second through hole 702, then it is sequentially etched the second dielectric layer 103 of the 3rd dielectric layer 500, the second electrode lay 401, insulating barrier 300 and second area II；When etching third through-hole 703, it is sequentially etched the second dielectric layer 103 of the 3rd dielectric layer 500, insulating barrier the 300, first electrode layer 202 ' and the 3rd region III.Owing to the first electrode layer (202,202 ') is all identical with thickness with the material of the second electrode lay 401, and insulating barrier 300 thickness is less, the impact of etching is less, so it is all consistent with material with the thickness of the material layer of the required etching of third through-hole 703 to form described first through hole the 701, second through hole 702, carry out in the etching process of first through hole the 701, second through hole 702 and third through-hole 703 at the same time, the speed of etching all can keep consistent with the degree of depth, have only to once etching and just can concurrently form above-mentioned through hole, it is possible to save processing step.
Refer to Figure 10, fill described first through hole 701(and refer to Fig. 9), the second through hole (refer to Fig. 9) and third through-hole 703(refer to Fig. 9), form the first connector the 711, second connector 712 and the 3rd connector 713.
Fill described first through hole 701(and refer to Fig. 9), the second through hole 702(refer to Fig. 9) and third through-hole 703(refer to Fig. 9) material be Cu, W or Al, described material can be identical with the material of the first metal layer 101, can also differ, in the present embodiment, the material of described filling is Cu.
In the present embodiment, fill described first through hole 701(and refer to Fig. 9), second through hole 702(refer to Fig. 9) and third through-hole 703(refer to Fig. 9), the method forming connector is: adopt chemical vapor deposition method, formed and cover described mask layer 600(and refer to Fig. 9) surface and fill full described first through hole 701, the plug material Cu of the second through hole 702 and third through-hole 703, then planarize, remove described mask layer 600(and refer to Fig. 9) Cu on surface and mask layer 600, form the first connector 711, second connector 712 and the 3rd connector 713.Described first connector the 711, second connector 712 and the surface of the 3rd connector 713 flush with the surface of the 3rd dielectric layer 500.
In other embodiments of the invention, before filling described first through hole, the second through hole and third through-hole, can also being initially formed one layer of diffusion impervious layer in the inner wall surface of described first through hole, the second through hole and third through-hole, described diffusion impervious layer can stop that the follow-up metal filled in through hole outwards diffuses in insulating barrier and each interlayer dielectric layer.The material of described diffusion impervious layer can be TiN, TaN or TiW.
Being positioned at the first metal layer 101 surface bottom the first connector 711 formed, the first connector 711 sidewall and the 3rd dielectric layer 500, insulating barrier the 300, first electrode layer 202, second dielectric layer 103 connect；Being positioned at first medium layer 100 surface of second area II bottom second connector 712, the second connector 712 sidewall and the 3rd dielectric layer 500, the second electrode lay 401, insulating barrier 300, second dielectric layer 103 connect；The bottom of the 3rd connector 713 is positioned at the second metal level 102 surface, the sidewall of the 3rd connector 713 and the 3rd dielectric layer 500, insulating barrier the 300, first electrode layer 202, second dielectric layer 103 and connects.
First electrode layer 202 of the described bottom electrode as MIN electric capacity is connected with the first metal layer 101 by the sidewall of the first connector 711；The second electrode lay 401 as the upper electrode of MIM capacitor is connected with the second connector 712 sidewall；3rd connector 713 is connected with the first metal layer 101.
Be connected with the bottom electrode of MIM capacitor by the first connector 711, the sidewall of the second connector 712 is connected with the upper electrode of MIM capacitor.And prior art is formed and in MIM capacitor upper/lower electrode connector process connected vertically, it is easy to over etching can be caused to penetrate the electrode of electric capacity the upper/lower electrode of MIM capacitor, affect the performance of electric capacity.The substrate of electric capacity will not be caused over etching by the method forming described first connector 711 and the second connector 712 in described the present embodiment, such that it is able to prevent from affecting the performance of electric capacity.
Refer to Figure 11, form the 3rd metal level 801 covering described second connector 712 and the 3rd connector 713 surface on the 3rd dielectric layer 500 surface.
The material of described 3rd metal level 801 is identical with the material of the first metal layer the 101, second metal level 102, including Cu, W or Al.
The concrete method forming described 3rd metal level 801 includes: existing the 3rd metal material layer (not shown) forming described 3rd dielectric layer 500 of covering and first connector the 711, second connector 712 and the 3rd connector 713, the mask layer with opening is formed again on described 3rd metal material layer surface, described mask layer covers the position of described 3rd metal level 801, described 3rd metal material layer is etched along described opening, form the 3rd metal level 801, then remove described mask layer.
Described 3rd metal level 801, as metal interconnecting layer, is connected by connector between the semiconductor device cell that described 3rd dielectric layer 500 is formed over follow-up.The second electrode lay 401 of the described upper electrode as MIM capacitor is connected with the second connector 712, and be connected with the 3rd metal level 801 by the second connector 712, follow-up can be connected with the follow-up device cell being formed at the 3rd dielectric layer 500 again through the 3rd metal level 801.3rd connector 713 is as the interconnection structure of interlayer simultaneously, connects the second metal level 102 and the 3rd metal level 801.
The first metal layer 101 may be used for the source/drain region of other interconnection structures or the semiconductor device being connected in Semiconductor substrate by the bottom electrode of MIM capacitor.The upper electrode of MIM capacitor can be connected to the source/drain region of other interconnection structures or semiconductor device by the 3rd metal level 801 by the second connector 712.
The present embodiment additionally provides the MIM capacitor adopting said method to be formed.
Please continue to refer to Figure 11, for the cross-sectional view of the MIM capacitor that the present embodiment is formed.
Described MIM capacitor includes: substrate, adjacent first area I, second area II and the three region III, described part of substrate is positioned at first area I, part of substrate is positioned at second area II, part of substrate is positioned at the 3rd region III.
In the present embodiment, described substrate includes second metal level 102 of the first metal layer 101 in the first medium layer 100 of first medium layer 100 and first area I and the 3rd region III, and described the first metal layer 101 and the surface of the second metal level 102 flush with the surface of first medium layer 100；It is positioned at the second dielectric layer 103 on first medium layer 100 surface, the first metal layer 101 surface and the second metal level 102 surface.
The MIM capacitor of this enforcement also includes: be positioned at the 3rd dielectric layer 103 surface the first electrode layer 202 of first area I and first electrode layer 202 ' on second dielectric layer 103 surface of the 3rd region III；It is positioned at the insulating barrier 300 on the first electrode layer (202,202 ') and second dielectric layer 103 surface；It is positioned at the second electrode lay 401 on insulating barrier 300 surface, wherein, the described the second electrode lay 401 of part is positioned at first area I, the described the second electrode lay 401 of part is positioned at second area II, be positioned at the second electrode lay 401 of first area I expose described in be positioned at the partial insulative layer 300 of first area I, and the thickness of described the second electrode lay is identical with the thickness of material and the first electrode layer and material；It is positioned at the 3rd dielectric layer 500 of the planarization on insulating barrier 300 and the second electrode lay 401 surface；It is positioned at the first connector the 711, second connector 712 and the 3rd connector 713 of described substrate surface, wherein, being positioned at the first metal layer 101 surface bottom first connector 711, the first connector 711 sidewall and the 3rd dielectric layer 500, insulating barrier the 300, first electrode layer 202, second dielectric layer 103 connect；First medium layer 100 surface it is positioned at bottom second connector 712, sidewall and the 3rd dielectric layer 500, the second electrode lay 401, insulating barrier 300, the second dielectric layer 103 of the second connector 712 connect, the bottom of the 3rd connector 713 is positioned at the second metal level 102 surface, the sidewall of the 3rd connector 713 and the 3rd dielectric layer 500, insulating barrier the 300, first electrode layer 202 ', second dielectric layer 103 and connects；It is positioned at the 3rd dielectric layer 500 surface, the 3rd metal level 801 being connected with the second connector 712 and the 3rd connector 713.
Concrete, the thickness of described first electrode layer (202,202 ') and the second electrode lay 401 is 10 nanometers ~ 40 nanometers, and described first electrode layer (202,202 ') is identical with the thickness of the second electrode lay 401.Described first electrode layer 202 is identical with the material of the second electrode lay 401, including TiN, Ti, TaN, Ta, WN, W or TiW therein one or more.
The material of described insulating barrier 300 is high K medium material, including HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3, one in BaSrTiO several.The thickness of described insulating barrier 300 is 1 nanometer ~ 5 nanometers.
The material of described first connector the 711, second connector 712 and the 3rd connector 713 is Cu, W or Al.In other embodiments of the invention, described first connector, the second connector and the 3rd connector outer layer can also have diffusion impervious layer, and the material of described diffusion impervious layer can be TiN, TaN or TiW.Described diffusion impervious layer can stop the metal in connector outwards to diffuse in insulating barrier and each interlayer dielectric layer, destroys the performance of electric capacity.
In other embodiments of the invention, described insulating barrier 300 and the first electrode layer 202 surface, second dielectric layer 103 surface between there is passivation layer, also there is between described insulating barrier and the second electrode lay passivation layer.The material of described passivation layer includes Al2O3, SiN or SiO2Deng material, passivation layer can stop the ion in insulating barrier to spread in the first electrode layer and the second electrode lay, it is prevented that capacity fall off and reduce the performance of MIM capacitor.The thickness of described passivation layer is 10 angstroms ~ 1 nanometer.
In the present embodiment, it is connected with the sidewall of the first connector 711 as the first electrode layer 202 of MIM capacitor bottom electrode, is connected with the sidewall of the second connector 712 as the second electrode lay 401 of upper electrode of MIM capacitor, and the first electrode 202, insulating barrier 300 and the second electrode 401 are as the live part of MIM capacitor, described first connector 711 and the second connector 712 are positioned at the side of the live part of described MIM capacitor, the impact of electric capacity upper/lower electrode is less, do not have a upper electrode penetrating electric capacity or problem that bottom electrode is connected with the dielectric layer of electric capacity and makes condenser failure.
Although the present invention is with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art are without departing from the spirit and scope of the present invention; may be by the method for the disclosure above and technology contents and technical solution of the present invention is made possible variation and amendment; therefore; every content without departing from technical solution of the present invention; according to any simple modification, equivalent variations and modification that above example is made by the technical spirit of the present invention, belong to the protection domain of technical solution of the present invention.
Claims (16)
1. the forming method of a MIM capacitor, it is characterised in that including:
Thering is provided substrate, adjacent first area, second area and the 3rd region, part of substrate is positioned at first area, and part of substrate is positioned at second area, and part of substrate is positioned at the 3rd region；
The first electrode layer is concurrently formed on the surface of described first area and the substrate in the 3rd region；
Insulating barrier is formed in described first electrode layer surface and substrate surface；
The second electrode lay is formed at described surface of insulating layer, the described the second electrode lay of part is positioned at first area, the described the second electrode lay of part is positioned at second area, the second electrode lay being positioned at first area exposes the partial insulative layer being positioned at first area, and the thickness of described the second electrode lay is identical with the thickness of material and the first electrode layer and material；
Form the 3rd dielectric layer on the second electrode lay surface and surface of insulating layer and planarize described 3rd dielectric layer；
Concurrently form the first through hole, the second through hole and third through-hole, wherein, described first through hole sequentially passes through the first electrode layer of the 3rd dielectric layer, insulating barrier and first area, described second through hole sequentially passes through the insulating barrier of the 3rd dielectric layer, the second electrode lay and second area, and first the 3rd thickness of dielectric layers that runs through of the 3rd thickness of dielectric layers that runs through of through hole and the second through hole identical, described third through-hole sequentially passes through first electrode layer in the 3rd dielectric layer, insulating barrier and the 3rd region.
2. the forming method of MIM capacitor according to claim 1, it is characterized in that, described substrate includes: first medium layer and be positioned at the first metal layer of first medium layer of first area and be positioned at second metal level of first medium layer in the 3rd region, the surface of described the first metal layer and the surface of the second metal level flush with the surface of first medium layer, and are positioned at the second dielectric layer of described first medium layer surface, the first metal layer surface and the second layer on surface of metal；Described first through hole, the second through hole and third through-hole also extend through described second dielectric layer.
3. the forming method of MIM capacitor according to claim 1, it is characterised in that the thickness of described first electrode layer is 10 nanometers～40 nanometers, the thickness of the second electrode lay is 10 nanometers～40 nanometers.
4. the forming method of MIM capacitor according to claim 1, it is characterised in that the material of described first electrode layer is TiN, Ti, TaN, Ta, WN, W or TiW, the material of the second electrode lay is TiN, Ti, TaN, Ta, WN, W or TiW.
5. the forming method of MIM capacitor according to claim 1, it is characterised in that the material of described insulating barrier is high K medium material.
6. the forming method of MIM capacitor according to claim 1, it is characterised in that the thickness of described insulating barrier is 1 nanometer～5 nanometers.
7. the forming method of MIM capacitor according to claim 1, it is characterized in that, also include, fill described first through hole, the second through hole and third through-hole, forming the first connector, the second connector and the 3rd connector, the material filling described first connector, the second connector and the 3rd connector is Cu, W or Al.
8. the forming method of MIM capacitor according to claim 7, it is characterised in that also include, forms the 3rd metal level being connected with the second connector and the 3rd connector at the 3rd dielectric layer surface.
9. a MIM capacitor, it is characterised in that including:
Substrate, adjacent first area, second area and the 3rd region, part of substrate is positioned at first area, and part of substrate is positioned at second area, and part of substrate is positioned at the 3rd region；
It is positioned at the first electrode layer of the substrate surface in first area and the 3rd region；
It is positioned at the insulating barrier of the first electrode layer and substrate surface；
It is positioned at the second electrode lay of surface of insulating layer, the described the second electrode lay of part is positioned at first area, the described the second electrode lay of part is positioned at second area, the second electrode lay being positioned at first area exposes the partial insulative layer being positioned at first area, and the thickness of described the second electrode lay is identical with the thickness of material and the first electrode layer and material；
Being positioned at the 3rd dielectric layer of the second electrode lay surface and surface of insulating layer, described 3rd dielectric layer surface is smooth；
First connector, described first connector runs through the first electrode layer of the 3rd dielectric layer, insulating barrier and first area；
Second connector, described second connector runs through the insulating barrier of the 3rd dielectric layer, the second electrode lay and second area；
3rd connector, described 3rd connector runs through first electrode layer in the 3rd dielectric layer, insulating barrier and the 3rd region.
10. MIM capacitor according to claim 9, it is characterized in that, described substrate includes: first medium layer and be positioned at the first metal layer of first medium layer of first area and be positioned at second metal level of first medium layer in the 3rd region, and the surface of described the first metal layer and the second metal level flushes with the surface of first medium layer；It is positioned at the second dielectric layer of described first medium layer, the first metal layer and the second layer on surface of metal；Described first connector, the second connector and the 3rd connector also extend through described second dielectric layer.
11. MIM capacitor according to claim 9, it is characterised in that the thickness of described first electrode layer is 10 nanometers～40 nanometers, the thickness of the second electrode lay is 10 nanometers～40 nanometers.
12. MIM capacitor according to claim 9, it is characterised in that the material of described first electrode layer is TiN, Ti, TaN, Ta, WN, W or TiW, the material of the second electrode lay is TiN, Ti, TaN, Ta, WN, W or TiW.
13. MIM capacitor according to claim 9, it is characterised in that the material of described insulating barrier is high K medium material.
14. MIM capacitor according to claim 9, it is characterised in that the thickness of described insulating barrier is 1 nanometer～5 nanometers.
15. MIM capacitor according to claim 9, it is characterised in that also include: be positioned at the 3rd metal level being connected with the second connector and the 3rd connector of the 3rd dielectric layer surface.
16. MIM capacitor according to claim 9, it is characterised in that the material of described first connector, the second connector and the 3rd connector is Cu, W or Al.
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