CN103905002B - A kind of low-temperature coefficient variable gain amplifier promoting gain variation range - Google Patents
A kind of low-temperature coefficient variable gain amplifier promoting gain variation range Download PDFInfo
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- CN103905002B CN103905002B CN201410086961.9A CN201410086961A CN103905002B CN 103905002 B CN103905002 B CN 103905002B CN 201410086961 A CN201410086961 A CN 201410086961A CN 103905002 B CN103905002 B CN 103905002B
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Abstract
nullThe invention discloses a kind of low-temperature coefficient variable gain amplifier promoting gain variation range，Including variable gain circuit、Cross-couplings temperature-compensation circuit and gain control circuit，Variable gain circuit adjusts circuit gain with stable output according to input signal strength，Negative resistance is used to constitute positive feedback to promote the mutual conductance current efficiency of input transconductance stage as source-degeneration resistance，The transistor connected by diode to and cross-couplings connect transistor to constituting active load，In the case of difference mode signal，Cross-coupled pair reduces, as a negative conductance, the conductance that load is overall，The common-mode gain of circuit is the lowest，Not only increase the gain of circuit by introducing cross-coupled pair and improve the common mode inhibition capacity of circuit，Cross-coupled pair and a reference source with positive temperature characterisitic constitute temperature-compensation circuit simultaneously，The variable-gain-circuit gain range caused due to variations in temperature with compensation.The advantages such as the present invention has one pass gain range of accommodation technique change big, anti-, resisting temperature changes and low in energy consumption.
Description
Technical field
The present invention relates to a kind of low-temperature coefficient variable gain amplifier promoting gain variation range.
Background technology
Variable gain amplifier is as a key modules of wireless receiver, the research of its design always radio frequency, the study hotspot of Analogous Integrated Electronic Circuits.In a wireless communication system, owing to external environment changes such as temperature, the impact of barrier etc., receiver received signal Strength Changes is the biggest, if receiver signal link gain is constant, will strong signal blocking when receiving big signal, if receiving the most weak signal easily to be flooded by noise, cannot demodulate, therefore it is required that the gain of receiver adjusts automatically according to the strong and weak of signal, when i.e. reception signal is strong, receiver gain reduces, when received signal strength is weak, increasing receiver gain, this function is mainly completed by variable gain amplifier.Variable gain amplifier plays change receiver gain, stablizes the effect of output signal power.Promote the low-temperature coefficient variable gain amplifier of gain variation range due to its gain consecutive variations, and SPA sudden phase anomalies will not be occurred to be widely adopted, the low-temperature coefficient variable gain amplifier of conventional lift gain variation range is limited due to one pass gain, for increasing the method that gain-adjusted scope often uses multi-stage cascade, but these methods circuit power consumption while increasing gain-adjusted scope also will dramatically increase, and gain-adjusted scope temperature influence is obvious.So promoting the gain-adjusted scope of single stage Variable Gain amplifier on the premise of not increasing power consumption, and ensure that circuit can normally work in the presence of a harsh environment and still suffer from many challenges.
Accordingly, it would be desirable to the low-temperature coefficient variable gain amplifier of a kind of new lifting gain variation range is to solve the problems referred to above.
Summary of the invention
Goal of the invention: the present invention is directed to the defect of variable gain amplifier in prior art, it is provided that a kind of low-temperature coefficient variable gain amplifier promoting gain variation range.
Technical scheme: for solving above-mentioned technical problem, the low-temperature coefficient variable gain amplifier of the lifting gain variation range of the present invention adopts the following technical scheme that
A kind of low-temperature coefficient variable gain amplifier promoting gain variation range, including variable gain circuit, cross-couplings temperature-compensation circuit and gain control circuit；
nullWherein，Described variable gain circuit includes the first p-type MOS transistor、Second p-type MOS transistor、First N-type MOS transistor、Second N-type MOS transistor、3rd N-type MOS transistor、4th N-type MOS transistor、5th N-type MOS transistor、6th N-type MOS transistor、7th N-type MOS transistor、8th N-type MOS transistor、9th N-type MOS transistor、Tenth N-type MOS transistor、11st N-type MOS transistor、12nd N-type MOS transistor、13rd N-type MOS transistor、14th N-type MOS transistor、15th N-type MOS transistor、16th N-type MOS transistor and the first current source (I1)；
The grid of described first p-type MOS transistor and the grid of described second p-type MOS transistor connect；
The source electrode of described first p-type MOS transistor and the source electrode of described second p-type MOS transistor connect；
The drain electrode of the drain electrode of described first p-type MOS transistor, the grid of described first N-type MOS transistor, the drain electrode of described 7th N-type MOS transistor and described 9th N-type MOS transistor connects；
The drain electrode of the drain electrode of described second p-type MOS transistor, the grid of described second N-type MOS transistor, the drain electrode of described 8th N-type MOS transistor and described tenth N-type MOS transistor connects；
The drain electrode of the grid of described 9th N-type MOS transistor, the grid of described tenth N-type MOS transistor, the grid of described 15th N-type MOS transistor, the grid of described 16th N-type MOS transistor, the grid of described 13rd N-type MOS transistor, described first current source and described 16th N-type MOS transistor connects；
The source electrode of described 7th N-type MOS transistor, described 9th N-type MOS transistor source electrode, the drain electrode of the 11st N-type MOS transistor, the drain electrode of the 13rd N-type MOS transistor and the 12nd N-type MOS transistor grid connect；
The source electrode of described 8th N-type MOS transistor, described tenth N-type MOS transistor source electrode, the drain electrode of the 12nd N-type MOS transistor, the drain electrode of the 15th N-type MOS transistor and the 11st N-type MOS transistor grid connect；
The source electrode of the source electrode of described 13rd N-type MOS transistor, the source electrode of described 14th N-type MOS transistor, the source electrode of described 15th N-type MOS transistor and described 16th N-type MOS transistor connects and ground connection；
The drain electrode of source electrode, the source electrode of the 12nd N-type MOS transistor and the described 14th N-type MOS transistor of described 11st N-type MOS transistor connects；
The drain electrode of the drain electrode of the first N-type MOS transistor, the grid of the first N-type MOS transistor, the grid of the 3rd N-type MOS transistor and the 4th N-type MOS transistor connects；
The drain electrode of the drain electrode of the second N-type MOS transistor, the grid of the second N-type MOS transistor, the grid of the 4th N-type MOS transistor and the 3rd N-type MOS transistor connects；
The drain electrode of the source electrode of the 3rd N-type MOS transistor, the source electrode of the 4th N-type MOS transistor and the 6th N-type MOS transistor is connected；
The drain electrode of the source electrode of the first N-type MOS transistor, the source electrode of the second N-type MOS transistor and the 5th N-type MOS transistor connects；
The source electrode of the 5th N-type MOS transistor and the source electrode of the 6th N-type MOS transistor connect and ground connection；
The grid of described 7th N-type MOS transistor and the grid of described 8th N-type MOS transistor are respectively as normal phase input end (Vip) and negative-phase input (Vin)；The drain electrode of described first p-type MOS transistor and the drain electrode of described second p-type MOS transistor export (Vop) respectively as anti-phase output (Von) and positive；
Described cross-couplings temperature-compensation circuit includes the 3rd p-type MOS transistor, the 4th p-type MOS transistor, the 17th N-type MOS transistor, the 18th N-type MOS transistor, the 19th N-type MOS transistor and the first resistance；
The drain electrode of the grid of described 3rd p-type MOS transistor, the grid of described 4th p-type MOS transistor and described 17th N-type MOS transistor connects；
The grid of the source electrode of described 17th N-type MOS transistor, the grid of described 18th N-type MOS transistor, the drain electrode of described 18th N-type MOS transistor and described 19th N-type MOS transistor connects；
The grid of the drain electrode of described 4th p-type MOS transistor, the drain electrode of described 19th N-type MOS transistor, the drain electrode of described 17th N-type MOS transistor and described 17th N-type MOS transistor connects；
The drain electrode of the drain electrode of described 3rd p-type MOS transistor, the grid of described 18th N-type MOS transistor and described 18th N-type MOS transistor connects；
The source electrode of described 18th N-type MOS transistor and described 19th N-type MOS transistor source electrode are connected by described first resistance, the source ground of described 18th N-type MOS transistor；
The grid of described 18th N-type MOS transistor is connected with the grid of described 6th N-type MOS transistor.
Further, described gain control circuit includes the 5th p-type MOS transistor, 6th p-type MOS transistor, 7th p-type MOS transistor, 8th p-type MOS transistor, 9th p-type MOS transistor, tenth p-type MOS transistor, 20th N-type MOS transistor, 21st N-type MOS transistor, 22nd N-type MOS transistor, 23rd N-type MOS transistor, 24th N-type MOS transistor, 25th N-type MOS transistor, 26th N-type MOS transistor and the second resistance,
The source electrode of source electrode, the source electrode of the 6th p-type MOS transistor, the source electrode of the 7th p-type MOS transistor, the source electrode of the 8th p-type MOS transistor, the source electrode of the 9th p-type MOS transistor and the tenth p-type MOS transistor of described 5th p-type MOS transistor connects；
The drain electrode of the drain electrode of described 5th p-type MOS transistor, the drain electrode of described 6th p-type MOS transistor, the grid of described 22nd N-type MOS transistor and described 22nd N-type MOS transistor connects；
The grid of described 7th p-type MOS transistor and the grid of described 8th p-type MOS transistor connect；
The grid of the drain electrode of described 8th p-type MOS transistor, the drain electrode of described 23rd N-type MOS transistor and described 23rd N-type MOS transistor connects；
The source electrode of the drain electrode of described 9th p-type MOS transistor, the drain electrode of described 24th N-type MOS transistor, the grid of described 21st N-type MOS transistor, the grid of described 24th N-type MOS transistor, the grid of described 25th N-type MOS transistor and described 26th N-type MOS transistor connects；
The grid of the grid of described 9th p-type MOS transistor, the grid of described tenth p-type MOS transistor, the drain electrode of described tenth p-type MOS transistor, the grid of described 26th N-type MOS transistor, the drain electrode of described 26th N-type MOS transistor, the drain electrode of described 25th N-type MOS transistor and described 6th p-type MOS transistor connects；
The source electrode of the source electrode of described 20th N-type MOS transistor, the source electrode of described 21st N-type MOS transistor, the source electrode of described 22nd N-type MOS transistor, the source electrode of described 23rd N-type MOS transistor, the source electrode of described 24th N-type MOS transistor and described 25th N-type MOS transistor is all connected with and ground connection；
The drain electrode of the drain electrode of described 20th N-type MOS transistor, the drain electrode of described 21st N-type MOS transistor and described 7th p-type MOS transistor connects；
It is provided with described second resistance between source electrode and the earth point of described 25th N-type MOS transistor.
Beneficial effect: the variable gain amplifier of the present invention, on the basis of promoting conventional variable gain amplifier gain range of accommodation, has good temp characteristic, the feature of anti-technique change simultaneously.As source-degeneration resistance by introducing negative resistance in the input stage of variable gain amplifier thus constitute positive feedback and double input mutual conductance, to improve the mutual conductance current efficiency of input stage.Promote circuit gain range of accommodation, simultaneously this variable gain amplifier use the transistor that connected by diode to and the transistor that connects of the cross-couplings active load to constituting, in the case of input difference mode signal, cross-coupled pair reduces the conductance of overall load as a negative conductance, so the differential mode voltage gain of one-stage amplifier can be configured to a sufficiently high value, and in the case of common-mode signal, cross-coupled pair improves the conductance of load as a positive conductance, therefore the common-mode gain of circuit is the lowest, not only considerably improve the gain of circuit by introducing cross-coupled pair but also improve the common mode inhibition capacity of traditional circuit.Generally amplifier gain raises with the temperature of working environment, gain will be decreased obviously, cross-couplings temperature-compensation circuit in the design by controlling the value of negative conductance with the current source of PTAT, when the temperature increases, the current source current increase with positive temperature characterisitic makes cross-coupled pair negative conductance increase, due to the variable gain amplifier in the present invention load use the transistor that connected by diode to and the transistor that connects of the cross-couplings active load to constituting, the gain reduction that can cause owing to temperature raises with effective compensation by this method, equally, temperature reduces current source current increase and cross-coupled pair negative conductance is reduced, such that it is able to the gain that effective compensation causes owing to temperature reduces raises.
Accompanying drawing explanation
Fig. 1 is the low-temperature coefficient gain-changeable amplifier circuit figure of the lifting gain variation range of the present invention；
Fig. 2 is the low-temperature coefficient variable-gain amplifier gain excursion simulation result figure of the lifting gain variation range of the present invention；
Fig. 3 is the low-temperature coefficient variable gain amplifier different gains curve simulation result figure of the lifting gain variation range of the present invention；
Fig. 4 is that the low-temperature coefficient variable-gain amplifier gain of the lifting gain variation range of the present invention varies with temperature simulation result figure.
Detailed description of the invention
With detailed description of the invention, the present invention is described in further detail below in conjunction with the accompanying drawings:
Referring to shown in Fig. 1, the low-temperature coefficient variable gain amplifier of the lifting gain variation range of the present invention, including variable gain circuit, cross-couplings temperature-compensation circuit and gain control circuit.
nullWherein，Variable gain circuit includes the first p-type MOS transistor P1、Second p-type MOS transistor P2、First N-type MOS transistor N1、Second N-type MOS transistor N2、3rd N-type MOS transistor N3、4th N-type MOS transistor N4、5th N-type MOS transistor N5、6th N-type MOS transistor N6、7th N-type MOS transistor N7、8th N-type MOS transistor N8、9th N-type MOS transistor N9、Tenth N-type MOS transistor N10、11st N-type MOS transistor N11、12nd N-type MOS transistor N12、13rd N-type MOS transistor N13、14th N-type MOS transistor N14、15th N-type MOS transistor N15、16th N-type MOS transistor N16 and the first current source I1.
The grid of the first p-type MOS transistor P1 and the grid of the second p-type MOS transistor P2 connect.The source electrode of the first p-type MOS transistor P1 and the source electrode of the second p-type MOS transistor P2 connect.The drain electrode of the drain electrode of the first p-type MOS transistor P1, the grid of the first N-type MOS transistor N1, the drain electrode of the 7th N-type MOS transistor N7 and the 9th N-type MOS transistor N9 connects.The drain electrode of the drain electrode of the second p-type MOS transistor P2, the grid of the second N-type MOS transistor N2, the drain electrode of the 8th N-type MOS transistor N8 and the tenth N-type MOS transistor N10 connects.The grid of the 9th N-type MOS transistor N9, the grid of the tenth N-type MOS transistor N10, the grid of the 15th N-type MOS transistor N15, the grid of the 16th N-type MOS transistor N16, the grid of the 13rd N-type MOS transistor N13, the drain electrode of the first current source I1 and the 16th N-type MOS transistor N16 connect.The grid of the source electrode of the 7th N-type MOS transistor N7, the source electrode of the 9th N-type MOS transistor N9, the drain electrode of the 11st N-type MOS transistor N11, the drain electrode of the 13rd N-type MOS transistor N13 and the 12nd N-type MOS transistor N12 connects.The grid of the source electrode of the 8th N-type MOS transistor N8, the source electrode of the tenth N-type MOS transistor N10, the drain electrode of the 12nd N-type MOS transistor N12, the drain electrode of the 15th N-type MOS transistor N15 and the 11st N-type MOS transistor N11 connects.The source electrode of the source electrode of the 13rd N-type MOS transistor N13, the source electrode of the 14th N-type MOS transistor N14, the source electrode of the 15th N-type MOS transistor N15 and the 16th N-type MOS transistor N16 connects and ground connection.The drain electrode of the source electrode of the 11st N-type MOS transistor N11, the source electrode of the 12nd N-type MOS transistor N12 and the 14th N-type MOS transistor N14 connects.The drain electrode of the drain electrode of the first N-type MOS transistor N1, the grid of the first N-type MOS transistor N1, the grid of the 3rd N-type MOS transistor N3 and the 4th N-type MOS transistor N4 connects.The drain electrode of the drain electrode of the second N-type MOS transistor N2, the grid of the second N-type MOS transistor N2, the grid of the 4th N-type MOS transistor N4 and the 3rd N-type MOS transistor N3 connects.The drain electrode of the source electrode of the 3rd N-type MOS transistor N3, the source electrode of the 4th N-type MOS transistor N4 and the 6th N-type MOS transistor N6 is connected.The drain electrode of the source electrode of the first N-type MOS transistor N1, the source electrode of the second N-type MOS transistor N2 and the 5th N-type MOS transistor N5 connects.The source electrode of the 5th N-type MOS transistor N5 and the source electrode of the 6th N-type MOS transistor N6 connect and ground connection.The grid of the 7th N-type MOS transistor N7 and the grid of the 8th N-type MOS transistor N8 are respectively as normal phase input end Vip and negative-phase input Vin.The drain electrode of the first p-type MOS transistor P1 and the drain electrode of the second p-type MOS transistor P2 export Vop respectively as anti-phase output Von and positive.
Cross-couplings temperature-compensation circuit includes the 3rd p-type MOS transistor P3, the 4th p-type MOS transistor P4, the 17th N-type MOS transistor N17, the 18th N-type MOS transistor N18, the 19th N-type MOS transistor N19 and the first resistance R1.
The drain electrode of the grid of the 3rd p-type MOS transistor P3, the grid of the 4th p-type MOS transistor P4 and the 17th N-type MOS transistor N17 connects.The grid of the source electrode of the 17th N-type MOS transistor N17, the grid of the 18th N-type MOS transistor N18, the drain electrode of the 18th N-type MOS transistor N18 and the 19th N-type MOS transistor N19 connects.The grid of the drain electrode of the 4th p-type MOS transistor P4, the drain electrode of the 19th N-type MOS transistor N19, the drain electrode of the 17th N-type MOS transistor N17 and the 17th N-type MOS transistor N17 connects.The drain electrode of the drain electrode of the 3rd p-type MOS transistor P3, the grid of the 18th N-type MOS transistor N18 and the 18th N-type MOS transistor N18 connects.The source electrode of the 18th N-type MOS transistor N18 and the 19th N-type MOS transistor N19 source electrode are connected by the first resistance R1, the source ground of the 18th N-type MOS transistor N18.The grid of the 18th N-type MOS transistor N18 and the grid of the 6th N-type MOS transistor N6 connect.
Gain control circuit includes the 5th p-type MOS transistor P5, 6th p-type MOS transistor P6, 7th p-type MOS transistor P7, 8th p-type MOS transistor P8, 9th p-type MOS transistor P9, tenth p-type MOS transistor P10, 20th N-type MOS transistor N20, 21st N-type MOS transistor N21, 22nd N-type MOS transistor N22, 23rd N-type MOS transistor N23, 24th N-type MOS transistor N24, 25th N-type MOS transistor N25, 26th N-type MOS transistor N26 and the second resistance R2,
The source electrode of the source electrode of the 5th p-type MOS transistor P5, the source electrode of the 6th p-type MOS transistor P6, the source electrode of the 7th p-type MOS transistor P7, the source electrode of the 8th p-type MOS transistor P8, the source electrode of the 9th p-type MOS transistor P9 and the tenth p-type MOS transistor P10 connects.The drain electrode of the drain electrode of the 5th p-type MOS transistor P5, the drain electrode of the 6th p-type MOS transistor P6, the grid of the 22nd N-type MOS transistor N22 and the 22nd N-type MOS transistor N22 connects.The grid of the 7th p-type MOS transistor P7 and the grid of the 8th p-type MOS transistor P8 connect.The grid of the drain electrode of the 8th p-type MOS transistor P8, the drain electrode of the 23rd N-type MOS transistor N23 and the 23rd N-type MOS transistor N23 connects.The source electrode of the drain electrode of the 9th p-type MOS transistor P9, the drain electrode of the 24th N-type MOS transistor N24, the grid of the 21st N-type MOS transistor N21, the grid of the 24th N-type MOS transistor N24, the grid of the 25th N-type MOS transistor N25 and the 26th N-type MOS transistor N26 connects.The grid of the grid of the 9th p-type MOS transistor P9, the grid of the tenth p-type MOS transistor P10, the drain electrode of the tenth p-type MOS transistor P10, the grid of the 26th N-type MOS transistor N26, the drain electrode of the 26th N-type MOS transistor N26, the drain electrode of the 25th N-type MOS transistor N25 and the 6th p-type MOS transistor P6 connects.The source electrode of the source electrode of the 20th N-type MOS transistor N20, the source electrode of the 21st N-type MOS transistor N21, the source electrode of the 22nd N-type MOS transistor N22, the source electrode of the 23rd N-type MOS transistor N23, the source electrode of the 24th N-type MOS transistor N24 and the 25th N-type MOS transistor N25 is all connected with and ground connection.The drain electrode of the drain electrode of the 20th N-type MOS transistor N20, the drain electrode of the 21st N-type MOS transistor N21 and the 7th p-type MOS transistor P7 connects.It is provided with the second resistance R2 between source electrode and the earth point of the 25th N-type MOS transistor N25.
For promoting the gain-adjusted scope of single stage Variable Gain amplifier, the design introduces the 11st N-type MOS transistor N11 and the 12nd N-type MOS transistor N12 in input stage and constitutes negative resistance respectively as Differential Input to the 7th N-type MOS transistor N7 and the 8th N-type MOS transistor N8 source-degeneration resistance, local constitutes positive feedback multiplication input mutual conductance, to improve the mutual conductance current efficiency of input stage.This variable gain amplifier uses active load, 3rd N-type MOS transistor N3 and the 4th N-type MOS transistor N4 is constituted by the transistor that the first N-type MOS transistor N1 and the second N-type MOS transistor N2 is connected by its transistor connected by diode with cross-couplings, in the case of difference mode signal, cross-coupled pair is handed over to reduce the conductance of overall load as a negative conductance, so the differential mode voltage gain of one-stage amplifier can be configured to a sufficiently high value, and in the case of common-mode signal, cross-coupled pair improves the conductance of the load of entirety as a positive conductance, therefore the common-mode gain of circuit is the lowest, not only considerably improve the gain of circuit by introducing cross-coupled pair but also improve the common mode inhibition capacity of traditional circuit.Generally amplifier gain raises with the temperature of working environment, gain will be decreased obviously, cross-couplings temperature-compensation circuit in the design by controlling the value of negative conductance with the current source of PTAT, when the temperature increases, the current source current increase with positive temperature characterisitic makes cross-coupled pair negative conductance increase, due to the variable gain amplifier in the present invention load use the transistor that connected by diode to and the transistor that connects of the cross-couplings active load to constituting, the gain reduction that can cause owing to temperature raises with effective compensation by this method, equally, temperature reduces current source current increase and cross-coupled pair negative conductance is reduced, such that it is able to the gain that effective compensation causes owing to temperature reduces raises.The tail current source that amplifier gain regulation is connected transistor by exponent circuit generation with the current signal control input stage tail current source controlling voltage signal exponent function relation and load stage diode realizes gain continuous dB change.
Fig. 2 show the gain-adjusted scope same tradition Structure Comparison figure of the present invention, and gain-adjusted scope the most of the present invention has the lifting of about 3 times compared with traditional circuit.The detailed description of this principle is referred to technical scheme and detailed description of the invention part with explanation.
Fig. 3 show the amplitude-versus-frequency curve in the case of different gains of the present invention, from figure 3, it can be seen that under different gain control signals (Vc), circuit gain realizes change and bandwidth is constant.
Fig. 4 show gain-adjusted scope of the present invention simulation result at different temperatures, it can be seen that the input-output characteristic after compensation essentially coincides at-50 °-100 °, has preferable temperature stability.
The invention provides a kind of implementation method of full analogue variable gain amplifier, use standard CMOS process to realize so that this variable gain amplifier has the advantages such as gain-adjusted scope is big, resisting temperature changes, simple for structure, low in energy consumption.The present invention is based on cross-couplings negative conductance and the thought of source-electrode degradation, and the input stage at variable gain amplifier introduces negative conductance and as source-degeneration resistance thus constitutes positive feedback with input stage mutual conductance of doubling, thus improves the mutual conductance current efficiency of input stage.Simultaneously this variable gain amplifier use the transistor that connected by diode to and the transistor that connects of the cross-couplings active load to constituting, in the case of difference mode signal, cross-coupled pair is handed over to reduce the conductance of overall load as a negative conductance, so the differential mode voltage gain of one-stage amplifier can be configured to a sufficiently high value, and in the case of common-mode signal, cross-coupled pair improves the conductance of overall load as a positive conductance, therefore the common-mode gain of circuit is the lowest, not only considerably improve the gain of circuit by introducing cross-coupled pair but also improve the common mode inhibition energy of circuit, the electric conductivity value of the current source regulation cross-couplings negative conductance by being directly proportional to temperature, thus compensate the change in gain caused due to variations in temperature.
The variable gain amplifier of the present invention, on the basis of promoting conventional variable gain amplifier gain range of accommodation, has good temp characteristic, the feature of anti-technique change simultaneously.As source-degeneration resistance by introducing negative resistance in the input stage of variable gain amplifier thus constitute positive feedback and double input mutual conductance, to improve the mutual conductance current efficiency of input stage.Promote circuit gain range of accommodation, simultaneously this variable gain amplifier use the transistor that connected by diode to and the transistor that connects of the cross-couplings active load to constituting, in the case of input difference mode signal, cross-coupled pair reduces the conductance of overall load as a negative conductance, so the differential mode voltage gain of one-stage amplifier can be configured to a sufficiently high value, and in the case of common-mode signal, cross-coupled pair improves the conductance of load as a positive conductance, therefore the common-mode gain of circuit is the lowest, not only considerably improve the gain of circuit by introducing cross-coupled pair but also improve the common mode inhibition capacity of traditional circuit.Generally amplifier gain raises with the temperature of working environment, gain will be decreased obviously, cross-couplings temperature-compensation circuit in the design by controlling the value of negative conductance with the current source of PTAT, when the temperature increases, the current source current increase with positive temperature characterisitic makes cross-coupled pair negative conductance increase, due to the variable gain amplifier in the present invention load use the transistor that connected by diode to and the transistor that connects of the cross-couplings active load to constituting, the gain reduction that can cause owing to temperature raises with effective compensation by this method, equally, temperature reduces current source current increase and cross-coupled pair negative conductance is reduced, such that it is able to the gain that effective compensation causes owing to temperature reduces raises.
Claims (2)
1. the low-temperature coefficient variable gain amplifier promoting gain variation range, it is characterised in that include variable gain circuit, cross-couplings temperature-compensation circuit and gain control circuit；
nullWherein，Described variable gain circuit includes the first p-type MOS transistor (P1)、Second p-type MOS transistor (P2)、First N-type MOS transistor (N1)、Second N-type MOS transistor (N2)、3rd N-type MOS transistor (N3)、4th N-type MOS transistor (N4)、5th N-type MOS transistor (N5)、6th N-type MOS transistor (N6)、7th N-type MOS transistor (N7)、8th N-type MOS transistor (N8)、9th N-type MOS transistor (N9)、Tenth N-type MOS transistor (N10)、11st N-type MOS transistor (N11)、12nd N-type MOS transistor (N12)、13rd N-type MOS transistor (N13)、14th N-type MOS transistor (N14)、15th N-type MOS transistor (N15)、16th N-type MOS transistor (N16) and the first current source (I1)；
The grid of described first p-type MOS transistor (P1) and the grid of described second p-type MOS transistor (P2) connect；
The source electrode of described first p-type MOS transistor (P1) and the source electrode of described second p-type MOS transistor (P2) connect；
The drain electrode of the drain electrode of described first p-type MOS transistor (P1), the grid of described first N-type MOS transistor (N1), the drain electrode of described 7th N-type MOS transistor (N7) and described 9th N-type MOS transistor (N9) connects；
The drain electrode of the drain electrode of described second p-type MOS transistor (P2), the grid of described second N-type MOS transistor (N2), the drain electrode of described 8th N-type MOS transistor (N8) and described tenth N-type MOS transistor (N10) connects；
The drain electrode of the grid of described 9th N-type MOS transistor (N9), the grid of described tenth N-type MOS transistor (N10), the grid of described 15th N-type MOS transistor (N15), the grid of described 16th N-type MOS transistor (N16), the grid of described 13rd N-type MOS transistor (N13), described first current source (I1) and described 16th N-type MOS transistor (N16) connects；
The source electrode of described 7th N-type MOS transistor (N7), described 9th N-type MOS transistor (N9) source electrode, the drain electrode of the 11st N-type MOS transistor (N11), the drain electrode of the 13rd N-type MOS transistor (N13) and the 12nd N-type MOS transistor (N12) grid connect；
The source electrode of described 8th N-type MOS transistor (N8), described tenth N-type MOS transistor (N10) source electrode, the drain electrode of the 12nd N-type MOS transistor (N12), the drain electrode of the 15th N-type MOS transistor (N15) and the 11st N-type MOS transistor (N11) grid connect；
The source electrode of the source electrode of described 13rd N-type MOS transistor (N13), the source electrode of described 14th N-type MOS transistor (N14), the source electrode of described 15th N-type MOS transistor (N15) and described 16th N-type MOS transistor (N16) connects and ground connection；
The drain electrode of source electrode, the source electrode of the 12nd N-type MOS transistor (N12) and the described 14th N-type MOS transistor (N14) of described 11st N-type MOS transistor (N11) connects；
The drain electrode of the drain electrode of the first N-type MOS transistor (N1), the grid of the first N-type MOS transistor (N1), the grid of the 3rd N-type MOS transistor (N3) and the 4th N-type MOS transistor (N4) connects；
The drain electrode of the drain electrode of the second N-type MOS transistor (N2), the grid of the second N-type MOS transistor (N2), the grid of the 4th N-type MOS transistor (N4) and the 3rd N-type MOS transistor (N3) connects；
The drain electrode of the source electrode of the 3rd N-type MOS transistor (N3), the source electrode of the 4th N-type MOS transistor (N4) and the 6th N-type MOS transistor (N6) is connected；
The drain electrode of the source electrode of the first N-type MOS transistor (N1), the source electrode of the second N-type MOS transistor (N2) and the 5th N-type MOS transistor (N5) connects；
The source electrode of the 5th N-type MOS transistor (N5) and the source electrode of the 6th N-type MOS transistor (N6) connect and ground connection；
The grid of described 7th N-type MOS transistor (N7) and the grid of described 8th N-type MOS transistor (N8) are respectively as normal phase input end (Vip) and negative-phase input (Vin)；The drain electrode of described first p-type MOS transistor (P1) and the drain electrode of described second p-type MOS transistor (P2) export (Vop) respectively as anti-phase output (Von) and positive；
Described cross-couplings temperature-compensation circuit includes the 3rd p-type MOS transistor (P3), the 4th p-type MOS transistor (P4), the 17th N-type MOS transistor (N17), the 18th N-type MOS transistor (N18), the 19th N-type MOS transistor (N19) and the first resistance (R1)；
The drain electrode of the grid of described 3rd p-type MOS transistor (P3), the grid of described 4th p-type MOS transistor (P4) and described 17th N-type MOS transistor (N17) connects；
The grid of the source electrode of described 17th N-type MOS transistor (N17), the grid of described 18th N-type MOS transistor (N18), the drain electrode of described 18th N-type MOS transistor (N18) and described 19th N-type MOS transistor (N19) connects；
The grid of the drain electrode of described 4th p-type MOS transistor (P4), the drain electrode of described 19th N-type MOS transistor (N19), the drain electrode of described 17th N-type MOS transistor (N17) and described 17th N-type MOS transistor (N17) connects；
The drain electrode of the drain electrode of described 3rd p-type MOS transistor (P3), the grid of described 18th N-type MOS transistor (N18) and described 18th N-type MOS transistor (N18) connects；
The source electrode of described 18th N-type MOS transistor (N18) and described 19th N-type MOS transistor (N19) source electrode are connected by described first resistance (R1), the source ground of described 18th N-type MOS transistor (N18)；
The grid of described 18th N-type MOS transistor (N18) is connected with the grid of described 6th N-type MOS transistor (N6).
null2. the low-temperature coefficient variable gain amplifier promoting gain variation range as claimed in claim 1，It is characterized in that，Described gain control circuit includes the 5th p-type MOS transistor (P5)、6th p-type MOS transistor (P6)、7th p-type MOS transistor (P7)、8th p-type MOS transistor (P8)、9th p-type MOS transistor (P9)、Tenth p-type MOS transistor (P10)、20th N-type MOS transistor (N20)、21st N-type MOS transistor (N21)、22nd N-type MOS transistor (N22)、23rd N-type MOS transistor (N23)、24th N-type MOS transistor (N24)、25th N-type MOS transistor (N25)、26th N-type MOS transistor (N26) and the second resistance (R2)，
The source electrode of source electrode, the source electrode of the 6th p-type MOS transistor (P6), the source electrode of the 7th p-type MOS transistor (P7), the source electrode of the 8th p-type MOS transistor (P8), the source electrode of the 9th p-type MOS transistor (P9) and the tenth p-type MOS transistor (P10) of described 5th p-type MOS transistor (P5) connects；
The drain electrode of the drain electrode of described 5th p-type MOS transistor (P5), the drain electrode of described 6th p-type MOS transistor (P6), the grid of described 22nd N-type MOS transistor (N22) and described 22nd N-type MOS transistor (N22) connects；
The grid of described 7th p-type MOS transistor (P7) and the grid of described 8th p-type MOS transistor (P8) connect；
The grid of the drain electrode of described 8th p-type MOS transistor (P8), the drain electrode of described 23rd N-type MOS transistor (N23) and described 23rd N-type MOS transistor (N23) connects；
The source electrode of the drain electrode of described 9th p-type MOS transistor (P9), the drain electrode of described 24th N-type MOS transistor (N24), the grid of described 21st N-type MOS transistor (N21), the grid of described 24th N-type MOS transistor (N24), the grid of described 25th N-type MOS transistor (N25) and described 26th N-type MOS transistor (N26) connects；
The grid of described 9th p-type MOS transistor (P9), the grid of described tenth p-type MOS transistor (P10), the drain electrode of described tenth p-type MOS transistor (P10), the grid of described 26th N-type MOS transistor (N26), the drain electrode of described 26th N-type MOS transistor (N26), the drain electrode of described 25th N-type MOS transistor (N25) and the grid of described 6th p-type MOS transistor (P6) connect；
The source electrode of the source electrode of described 20th N-type MOS transistor (N20), the source electrode of described 21st N-type MOS transistor (N21), the source electrode of described 22nd N-type MOS transistor (N22), the source electrode of described 23rd N-type MOS transistor (N23), the source electrode of described 24th N-type MOS transistor (N24) and described 25th N-type MOS transistor (N25) is all connected with and ground connection；
The drain electrode of the drain electrode of described 20th N-type MOS transistor (N20), the drain electrode of described 21st N-type MOS transistor (N21) and described 7th p-type MOS transistor (P7) connects；
It is provided with described second resistance (R2) between source electrode and the earth point of described 25th N-type MOS transistor (N25).
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| CN106059512A (en) * | 2016-05-26 | 2016-10-26 | 华南理工大学 | Novel low-complexity broadband variable gain amplifier |
| CN108920779B (en) * | 2018-06-13 | 2022-07-29 | 东南大学 | Regeneration-based variable gain amplifier structure and control method thereof |
| CN110504933A (en) * | 2019-08-07 | 2019-11-26 | 宁波大学 | A kind of highly linear variable gain amplifier |
| CN110995169B (en) * | 2019-11-29 | 2021-08-06 | 浙江大学 | On-chip variable gain temperature compensation amplifier |
| CN112039444B (en) * | 2020-11-04 | 2021-02-19 | 成都铱通科技有限公司 | Gain amplifier for improving variation range of positive temperature coefficient |
| CN116137512A (en) * | 2021-11-17 | 2023-05-19 | 深圳市中兴微电子技术有限公司 | Variable gain amplifier and transmitting device |
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