CN103904084A - Multilayer connection structure and making method - Google Patents
Multilayer connection structure and making method Download PDFInfo
- Publication number
- CN103904084A CN103904084A CN201410153001.XA CN201410153001A CN103904084A CN 103904084 A CN103904084 A CN 103904084A CN 201410153001 A CN201410153001 A CN 201410153001A CN 103904084 A CN103904084 A CN 103904084A
- Authority
- CN
- China
- Prior art keywords
- contact
- layer
- opening
- contact layer
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2<SP>N</SP> contact levels. Each mask is used to etch effectively half of the contact openings. When N is 3, a first mask etches one contact level, a second mask etches two contact levels, and a third mask etches four contact levels. A dielectric layer may be formed on the sidewalls of the contact openings. Electrical conductors may be formed through the contact openings with the dielectric layers electrically insulating the electrical conductors from the sidewalls.
Description
The application is divisional application, the application number of female case: 201110182911.7, and the applying date: on June 27th, 2011, title: 3-D stacks integrated circuit (IC) apparatus and manufacture method thereof.
Technical field
The present invention relates to a kind of high density integrated circuit device haply, and relates to especially a kind of interconnection structure for multi-layer three-dimension laminated device.
Background technology
In the manufacture of high density memory devices, on integrated circuit, the data volume of per unit area can be as the factor of a key.Therefore,, in the time that the critical size of storage arrangement reaches the limit of photoetching technique, in order to reach the cost of higher storage density and lower every bit, be suggested for the technology of lamination multilayered memory unit (memory cell).
For example, in the people's such as Lai " A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory, " IEEE Int ' l Electron Devices Meeting, 11-13Dec.2006, and in the people such as Jung " Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond30nm Node ", IEEE Int ' l Electron Devices Meeting, 11-13Dec.2006 document in, thin-film transistor technologies is applied to charge capturing memory.
In addition, in the people such as Johnson " 512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory Cells ", IEEE J.of Solid-State Circuits, vol.38, no.11, in the document of Nov.2003, crosspoint array (cross-point array) technology has been applied to anti-fuse memory (anti-fuse memory).Meanwhile, be the United States Patent (USP) case the 7th of " Three-Dimensional Memory " with reference to the title of Cleeves, 081, No. 377 case.
In charge capturing memory technology, provide vertical anti-and (NAND) another structure of unit be described in the people such as Kim " Novel3-D Structure for Ultra-High Density Flash Memory with VRAT and PIPE ", 2008Symposium on VLSI Technology Digest of Technical Papers; 17-19June2008; In the document of pages122-123.
In 3-D stacks storage arrangement, conductive interconnection through memory cell compared with upper strata, in order to memory cell is coupled to decoding circuit and analogous circuit thereof compared with lower floor.The cost of carrying out interconnection can increase along with the quantity of required lithography step.A kind of method of the quantity that reduces lithography step be described in the people's such as Tanaka " Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory ", 2007Symposium on VLSI Technology Digest of Technical Papers; 12-14June2007, in the document of pages:14-15.
But one of them shortcoming of known 3-D stacks storage arrangement is conventionally to use independently mask for each contact layer.Therefore, if there are for example 20 contact layers, conventionally need 20 different masks, each contact layer need to be for the generation of the mask of this layer, and for the etch step of this layer.
Summary of the invention
In view of this, one of object of the present invention is to provide a kind of method, be used in the 3-D stacks integrated circuit (IC) apparatus that an interconnect area has a lamination of at least four contact layers, in order to produce multiple interconnection contact areas, multiple landing region alignment of the plurality of interconnection contact area and the plurality of contact layer and expose the plurality of landing region in the plurality of contact layer.Respectively this contact layer comprises a conductive layer and an insulating barrier.At least a portion that is arranged at any upper strata in this interconnect area is removed, to expose one first contact layer and to produce for the each contact openings of this contact layer.Select one group of N etching mask, this lamination place that is used to the plurality of contact layer produces multiple interconnection contact area layers, and N at least equals 2 integer.Use a plurality of N etching mask extremely to reach with the plurality of contact openings of etching and comprise a Nth power the plurality of contact layer of 2.The plurality of N mask uses step to comprise to use one first mask with this contact layer of the plurality of contact openings etching for half effectively and uses one second mask, with for two the plurality of contact layers of the plurality of contact openings etching of half effectively.This removes, this selection and this use step are to carry out so that the plurality of contact openings extends to a Nth power contact layer of the plurality of 2.Form multiple electric conductors and pass the plurality of contact openings to be contacted with the plurality of landing region of the plurality of contact layer.In some examples, this removes step is to carry out with an extra mask.In some examples, this first mask uses step to comprise to use this first to be masked in every this contact layer of this contact openings etching, and this second mask uses step to comprise to use this second to be masked in the 3rd at least one group of first to fourth the plurality of contact openings and two the plurality of contact layers of the 4th contact openings etching.In some examples, the plurality of N mask uses step more to comprise to use one the 3rd mask with for four the plurality of contact layers of the plurality of contact openings etching of half effectively, and uses one the 4th mask with for eight the plurality of contact layers of the plurality of contact openings etching of half effectively.In some examples, the 3rd mask uses step to comprise to use the 3rd to be masked at least one group first to four the plurality of contact layers of the 5th to the 8th contact openings etching in the 8th the plurality of contact openings, and the 4th mask uses step to comprise to use the 4th to be masked at least one group of eight the plurality of contact layers of the 9th to the 16 contact openings etching in the first to the 16 the plurality of contact openings.In some examples, produce a ground connection contact openings through the plurality of contact layer, and form a grounded conductive body through this ground connection contact openings, with in electrical contact with the multiple the plurality of conductive layer of the plurality of contact layer.In some examples, this ground connection contact openings has a ground connection contact openings sidewall, and before this grounded conductive body forms step, remove in the part of the insulating barrier of this ground connection contact openings sidewall, so this grounded conductive body strengthens in electrical contact between the multiple the plurality of conductive layer of this grounded conductive body and the plurality of contact layer.
Two of object of the present invention is to provide a kind of method, and for a 3-D stacks integrated circuit (IC) apparatus, the method provides multiple landing region at multiple lamination places that are electrically connected to the multiple contact layers that are positioned at this interconnect area.This integrated circuit (IC) apparatus is a type that comprises an interconnect area.This interconnect area comprises a upper strata, has the lamination of the plurality of contact layer under this upper strata.Respectively this contact layer comprises a conductive layer and an insulating barrier.At least a portion that is arranged at any upper strata in this interconnect area is removed, to expose one first contact layer and to produce for the each contact openings of this contact layer.Select one group of N etching mask to produce multiple interconnection contact area layers in this lamination place of the plurality of contact layer, N at least equals 2 integer.Use a plurality of N etching mask extremely to reach with the plurality of contact openings of etching and comprise a Nth power the plurality of contact layer of 2.The plurality of N mask uses step to comprise to use one first mask with for this contact layer of the plurality of contact openings etching of half effectively, and uses one second mask with for two the plurality of contact layers of the plurality of contact openings etching of half effectively.This removes, this selection and this use step is performed so that the plurality of contact openings extends to a Nth power contact layer of the plurality of 2.Form a dielectric layer on multiple sidewalls.Form multiple electric conductors and pass the plurality of contact openings to the plurality of landing region that is positioned at the plurality of contact layer, the plurality of electric conductor is electrically insulated from the plurality of sidewall by the plurality of dielectric layer.In some examples, produce a ground connection contact openings through the plurality of contact layer, and form a grounded conductive body through this ground connection contact openings, with in electrical contact with the multiple the plurality of conductive layer of the plurality of contact layer.In some examples, this ground connection contact openings has a ground connection contact openings sidewall, and before this grounded conductive body forms step, remove in the part of the plurality of insulating barrier of this ground connection contact openings sidewall, make to be exposed adjacent to the part of multiple the plurality of conductive layers of this ground connection contact openings, make this grounded conductive body strengthen in electrical contact with multiple the plurality of conductive layers.
First example of one 3-D stacks integrated circuit (IC) apparatus comprises at least first, second, third and a lamination of the 4th contact layer, is positioned at an interconnect area.Respectively this contact layer comprises a conductive layer and an insulating barrier.First, second, third and the 4th electric conductor through the part of the lamination of this contact layer.This first, second, third and the 4th electric conductor respectively with this first, second, third and the 4th conductive layer in electrical contact.One dielectric sidewall spacer is around changed around this second, third and the 4th electric conductor so that this second, third and the 4th electric conductor only in electrical contact separately this second, third and the 4th conductive layer.In some examples, this first, second, third and the 4th electric conductor there is a constant spacing.In some examples, this first, second, third and the position of the 4th electric conductor be to be determined by a common mask.In some examples, this stacked integrated circuit device more comprises the part of a grounded conductive body through this lamination of the plurality of contact layer, this grounded conductive body in electrical contact respectively this first, second, third and the 4th conductive layer.
Second example of one 3-D stacks integrated circuit (IC) apparatus comprises at least first, second, third and a lamination of the 4th contact layer, is positioned at an interconnect area.Respectively this contact layer comprises a conductive layer and an insulating barrier.First, second, third and the 4th electric conductor through the part of this lamination of the plurality of contact layer.This first, second, third and the 4th electric conductor respectively with this first, second, third and the 4th conductive layer in electrical contact.This first, second, third and the 4th electric conductor there is a constant spacing.In some examples, this first, second, third and the position of the 4th electric conductor be to be determined by a common mask.
The 3rd example of one 3-D stacks integrated circuit (IC) apparatus comprises at least first, second, third and a lamination of the 4th contact layer, is positioned at an interconnect area.Respectively this contact layer comprises a conductive layer and an insulating barrier.First, second, third and the 4th electric conductor through the part of this lamination of the plurality of contact layer.This first, second, third and the 4th electric conductor respectively with this first, second, third and the 4th conductive layer in electrical contact.One dielectric sidewall spacer is around changed around this second, third and the 4th electric conductor so that this second, third and the 4th electric conductor only in electrical contact separately this second, third and the 4th conductive layer.One grounded conductive body through the part of this lamination of the plurality of contact layer and in electrical contact respectively this first, second, third and the 4th conductive layer.This first, second, third and the 4th electric conductor there is a constant spacing.This first, second, third and the position of the 4th electric conductor and this grounded conductive body be to be determined by a common mask.
Other aspects and advantages of the present invention can be with reference to the explanation of graphic, execution mode and the claim scope of enclosing.
Brief description of the drawings
Fig. 1 to Figure 16 and relevant description are taken from the U.S. patent application case the 12/579th of filing an application on October 14th, 2009, No. 192 cases, and its title is " 3D Integrated Circuit Layer Interconnect having the same assignee as this application ", be incorporated into this disclosure as reference.
Fig. 1 illustrates the cross section view of the device that comprises the three-dimensional structure with interconnection structure 190, and interconnection structure 190 has little floor space district, and wherein electric conductor 180 extends to the different contact layer 160-1 to 160-4 in device.
Fig. 2 A illustrates the plan view of contact layer 160-1, represents landing region.
Fig. 2 B illustrates the plan view of contact layer 160-2, represents the opening adjacent to landing region.
Fig. 2 C illustrates the plan view of contact layer 160-3, represents the opening adjacent to landing region.
Fig. 2 D illustrates the plan view of contact layer 160-4, represents the opening adjacent to landing region.
Fig. 3 A and Fig. 3 B illustrate each right-angle view of a part for 3-D stacks integrated circuit (IC) apparatus, and this 3-D stacks integrated circuit (IC) apparatus comprises the 3 dimension interconnection structures with little floor space.
Fig. 4 illustrates the top view of the layout of an embodiment of device, and this is installed in the surrounding on the dual-side of memory array and comprises interconnection structure.
Fig. 5 illustrates the top view of the layout of an embodiment of device, and this is installed in the surrounding on four sides of memory array and comprises interconnection structure.
Fig. 6 illustrates the schematic diagram of a part for the storage arrangement that comprises said interconnection structure.
Fig. 7 illustrates the simplification calcspar of integrated circuit (IC) apparatus, and integrated circuit (IC) apparatus comprises the 3 D memory array with interconnection structure described here.
Fig. 8 A, 8B, Fig. 8 C to Figure 15 illustrate the step of the manufacturing process of manufacturing interconnection structure described herein.
Figure 16 illustrates the plan view of the opening in mask, and this mask is with the mode vicissitudinous width of tool in a longitudinal direction of similar ladder, with the width of the variation in the landing region on accommodating layer.
Figure 17 to Figure 34 A illustrates structure and the method for the example of manufacturing another 3-D stacks integrated circuit (IC) apparatus.
Figure 17 and Figure 17 A are simplified side section and the top view of the interconnect area of another example of 3-D stacks integrated circuit (IC) apparatus.
Figure 18 and Figure 18 A illustrate through upper strata and form contact openings to expose the interconnect area after the upper strata conductive layer of the first contact layer.
Figure 19 and Figure 19 A illustrate in the structure that the first mask is positioned at Figure 18, and the first mask exposes and separates mouth.
Figure 20 and Figure 20 A illustrate the etching result of the single contact layer that is passed in the contact openings exposing.
Figure 21 and Figure 21 A illustrate removing of the first mask and the second mask and are formed at the structural result of Figure 20, and the first and second contact openings that come from left side number are covered by the second mask, and the third and fourth contact openings is exposed.
Figure 22 and Figure 22 A illustrate and are passed down through the 3rd and the etching result of two contact layers of the 4th contact openings.
Figure 23 and Figure 23 A illustrate Figure 22 and remove the structure after the second mask.
Figure 24 and Figure 24 A illustrate Figure 23 and form the structure after sidewall spacer at the sidewall of opening, with this, contact layer are electrically insulated to the inside of contact openings.
The structure that Figure 25 and Figure 25 A illustrate Figure 24 adds the cross section view of the contact openings of ground connection shown in Figure 25.Contact openings is covered by photoresist material, and ground connection contact openings exposes.
Figure 26 and Figure 26 A illustrate Figure 25 and pass the structure after three contact layers in etching, to expose the conductive layer of ground connection contact openings.
Figure 27 and Figure 27 A illustrate Figure 26 and remove the structure after photoresist material.
Figure 28 and Figure 28 A illustrate Figure 27 deposit spathic silicon layer and fill contact openings and ground connection contact openings and cover the structure behind upper strata, and this polysilicon layer in contact openings and ground connection contact openings forms respectively electric conductor and grounded conductive body.
Figure 29 and Figure 29 A illustrate Figure 28 and etch away the structure after the polysilicon layer that covers upper strata.
Figure 30 and Figure 30 A illustrate the result of upper surface down to the chemico-mechanical polishing of the electric charge capture layer of upper surface.
Figure 31 and Figure 31 A illustrate Figure 30 and deposit stop-layer and deposit subsequently the structure of interlayer dielectric oxide after on stop-layer.
Figure 32 and Figure 32 A illustrate Figure 31 and form contact openings extension and extend and pass through interlayer dielectric oxide and stop-layer to the structure after electric conductor and grounded conductive body, fill this through hole with electric conductor subsequently, to produce electric conductor and grounded conductive body, it has Part I extension and passes through contact layer, and upper strata is passed through in Part II extension.
Figure 33 is with one group of 16 contact openings of graphic drawing, represents not contact openings on the same group, is etched to four different degree of depth, to produce the structure of Figure 17.
Figure 34 and Figure 34 A are section and the plan view of a 3-D stacks integrated circuit (IC) apparatus.
Figure 35 illustrate Figure 33 with multi-form mask and etching program.
Figure 36 to Figure 38 is similar in appearance to Figure 35, but be respectively, etching order changes, mask order changes and sequence of positions changes.
Figure 39 is similar in appearance to Figure 35 but combine the change of Figure 36 to Figure 38.
[main element symbol description]
14,14.1,14.2,14.3,14.4: interconnection contact area
17: interconnect area
18.1,18.2,18.3,18.4,160-1,160-2,160-3,160-4: contact layer
19: silicon substrate
24: upper strata
25,26: dielectric layer
27,96: stop-layer
28: upper dielectric layer
29: end dielectric layer
33,33.1,33.2,33.3,33.4: contact openings
34,34.1,34.2,34.3,34.4: conductive layer
35: ground connection contact openings
36,36.1,36.2,36.3,36.4,164,165-1,165-2,165-3,166: insulating barrier
52,144,154: interlayer dielectric
54,54.1,54.2,54.3,54.4,180: electric conductor
55: grounded conductive body
57: the Part I of electric conductor 54
59: the Part II of electric conductor 54
61: dielectric sidewall spacer
88,92: photoresist material
89: the first masks
90: the second masks
93: electrically electric conducting material
95: electric charge capture layer
97: interlayer dielectric
100,300: 3-D stacks integrated circuit (IC) apparatus
110: memory array area
112: memory cell access layer
120: peripheral region
130: Semiconductor substrate
131a, 131b: level field effect transistor access device
132a, 132b: source area
134a, 134b: drain region
135a, 135b: trench isolation structures
140,140a, 140b, 94: word line (WL)
142a, 142b: contact plunger
146a, 146b: contact hole
150,150a, 150b: bit line (BL)
152a, 152b: contact pad
161-1a, 161-1b, 161-2a, 161-2b, 161-3a, 161-3b, 161-4: landing region
165: insulating material
170a, 170b: conduction stratum nucleare
171a: the first electrode column
171b: the second electrode column
172a, 172b: polysilicon cover layer
174a, 174b: anti-fuse materials layer
185: interconnection
190: interconnection structure
190-1,190-2,190-3,190-4: serial
192: the width of opening 810
194: the length of opening 810
200: the width of landing region 161-1a
201: the length of landing region 161-1a
202: the width of landing region 161-1b
203: the length of landing region 161-1b
204: the width of landing region 161-2a
205: the length of landing region 161-2a
206: the width of landing region 161-2b
207: the length of landing region 161-2b
214: the width of landing region 161-3a
215: the length of landing region 161-3a
216: the width of landing region 161-3b
217: the length of landing region 161-3b
224: the width of landing region 161-4
225: the length of landing region 161-4
250,255,260,265,270,275,810,1000,1010,1200,1210,1310,1320,1510: opening
251a, 251b, 256a, 256b, 261a, 261b, 271a, 271b, 276a, 276b: longitudinal side wall
252: the length of opening 250
253a, 253b, 258a, 258b, 263a, 263b, 268a, 268b, 273a, 273b, 278a, 278b: lateral sidewalls
254: the width of opening 250
257: the length of opening 255
259: the width of opening 255
262: the length of opening 260
264a, 264b: the width of opening 260
266a, 261a: outside longitudinal side wall
266b, 261b: inner side longitudinal side wall
267: the length of opening 265
269a, 269b: the width of opening 265
272: the length of opening 270
274a, 274b, 274c: the width of opening 270
277: the length of opening 275
279a, 279b, 279c: the width of opening 275
360: 3 D memory array
361: column decoder
363: row decoder
365,367: bus
366: sensing amplifier and data input structure
368: bias voltage arrangement supply voltage
369: bias voltage arranges state machine
371: Data In-Line
372: DOL Data Output Line
374: other circuit
544-1,544-2,544-3,544-4: memory component
546: plane decoder
547: ground connection
548: programmable element
549: rectifier
800: the first masks
900: the second masks
The length of 910: the second masks
1002: the length of opening 1000
1004: the width of opening 1000,1010
1012: the length of opening 1010
1100,1300: through reducing the mask of length
1110: the length of mask 1100
1202: the length of opening 1200
1204: the width of opening 1200,1210
1212: the length of opening 1210
1305: the length of mask 1300
1312: the length of opening 1310
1314: the width of opening 1310
1322: the length of opening 1320
1324: the width of opening 1320
1400: insulation filling material
Embodiment
Fig. 1 illustrates the cross section view of the device that comprises the three-dimensional structure with interconnection structure 190, and interconnection structure 190 has little floor space (footprint), and wherein electric conductor 180 extends to contact layer 160-1 to 160-4 different in device.Shown in example in, indicate four contact layer 160-1 to 160-4.Generally speaking, little interconnection structure 190 described here can be to there is contact layer 0 to N N be at least 2 structure and carry out.
Within electric conductor 180 is arranged in interconnection structure 190, to contact the landing region on different contact layer 160-1 to 160-4.As described in more detail below, extend through the opening of the layer that is arranged at top for the electric conductor 180 of each certain layer, to contact landing region 161-1a, 161-1b, 161-2a, 161-2b, 161-3a, 161-3b, 161-4.In this example, electric conductor 180 is the interconnection 185 for contact layer 160-1 to 160-4 being coupled to conductor layer, and conductor layer is arranged at the top of contact layer 160-1 to 160-4.
Landing region is the part of the contact layer 160-1 to 160-4 for contacting with electric conductor 180.The size in landing region is even as big as providing space to electric conductor 180, make electric conductor 180 sufficiently the conduction landing region in the landing region of different contact layer 160-1 to 160-4 is coupled to the interconnection 185 above being arranged at, for example solve in different layers electric conductor 180 and the problem that do not line up between the opening above one deck wherein that is arranged at for the region of landing simultaneously.
Therefore the size in landing region depends on several factors, the size that comprises used electric conductor and quantity, and will change to some extent along with each embodiment.In addition,, for each landing region, the quantity of electric conductor 180 can be different.
In shown in example in, contact layer 160-1 to 160-4 is made up of the plane conductive layer separately of material, this material, for example through the polysilicon of doping, is wherein separated the insulating material 165 of contact layer 160-1 to 160-4 in addition.Or contact layer 160-1 to 160-4 needs not be the material layer of flat stack, be the material layer that can change to some extent along vertical dimensions on the contrary.
Contacting the electric conductor 180 of different contact layer 160-1 to 160-4, is to arrange with the section bearing of trend along as shown in Figure 1A.Arrange by this of the electric conductor 180 of the different contact layer 160-1 to 160-4 of contact direction defining, referred to here as " longitudinally " direction." laterally " direction is perpendicular to longitudinal direction, and for the paper feed face of section as shown in Figure 1A and go out paper direction.Longitudinally and horizontal direction the two be all considered to " lateral dimensions (lateral dimensions) ", mean the direction in the 2 dimensional region of plan view of contact layer 160-1 to 160-4." length " of structure or be characterized as its length on longitudinal direction, and " width " of structure is that it is in width in a lateral direction.
Contact layer 160-1 is minimum layer in multiple contact layer 160-1 to 160-1.Contact layer 160-1 is positioned on insulating barrier 164.
Contact layer 160-1 comprises first and second landing region 161-1a, the 161-1b in order to contact with electric conductor 180.
In Fig. 1, contact layer 160-1 comprises two landing region 161-1a, 161-1b on the relative end of interconnection structure 190.At some, in other embodiment, one of them is omitted landing region 161-1a, 161-1b.
Fig. 2 A illustrates the plan view of a part of contact layer 160-1, comprises landing region 161-1a, 161-1b in the floor space of interconnection structure 190.The floor space of interconnection structure 190 can approach the width for the clear size of opening of electric conductor, and has the length longer than this width.As shown in Figure 2 A, landing region 161-1a transversely direction has width 200, and has in a longitudinal direction length 201.Landing region 161-1b transversely direction has width 202, and has in a longitudinal direction length 203.In the embodiment of Fig. 2 A, landing region 161-1a, 161-1b respectively have rectangular section.In embodiment, landing region 161-1a, 161-1b respectively can have circle, ellipse, square, rectangle or some difform sections.
Because contact layer 160-1 is minimum contact layer, electric conductor 180 does not need through contact layer 160-1 to the layer that is arranged at below.Therefore,, in this example, contact layer 160-1 does not have opening within interconnection structure 190.
Refer back to Fig. 1, contact layer 160-2 is arranged at the top of contact layer 160-1.The opening 250 of the top that contact layer 160-2 comprises the landing region 161-1a being arranged on contact layer 160-1.Opening 250 has the longitudinal side wall 251a in distally and the longitudinal side wall 251b of nearside, defines the length 252 of opening 250.The length 252 of opening 250 is at least equally long with the length 201 of landing region 161-1a that is arranged at below, makes can pass contact layer 160-2 for the electric conductor 180 of the region 161-1a that lands.
Contact layer 160-2 also comprises the opening 255 of the top that is arranged at landing region 161-1b.Opening 255 has longitudinal side wall 256a distally and nearside, 256b, defines the length 257 of opening 255.The length 257 of opening 255 is at least equally long with the length 203 of landing region 161-1b that is arranged at below, makes can pass contact layer 160-2 for the electric conductor 180 of the region 161-1b that lands.
Contact layer 160-2 also comprises first and second landing region 161-2a, 161-2b, and it is respectively adjacent to opening 250,255.First and second landing region 161-2a, 161-2b are the part of the contact layer 160-2 for contacting with electric conductor 180.
Fig. 2 B illustrates the plan view of a part of contact layer 160-2, comprises first and second landing region 161-2a, 161-2b and opening 250,255 within interconnection structure 190.
As shown in Figure 2 B, opening 250 has longitudinal side wall 251a, 251b, defines the length 252 of opening 250, and has lateral sidewalls 253a, 253b, defines the width 254 of opening 250.Width 254 is at least equally wide with the width 200 of landing region 161-1a that is arranged at below, makes electric conductor 180 can pass opening 250.
In the plan view of Fig. 2 B, opening 250,255 respectively has rectangular section.In embodiment, opening 250,255 depends on the shape of the mask that forms these a little openings, and opening 250,255 respectively can have circle, ellipse, square, rectangle or some difform sections.
As shown in Figure 2 B, region 161-2a is adjacent to opening 250 in landing, and in thering is in a lateral direction width 204, and on longitudinal direction, there is length 205.Region 161-2b is adjacent to opening 255 in landing, and in thering is in a lateral direction width 206, and on longitudinal direction, there is length 207.
Refer back to Fig. 1, contact layer 160-3 is arranged at the top of contact layer 160-2.The opening 260 of the top that contact layer 160-3 comprises the landing region 161-2a on landing region 161-1a and the contact layer 160-2 being arranged on contact layer 160-1.Opening 260 has longitudinal side wall 261a distally and nearside, 261b, defines the length 262 of opening 260.The length 262 of opening 260 is at least equally long with the summation that is arranged at the landing region 161-1a of below and the length 201 and 205 of 161-2a, makes can pass contact layer 160-3 for the electric conductor 180 of land region 161-1a and 161-2a.
As shown in Figure 1, the distally longitudinal side wall 261a of opening 260 is vertically aligned in the distally longitudinal side wall 251a of the opening 250 that is arranged at below.Manufacturing in greater detail below in embodiment, opening in the single etching mask of energy use and the extra mask on an opening being formed in this single etching mask, and for the process of this extra mask of etching, form opening, and do not need crucial alignment step, thereby cause having distally longitudinal side wall (261a, 251a ...) opening be along the periphery of the single etching mask through vertical alignment and form.
Contact layer 160-3 also comprises the opening 265 of the top of the landing region 161-2b on landing region 161-1b and the contact layer 160-2 being arranged on contact layer 160-1.Opening 265 has longitudinal side wall 266a, the 266b of outside and inner side, defines the length 267 of opening 265.The outside longitudinal side wall 266a of opening 265 is vertically aligned in the outside longitudinal side wall 256a of the opening 255 that is arranged at below.
The length 267 of opening 265 is at least equally long with the summation that is arranged at the landing region 161-1b of below and the length 203 and 207 of 161-2b, makes can pass contact layer 160-3 for the electric conductor 180 of land region 161-1b and 161-2b.
Contact layer 160-3 also comprises first and second landing region 161-3a, 161-3b, and it is respectively adjacent to opening 260,265.First and second landing region 161-3a, 161-3b are the part of the contact layer 160-3 for contacting with electric conductor 180.
Fig. 2 C illustrates the plan view of a part of contact layer 160-3, comprises first and second landing region 161-3a, 161-3b and opening 260,265 within interconnection structure 190.
As shown in Figure 2 C, opening 260 has longitudinal side wall 261a, the 261b of outside and inner side, defines the length 262 of opening 260, and has lateral sidewalls 263a, 263b, defines width 264a, the 264b of opening 260.Width 264a is at least equally wide with the width 200 of landing region 161-1a that is arranged at below, and width 264b is at least equally wide with the width 204 of landing region 161-2a that is arranged at below, makes electric conductor 180 can pass opening 260.
In an illustrated embodiment, width 264a and 264b are identical in fact.Or in order to hold the landing region with different width, width 264a and 264b can be difference.
As shown in Figure 2 C, region 161-3a is adjacent to opening 260 in landing, and in thering is in a lateral direction width 214, and on longitudinal direction, there is length 215.Region 161-3b is adjacent to opening 265 in landing, and in thering is in a lateral direction width 216, and on longitudinal direction, there is length 217.
Refer back to Fig. 1, contact layer 160-4 is arranged at the top of contact layer 160-3.The opening 270 of the top that contact layer 160-4 comprises the landing region 161-2a on landing region 161-1a, the contact layer 160-2 being arranged on contact layer 160-1 and the landing region 161-3a on contact layer 160-3.Opening 270 has longitudinal side wall 271a, 271b, defines the length 272 of opening 270.The length 272 of opening 270 is at least equally long with the summation that is arranged at landing region 161-1a, the 161-2a of below and the length 201,205 and 215 of 161-3a, makes can pass contact layer 160-4 for the electric conductor 180 of land region 161-1a, 161-2a and 161-3a.As shown in Figure 1, the longitudinal side wall 271a of opening 270 is vertically aligned in the longitudinal side wall 261a of the opening 260 that is arranged at below.
Contact layer 160-4 also comprises the opening 275 of the top of the landing region 161-2b on landing region 161-1b, the contact layer 160-2 being arranged on contact layer 160-1 and the landing region 161-3b on contact layer 160-3.Opening 275 has longitudinal side wall 276a, 276b, defines the length 277 of opening 275.The longitudinal side wall 276a of opening 275 is vertically aligned in the longitudinal side wall 266a of the opening 265 that is arranged at below.
The length 277 of opening 275 is at least equally long with the summation that is arranged at landing region 161-1b, the 161-2b of below and the length 203,207 and 217 of 161-3b, makes can pass contact layer 160-4 for the electric conductor 180 of land region 161-1b, 161-2b and 161-3b.
Contact layer 160-4 is also contained in the landing region 161-4 between opening 270,275.Landing region 161-4 is the part of the contact layer 160-4 for contacting with electric conductor 180.In Fig. 1, contact layer 160-4 has a landing region 161-4.Or contact layer 160-4 can comprise more than one landing region.
Fig. 2 D illustrates the plan view of a part of contact layer 160-4, comprises landing region 161-4a and opening 270,275 within interconnection structure 190.
As shown in Figure 2 D, opening 270 has longitudinal side wall 271a, 271b, defines the length 272 of opening 270, and has lateral sidewalls 273a, 273b, defines width 274a, 274b, the 274c of opening 270. Width 274a, 274b, 274c are at least equally wide with landing region 161-1a, the 161-2a and the width 200,204 and 214 of 161-3a that are arranged at below, so that electric conductor 180 can pass opening 270.
As shown in Figure 2 D, region 161-4 is between opening 270,275 in landing, and in thering is in a lateral direction width 224, and on longitudinal direction, there is length 225.
Refer back to Fig. 1, distally longitudinal side wall 271a, the 261a of opening 270,260 and 250 and 251a are vertically alignment, so that the deviation of opening 270,260 and 250 in length is to result from the horizontal-shift of sidewall 271b, 261b and 251b.Use at this, element or feature " vertically alignment " be flush in fact (flush) in horizontal and the two all vertical imaginary plane of longitudinal direction.Term used herein " flushes in fact " the manufacture allowable limit (tolerance) in the formation that is intended to be covered by opening, wherein the formation of this opening is the opening using in single etching mask, and uses the multiple etching processing of the variation of the flatness that can cause sidewall.
As shown in Figure 1, longitudinal side wall 276a, the 266a of opening 275,265 and 255 and 256a are vertically alignment.
Similarly, also vertically alignment of the lateral sidewalls of the opening in layer.With reference to Fig. 2 A to Fig. 2 D, lateral sidewalls 273a, the 263a of opening 270,260 and 250 and 253a are vertically alignment.In addition, lateral sidewalls 273b, 263b and 253b are vertically alignment.For opening 275,265 and 255, longitudinal side wall 276a, 266a and 256a are vertically alignment, and lateral sidewalls 278b, 268b and 258b are for vertically aliging.
In an illustrated embodiment, the opening in different contact layer 160-1 to 160-4 has identical in fact width in a lateral direction.Or in order to hold the landing region with different width, the width of opening can change in a longitudinal direction to some extent, for example, with similar stair-stepping form.
For carrying out this technology of interconnection structure 190 as described herein, compared to the technology of existing skill, can reduce significantly for contact needed area or floor space (footprint) with multiple contact layer 160-1 to 160-4.Therefore, in different contact layer 160-1 to 160-4, can there is more space to carry out memory circuitry.Compared to the technology of existing skill, so can in upper strata, allow the cost of higher storage density and less every bit.
In the profile of Fig. 1, the opening in interconnection structure 190 causes having similar ladder pattern on the both sides of all layers landing region 161-4 on contact layer 160-4.That is two openings in each layer, are symmetrical in one all perpendicular to the axle of longitudinal direction and horizontal direction, and two landing regions of each layer are also symmetrical in this axle.As said, term " symmetry " intention is covered by the manufacture allowable limit in the formation of opening, and wherein the formation of this opening is the opening using in single etching mask, and uses the multiple etching processing of the variation of the yardstick that can cause opening.
In other embodiments, each layer comprises single opening and single landing region, and these a little layers only have similar ladder pattern on one-sided.
In shown in example in, represent four contact layer 160-1 to 160-4.More generally, little interconnection structure described here can be rendered in layer 0 to N, and wherein N is at least 2.Generally speaking, layer (i) is arranged at the top of layer (i-1), wherein (i) equals 1 to N, and layer (i) has the opening (i) adjacent to landing region (i) on layer (i).Opening (i) extends the top in the landing region (i-1) on layer (i-1), and in the time that (i) is greater than 1, opening (i) extends the top of the opening (i-1) that layer (i-1) is adjacent.Opening (i) has the distally longitudinal side wall aliging with the distally longitudinal side wall of the opening (i-1) in layer (i), and has the nearside longitudinal side wall of the length of definition opening (i).If yes, at least to add the length of upper shed (i-1) equally long with the length in landing region (i-1) for the length of opening (i).In the time that (i) is greater than 1, opening (i) has the lateral sidewalls of aliging with the lateral sidewalls of the opening (i-1) in layer (i-1), and the width of definition opening (i) is at least equally wide with the width in landing region (i-1).
The memory cell of other type and configuration can be used in other embodiment.The memory cell of spendable other type for example comprises dielectric medium charge-trapping and floating gate memory cell.For example, in the layer of another kind of device, may be realized as the planar storage cell array of being separated by insulating material, and form access device and access line by thin-film transistor or correlation technique in layer.In addition, the 3-D stacks integrated circuit (IC) apparatus that interconnection structure described here can other type is carried out, and wherein, it is favourable having the electric conductor that extends to the different layers in device in little floor space district.
Fig. 3 A illustrates the cutaway view of a part for 3-D stacks integrated circuit (IC) apparatus 100, and 3-D stacks integrated circuit (IC) apparatus 100 comprises memory array area 110 and has the peripheral region 120 of interconnection structure 190 described here.
In Fig. 3 A, the One Time Programmable multilayered memory unit in the 12/430th, No. 290 case of U.S. patent application case of Lung is carried out for as be described in to memory array area 110, this case by the assignee of the application's case owned together and at this as reference.Describe to can be practiced in three-dimensional interconnect structure described herein as the integrated circuit structure of representative at this.
In shown in example in, these a little contact layers are made up of the plane conductive layer separately of material, this material for example through doping polysilicon.Or these a little contact layers need not be the material layer of flat stack, be the material layer that can change to some extent along vertical dimensions on the contrary.
Insulating barrier 165-1 to 165-3 separates contact layer 160-1 to 160-4 one by one.Insulating barrier 166 is arranged at the top of contact layer 160-1 to 160-4 and insulating barrier 165-1 to 165-3.
Multiple electrode columns (electrode pillar) 171a, 171b are arranged on the top of memory cell access layer 112, and extend through this little contact layers.In this figure, the first electrode column 171a comprises central authorities conductions stratum nucleare 170a, and this conduction stratum nucleare 170a is for example by tungsten or other suitable electrode material made, and by polysilicon cover layer 172a institute around.Anti-fuse materials layer 174a, or other programmable storage material layer are to be formed between polysilicon cover layer 172a and multiple contact layer 160-1 to 160-4.In this example, contact layer 160-1 to 160-4 comprises the N-shaped polysilicon of relative altitude doping, and polysilicon cover layer 172a comprises the p-type polysilicon of relatively slight doping.Preferably, the thickness of polysilicon cover layer 172a is greater than the degree of depth of the exhaustion region being formed by p-n junction.The degree of depth of exhaustion region is partly by being used to form the N-shaped of exhaustion region and the relative doping content of p-type polysilicon determines.Contact layer 160-1 to 160-4 and cover layer 172a also can carry out with amorphous silicon.In addition, also can use other semiconductor material.
The first electrode column 171a is coupled to contact pad 152a.The second electrode column 171b comprises conduction stratum nucleare 170b, polysilicon cover layer 172b and anti-fuse materials layer 174b, is coupled to contact pad 152b.
Interface area between multiple contact layer 160-1 to 160-4 and electrode column 171a, 171b, comprises memory component, and this memory component comprises the programmable element with rectifier series winding, will under explain in detail.
In primordial condition, the anti-fuse materials layer 174a of electrode column 171a has high resistance, and this anti-fuse materials layer 174a can be silicon dioxide, silicon oxynitride or other Si oxide.Can use other as the anti-fuse materials of silicon nitride.In by applying after suitable voltage programmes to word line 140, bit line 150 and multiple contact layer 160-1 to 160-4, anti-fuse materials layer 174a is breakdown, and active area in the anti-fuse materials of an adjacent respective layer presents low resistance state.
As shown in Figure 3A, multiple conductive layers of contact layer 160-1 to 160-4 extend into peripheral region 120, are to support in order to be connected to circuit and the electric conductor 180 of multiple contact layer 160-1 to 160-4 herein.Various devices are rendered in peripheral region 120, to support decoding logic circuit and other circuit on integrated circuit 100.
Within electric conductor 180 is arranged in interconnection structure 190, to contact the landing region on different contact layer 160-1 to 160-4.As discussed in more detail below, extend through the opening of the layer that is arranged at top for the electric conductor 180 of each specific contact layer 160-1 to 160-4, to the conductor layer that comprises conductive interconnection 185.Conductive interconnection 185 is provided as the interconnection between the decoding circuit in contact layer 160-1 to 160-4 and peripheral region 120.
As represented with dotted line in Fig. 3 A, the electric conductor 180 that contacts different contact layer 160-1 to 160-4 is arranged as into the section extending in a longitudinal direction for shown in Fig. 3 A.
Fig. 3 B illustrate interconnection structure 190 through Fig. 3 A with longitudinal direction the cross section view along Fig. 3 B-Fig. 3 B line, represent the view of interconnection structure similar to Figure 1 190.As visible in Fig. 3 B, extend through the opening of the layer that is arranged at top for the electric conductor 180 of each specific contact layer, to contact landing region.
In shown in example in, represent four contact layer 160-1 to 160-4.More generally, little interconnection structure described here can be rendered in layer 0 to N, and wherein N is at least 2.
The memory cell of other type and configuration can be used in other embodiment.For example, in the layer of another kind of device, may be realized as the planar storage cell array of being separated by insulating material, and form access device and access line by thin-film transistor or correlation technique in layer.In addition, the 3-D stacks integrated circuit (IC) apparatus that interconnection structure described here can other type is carried out, and wherein, it is favourable having the electric conductor that extends to the different layers in device in little floor space district.
In Fig. 3 A and Fig. 3 B, represent single interconnection structure 190.Can arrange multiple interconnection structures by the diverse location in device, for example, around memory array area 110, so that average distributing electric power to be provided.Fig. 4 illustrates the top view of the layout of an embodiment of device 100, and device 100 interconnection structures that comprise dual serial are included in peripheral region 120Zhong region 190-1 on the side separately of array and the serial of region 190-2.Fig. 5 illustrates the top view of the layout of an embodiment, and device 100 interconnection structures that comprise four serials, are included in serial 190-1,190-2,190-3 and 190-4 in the peripheral region 120 on all four sides of array.For example, array sizes comprises 1000 row (column) and 1000 row (row) unit, and there are 10 layers, characteristic size F defined word line width and bitline width, and the size in the landing region on its middle level is about F, the length of the shared area of a known interconnection structure is about 2F and is multiplied by the quantity of layer or is about 20F, and between every word line apart from being about 2F or wider, make the width of array be about 2000F.Therefore, so, shown in example, approximately 100 interconnection structures can be formed at as in the serial of the serial 190-3 along array-width, and also have similar amt can be formed at as in the serial of the serial 190-1 along array length
In another other other embodiment, except having interconnection structure in peripheral region 120, or as replacing, one or more interconnection structures can be practiced in memory array area 110.In addition, interconnection structure can diagonal or is extended with any other direction, but not is parallel to an edge of memory array area 110.
Fig. 6 illustrates the schematic diagram of a part for the storage arrangement that comprises said interconnection structure.The first electrode column 171a is coupled to access transistor 131a, and access transistor 131a is that use bit line 150a and word line 140a are selected.Multiple memory component 544-1 to 544-4 are connected to electrode column 171a.Each memory component comprises programmable element 548 and connects with rectifier 549.Even if anti-fuse materials layer is to be positioned at p-n junction, this arranged in series still represents the structure as shown in Fig. 3 A and Fig. 3 B.Programmable element 548 is by being generally used for indicating the symbol of anti-fuse to represent.But, it will be appreciated that programmable resistor material and the structure that also can use other type.
In addition, the rectifier 549 of carrying out by the p-n junction between conductive plane and polysilicon in electrode column, also can be replaced by other rectifier.For example, can use based on as the rectifier of the solid electrolyte of germanium silicide or other suitable material, so that rectifier to be provided.Other representational solid electrolyte material please refer to United States Patent (USP) case the 7th, 382, No. 647 cases.
Each memory component 544-1 to 544-4 is coupled to corresponding conductive contact layer 160-1 to 160-4.Contact layer 160-1 to 160-4 is coupled to plane decoder 546 via electric conductor 180 and interconnection 185.Plane decoder 546 in response to address to apply a voltage, as ground connection 547, to selected layer, so that the rectifier in memory component is by forward bias voltage drop and conducting, and apply a voltage to or the non-selected layer of floating so that the rectifier in memory component is by reverse bias or not conducting.
Fig. 7 illustrates the simplification calcspar of integrated circuit (IC) apparatus 300, and integrated circuit (IC) apparatus 300 comprises the 3 D memory array 360 with interconnection structure described here.Column decoder 361 is coupled to multiple word lines 140 of arranging along the row in memory array 360.Row decoder 363 is coupled to multiple bit lines 150 of arranging along the row in memory array 360, for reading and programming from the data of the memory cell of array 360.Plane decoder 546 is via electric conductor 180 and the interconnection 185 multiple contact layer 160-1 to 160-4 that are coupled in memory array 360.In bus 365, by address provision to row decoder 363, column decoder 361 and plane decoder 546.In this example, the sensing amplifier in square 366 and data input structure, see through data/address bus 367 and be coupled to row decoder 363.Input/output end port from integrated circuit 300, sees through Data In-Line 371, and data are supplied to the data input structure in square 366.In described embodiment, on integrated circuit 300, comprise other circuit 374, for example general processor of object or the application circuit of specific purposes, or the combination of the module of system-on-a-chip (system-on-a-chip) function is provided.Sensing amplifier from square 366, sees through DOL Data Output Line 372, and data are supplied to the input/output end port on integrated circuit 300, or is supplied to inside or other outside data destination of integrated circuit 300.
Use bias voltage to arrange state machine 369 and be rendered in the controller in this example, control via Voltage Supply Device or the supply in square 368 and produce or applying of voltage supplied in the bias voltage arrangement that provides, for example, read voltage and program voltage.Controller can be carried out with the specific purposes logical circuit as known skill.In other embodiment, controller comprises general object processor, and this processor can be practiced on identical integrated circuit, and this integrated circuit computer program is with the operation of control device.In another other embodiment, the combination of specific purposes logical circuit and general object processor can be used in the implementation of this controller.
Fig. 8 A to Fig. 8 C to Figure 15 illustrates in order to manufacture and is described in this and has the step in the embodiment of manufacturing process of the interconnection structure in very little floor space district.
Fig. 8 A and Fig. 8 C illustrate the cross section view of the first step of manufacturing process, and Fig. 8 B illustrates the top view of the first step of manufacturing process.For the object of this application, first step relates to and forms multiple contact layer 160-1 to 160-4 the top of provided memory cell access layer 112 is provided.In shown in embodiment in, the structure that Fig. 8 A to Fig. 8 C illustrates is to use the U.S. patent application case the 12/430th owned together by Lung, the technique described in No. 290 cases forms, this case is as above-mentioned reference.
In a further embodiment, contact layer can form by the standard technology as known skill, and can comprise doped region in access device for example transistor AND gate diode, word line, bit line and source electrode line, conductive plunger and substrate, depend on this device, wherein interconnection structure described herein is implemented.
As mentioned above, also can be used in other embodiment for memory cell and the configuration of other type of memory array area 110.
Then, first mask 800 with opening 810 is formed in the structure shown in Fig. 8 A to Fig. 8 C, and produces the top view of Fig. 9 A to Fig. 9 B and the structure that cross section view illustrates respectively.The first mask 800 can by deposition be used for the first mask 800 layer form, and use photoetching technique patterning this layer with form opening 810.The first mask can comprise for example hard mask material, as silicon nitride, Si oxide or silicon oxynitride.
Opening 810 in the first mask 800 is around the periphery of the combination in the landing region on contact layer 160-1 to 160-4.Therefore, the width 192 of opening 810 is at least equally wide with the width in the landing region on contact layer 160-1 to 160-4, so that the electric conductor 180 of follow-up formation can be through the opening in contact layer.The length 194 of opening 810 is at least equally long with the summation of the length in the landing region on contact layer 160-1 to 160-4, so that the electric conductor 180 of follow-up formation can be through the opening in contact layer.
Then, the second etching mask 900 is formed in the structure shown in Fig. 9 A to Fig. 9 B, is contained in opening 810, and produces the top view of Figure 10 A to Figure 10 B and the structure that cross section view illustrates respectively.As shown in FIG., the second etching mask 900 has the length 194 that length 910 is less than opening 810, and the second etching mask 900 has at least the width equally wide with the width 192 of opening 810.
In shown in embodiment in, the second etching mask 900 comprises the material being optionally etched with respect to the material of the first mask 800, so that the length of the second mask 900 in opening 810, can in following subsequent process steps, optionally reduce.In other words,, for the technique of the length in order to reduce by the second mask 900, the etching rate that the material of the second mask 900 has is greater than the etching rate of the material of the first mask 800.For example, in this embodiment, the first mask 800 comprises hard mask material, and the second mask can comprise photoresist material.
Then, use first and second mask 800,900 as etching mask, in the structure shown in Figure 10 A to Figure 10 B, carry out etching technics, and produce the top view of Figure 11 A to Fig. 1 ib and the structure that cross section view illustrates respectively.Etching technics can be implemented with single etch chemistries thing, for example time series pattern etching (timing mode etching).Or etching technics can be implemented with different etch chemistries thing, with individually etching insulating barrier 166, contact layer 160-4, insulating material 165-3 and contact layer 160-3.
This etching forms the opening 1000 through contact layer 160-4, to expose a part of contact layer 160-3.Opening 1000 is arranged at the top of the landing region 161-1a on contact layer 160-1.Opening 1000 has at least the same length of growing 1002 of length with landing region 161-1a, and has at least the width 1004 equally wide with the width of landing region 161-1a.
This etching also forms the opening 1010 through contact layer 160-4, to expose a part of contact layer 160-3.Opening 1010 is arranged at the top of the landing region 161-1b on contact layer 160-1.Opening 1010 has at least the same length of growing 1012 of length with landing region 161-1b, and has at least the width 1004 equally wide with the width of landing region 161-1b.
Then, reduce the length 910 of mask 900 to form the mask 1100 through reducing length, it has length 1110, and produces the top view of Figure 12 A to Figure 12 B and the structure that cross section view illustrates respectively.In shown in embodiment in, mask 900 comprises photoresist material, and can for example use and have with CL
2or the reactive ion etching of the HBr chemicals that are substrate is carried out trim mask 900.
Then, use the first mask 800 and the mask 1100 through reducing length as etching mask, in the structure shown in Figure 12 A to Figure 12 B, carry out etching technics, and produce the top view of Figure 13 A to Figure 13 B and the structure that cross section view illustrates respectively.
Etching technics extends opening 1000,1010 through contact layer 160-3, to expose the part of the below that is arranged at contact layer 160-2.
This etching also forms opening 1200,1210 part through contact layer 160-4, and because of the minimizing of the length of mask 1100, no longer masked 1100 cover, and exposes the part of contact layer 160-3 with this.Opening 1200 is to form adjacent to opening 1000, and is arranged at the top of the landing region 161-2a on contact layer 160-2.Opening 1200 has at least the same length of growing 1202 of length with landing region 161-2a, and has at least the width 1204 equally wide with the width of landing region 161-2a.
Then, reduce the length 1110 of mask 1100 to form the mask 1300 through reducing length, it has length 1305.Use the first mask 800 and mask 1300 as etching mask, carry out etching technics and produce the top view of Figure 14 A to Figure 14 B and the structure that cross section view illustrates respectively.
Etching technics extends opening 1000,1010 through contact layer 160-2, to expose landing region 161-1a, the 161-1b on contact layer 160-1.Etching technics also extends opening 1200,1210 through contact layer 160-3, to expose landing region 161-2a, the 161-2b on contact layer 160-2.
This etching also forms opening 1310,1320 part through contact layer 160-4, because of the minimizing of the length of mask 1300, no longer capped, exposes landing region 161-3a, the 161-3b on contact layer 160-3 with this.
Then, insulation filling material 1400 is deposited in the structure shown in Figure 14 A to Figure 14 B, and carry out flatening process, as chemico-mechanical polishing (Chemical Mechanical Polishing, CMP), to remove mask 800,1300, and the structure shown in the cross section view of generation Figure 15.
Then, form photoengraving pattern, with define for electric conductor 180 and be connected to landing region through hole.Can application response ion etching, with the through hole that forms high-aspect-ratio through insulation filling material 1400, to be provided for the through hole of electric conductor 180.After offering through hole, fill this through hole with tungsten or other electric conducting material, to form electric conductor 180.Then applied metal metallization processes is to form interconnection 185, so that being connected between the plane decoding circuit on electric conductor 180 and device to be provided.Finally, application backend process (back end of line, BEOL) is to complete integrated circuit, and the structure shown in generation Fig. 3 A to Fig. 3 B.
In different contact layers for electric conductor being passed through to be arranged at the opening in the landing region on the contact layer of below, that patterning contact layer forms by being used in the opening 810 in single etching mask 800, and use the technique of the mask extra for etching, and needn't crucial alignment step.Therefore, having the opening of the sidewall of vertical alignment in different contact layers, is to form in the mode of self-aligned.
In example shown in upper, the opening 810 in mask 800 has the section of rectangle on plane angle.Therefore, the opening in different contact layers, transversely has identical in fact width in direction.Or, depend on that the shape in the landing region of different contact layers, the opening in mask 800 can have circle, ellipse, square, rectangle or some difform sections.
For example, in order to hold the landing region with different in width, the width of the opening in mask 800 can change in a longitudinal direction and to some extent.Figure 16 illustrates the plan view of the opening 1510 in mask 800, and this mask 800 is with the mode vicissitudinous width of tool in a longitudinal direction of similar ladder, and causes the width of the opening in contact layer therefore to change to some extent.
Now will mainly with reference to Figure 17 to Figure 34 A, the present invention be described.
Following description is conventionally with reference to embodiment and the method for ad hoc structure.Be interpreted as not intending to limit embodiment and the method for invention to specific exposure, but can carry out with further feature, element, method and embodiment.Preferred embodiment will be described with explanation the present invention, and unrestricted by the defined category of the present invention of claim scope.These a little known skill persons will admit the variation of various equalizations described below.In different embodiment, identical element is with the common reference of identical component symbol.
Figure 17 to Figure 34 A illustrates structure and the method for the example of manufacturing another 3-D stacks integrated circuit (IC) apparatus, and similar label is equivalent to similar structure.Figure 17 and Figure 17 A are simplified side section and the top view of the interconnect area 17 of this example of 3-D stacks integrated circuit (IC) apparatus.In this example, interconnect area 17 comprises four interconnection contact layers 18, and it is labeled as 18.1 to 18.4, four electric conductors 54, and it is labeled as 54.1 to 54.4, and a grounded conductive body 55.Electric conductor 54 has Part I 57 through contact layer 18, and there is Part II 59 through interlayer dielectric 52 and stop-layer (Stopping Layer) 27, to be electrically connected to one of them of interconnection contact area 14 (being labeled as 14.1 to 14.4) of conductive layer 34 (being labeled as 34.1 to 34.4) of contact layer 18.Part I 57 be by 61 of dielectric sidewall spacer around, with by electric conductor 54 electrical isolation in conductive layer 34, make electric conductor not in electrical contact.In addition, grounded conductive body 55 is electrically connected to each conductive layer 34 of each contact layer 18.
Figure 18 and Figure 18 A illustrate the initial step of the manufacture of interconnect area 17.Make material 88 etching contact openings 33 and ground connection contact openings 35 with photoresist, pass upper strata 24 to expose the upper strata conductive layer 34.1 of the first contact layer 18.1, wherein contact openings 33 is labeled as opening 33.1 to 33.4, and ground connection contact openings 35 is to be illustrated in Figure 18 A.After the etching of contact openings 33, photoresist material 88 is divested, and forms the first photoresist mask 89 in interconnect area 17, as shown in Figure 19 and Figure 19 A.The first mask 89 exposes every an opening 33, that is opening 33.2 and 33.4 in this example.As Figure 19 A, mask 89 also covers ground connection contact openings 35.Via relatively Figure 17 and Figure 18 are known, the position of the determining positions electric conductor 54 of contact openings 33, the position of the determining positions grounded conductive body 55 of ground connection contact openings 35.In this example, electric conductor 54 and interconnection contact area 14 have constant spacing.
Figure 20 and Figure 20 A illustrate the etching result that is passed in the single contact layer 18.1 under the contact openings 33.2 and 33.4 exposing.Then the first mask 89 is divested, and forms the second photoresist mask 90 as shown in Figure 21 and Figure 21 A thereupon.The second mask 90 is in order to expose contact openings 33.3 and 33.4, covers contact openings 33.1 and 33.2 and ground connection contact openings 35 simultaneously.Figure 21 illustrates removing of the first mask 89 and the second mask 90 and is formed at the structural result of Figure 20, the first and second contact openings 33.1 and 33.2 that come from left side number are covered by the second mask, and the third and fourth contact openings 33.3 and 33.4 is exposed.
Figure 22 and Figure 22 A illustrate the etching result of two contact layers 18 that are passed down through the 3rd and the 4th contact openings 33.3 and 33.4.That is contact layer 18.1 and 18.2 is etched through in contact openings 33.3, and contact layer 18.2 and 18.3 is etched through in contact openings 33.4.Figure 23 and Figure 23 A illustrate the second mask structure after 90s that removes Figure 22.Visible contact openings 33.1 to 33.4 extends downward the conductive layer 34.1 to 34.4 of contact layer 18.1 to 18.4.
Figure 24 and Figure 24 A illustrate Figure 23 and form the structure after sidewall spacer 61 on the sidewalls of opening 33.1 to 33.4.Sidewall spacer 61 is electrically insulated from contact openings 33.2,33.3 and 33.4 conductive layer 34 of the contact layer 18 that contact openings passes through.
The structure that Figure 25 and Figure 25 A illustrate Figure 24 adds the cross section view of the contact openings of ground connection shown in Figure 25 35.All contact openings 33 are covered by photoresist material 92, exposure of ground connection contact openings 35.Figure 26 and Figure 26 A illustrate Figure 25 and pass the structure after three contact layers 18 in ground connection contact openings 35 etchings, to expose the inside of conductive layer 34.1 to 34.4 to ground connection contact openings 35.Figure 27 and Figure 27 A illustrate Figure 26 and remove the structure after photoresist material 92.
Figure 28 and Figure 28 A illustrate Figure 27 and deposit the structure after electrical electric conducting material 93, and electrically electric conducting material 93 is generally polysilicon, fills contact openings 33 and ground connection contact openings 35 with this.This material 93 in contact openings 33 and ground connection contact openings 35 forms respectively electric conductor 54 and grounded conductive body 55.If necessary, can be returned etching or first be removed the interior formation grounded conductive body 55 of ground connection contact openings 35 is front in the part of the insulating barrier 36 of ground connection contact openings sidewall, to strengthen in electrical contact between grounded conductive body 55 and the conductive layer 34 of contact layer 18.This is to represent by a dotted line in Figure 28 in the insulating barrier 36 of grounded conductive body 55.
Electrically electric conducting material 93 also covers the dielectric layer 26 on upper strata 24.After this, the structure of Figure 28 is etched and removes the electrical electric conducting material 93 that covers dielectric layer 26.This is illustrated in Figure 29 and Figure 29 A.Make the structure of Figure 29 bear for example chemico-mechanical polishing (chemical mechanical polishing) down to stop-layer 27, produce the structure of Figure 30.
Figure 31 and Figure 31 A illustrate Figure 30 and deposit stop-layer 96 and deposit subsequently the structure of interlayer dielectric 97 after on stop-layer, and stop-layer 96 is generally silicon nitride.Then the structure of Figure 31 has the extension of contact openings 33 and ground connection contact openings 35, and it is to form to electric conductor 54 and grounded conductive body 55 through interlayer dielectric 97 and stop-layer 96, and electric conductor 54 is labeled as 54.1 to 54.4.See Figure 32 and Figure 32 A, fill this extension subsequently with electric conducting material, for example tungsten, to produce electric conductor 54 and grounded conductive body 55.Electric conductor 54 has Part I 57 extensions and passes through contact layer 18, and upper strata 24 is passed through in Part II 59 extensions.
In some instances, stop-layer 96 is silicon nitride, and interlayer dielectric 97 is silicon dioxide.But stop-layer 96 can be other dielectric materials layer, as the layer of silicon dioxide or other silica and silicon nitride.Sidewall spacer 61 can be silicon nitride but also can be other material, as the multilayer of silicon dioxide or oxygen/silicon nitride.Similarly, dielectric layer 25 is generally silicon nitride but also can be for example silicon dioxide.The Part I 57 of electric conductor 54 is generally polysilicon but also can be other electric conducting material, as N+ polysilicon, tungsten, titanium nitride (TiN) etc.And the entire length of electric conductor 54 can be identical material, as tungsten.
Figure 33 is with one group of 16 contact openings of graphic drawing, represents four groups of different contact openings 33, is etched to 16 different degree of depth, by only providing passage to enter 16 contact layers 18 with four masks.
Figure 34 and Figure 34 A are section and the plan view of a 3-D stacks integrated circuit (IC) apparatus.Figure 34 is for to illustrate along word line 94, and this word line is the lamination that electrical isolation replaces in for example dielectric medium and semiconductor layer by layer 95.Layer 95 can be replacing of for example silica and silicon nitride, as electric charge capture layer.
Following example discussion provides the method that is electrically connected to interconnection contact area 14, and interconnection contact area 14 is positioned at the lamination place for the contact layer 18 of the interconnect area 17 of 3-D stacks integrated circuit (IC) apparatus.In this example, interconnect area 17 comprises upper strata 24, has the lamination of contact layer 18 under upper strata, and each contact layer comprises conductive layer 34 and insulating barrier 36.At least a portion that is arranged at any upper strata 24 in interconnect area 17 is removed, and to expose the first contact layer 18.1, and produces the contact openings 33 for each contact layer 18.This is illustrated in Figure 18.
Use one group of N etching mask, produce the interconnection contact area 14 of 2N layer in the lamination place of contact layer 18, the number of plies nearly and comprise 2N.Although be illustrated as the example of four contact layers 18 most, in this example, the quantity of contact layer will be increased to 16 contact layers, therefore N=4.Discussion at this will be also with reference to Figure 33, comprising the figure representative of 16 contact openings 33.Carrying out etching contact openings 33 with mask and reach and comprise 2N contact layer, is 16 contact layers in this example.Step is as performed below.
With reference to Figure 19, with the first mask 89 in carry out contact layer 18 of etching every an opening.The contact openings not covered by the first mask 89 is considered as being equal to eight dotted lines boxes around contact openings 33.2,33.4 etc. shown in Figure 33.Then,, with reference to Figure 21, carry out two contact layers 18 of etching in the third and fourth contact openings of the order with one group of first to fourth contact openings with the second mask 90.The second mask 90 is considered as being equal to Figure 33 and is shown in the central four groups of short dash line boxes around two adjacent contact openings 33 of one group of four contact openings.The third and fourth contact openings being etched in this example is contact openings 33.3 and 33.4, the contact openings 33.7 and 33.8 of contact openings 33.5 to 33.8 this groups etc. of the first contact openings 33.1 to the 4th contact openings 33.4 these groups.As seen from Figure 22, the use of the first and second masks 89,90 provides the contact openings 33 down to 18.1 to 18.4 each layers of four contact layers.
Then there is this example of 16 contact layers 18, use the 5th to the 8th contact openings 33 of the 3rd mask (not illustrating) Yu Yiyi group the first order to the 8th contact openings to carry out four contact layers 18 of etching.This points out by two in Figure 33 long dotted line boxes.Use the 4th mask (not illustrating) in carrying out eight contact layers 18 of etching with the 9th of at least one group of the first order to the 16 contact openings to the 16 contact openings 33.This points out by a solid line box in Figure 33.Note having the contact openings of half be by each first, second, third and the 4th mask carry out etching.
With reference to Figure 24, dielectric layer 61 is formed on the sidewall of each contact openings 33.Electric conductor 54 then form with through contact openings 33 to the interconnection contact area 14 of contact layer 18, this dielectric layer along sidewall by electric conductor 54 electrical isolation in conductive layer 34
As the discussion with reference to Figure 18 and Figure 19 above, ground connection contact openings 35 is formed in the mode identical with contact openings 33.1 conventionally.But, with reference to Figure 24, before the interior formation electric conductor 54 of contact openings 33, the part both sides of ground connection contact openings 35 in upper strata 24 is arranged with sidewall spacer, with reference to Figure 26, then be etched through contact layer 18, be then filled with as shown in figure 28 electrical electric conducting material to produce grounded conductive body 55.Grounded conductive body 55 each conductive layer 34 in electrical contact.On the contrary, because the use of dielectric sidewall spacer 61, electric conductor 54.1 to 54.4 only contacts single conductive layer 34.In some examples, grounded conductive body 55 can be not in electrical contact with each conductive layer 34.
In above example, contact openings 33 is to count to the right side from a left side.If necessary, contact openings can count to the right side from a left side or count to a left side from the right side or according to design requirement with other ordinal number number.Key point is always to make the contact openings of half open by each mask.That is in the time having the contact openings of even number, each mask is opening the contact openings of half, in the time having the contact openings of odd number, for example 15, each mask by open a little more than or fewer than half contact openings a little, for example 7 or 8.Removing of one deck/two-layer/tetra-layer/eight layers also can be expressed as the removing to 2 (N-1) layer for each step 20.
The mask of Figure 33 and etching program are illustrated in Figure 35 with different forms.In Figure 35, and in follow-up Figure 36 to Figure 39,0 represents darkly, that is has photoresist material, and 1 represent to open, that is there is no photoresist material, and making has 8 for opening for 16 contact openings of each mask.
If the etching flow process example of Figure 33 and Figure 35 removes one/bis-/tetra-/eight layers for mask 1-4, can be identified as and be located in layer by the contact layer place of being located in (that is being etched to) of etching positioned in sequence, be appointed as 0-15.The contact layer place of being located in (that is being etched to) causing at each position A to P is as shown for being located in layer 0,1,2,3 etc.
Can use other etching order.For example, Figure 36 illustrates the change of etching order, wherein exchanges masked 1 and the number of plies of 4 etchings of mask, makes 8 layers of mask 1 etchings, 2 layers of mask 2 etchings, 4 layers of mask 3 etchings, 1 layer of mask 4 etching.The contact layer place of being located in (that is being etched to) causing at each position A to P is as shown for being located in layer 0,8,2,10 etc.
Non-change etching order, or except changing etching order, that is as compared the number of plies of each mask institute etching that Figure 35 and Figure 36 demonstrated, mask order can change.This is illustrated in Figure 37, and wherein 4 layers of 2 layers of mask 2 etchings and mask 3 etchings, as the example of Figure 35.But, in the example of Figure 35, become the mask order for mask 3 in the example of Figure 37 for the mask order of mask 2 (00110011 etc.), in the example of Figure 35, become the order of the mask for mask 2 of Figure 37 for the mask order of mask 3 (00001111000 etc.).The contact layer place of being located in (that is being etched to) causing at each position A to P is as shown for being located in layer 0,1,4,5 etc.
The position illustrating with reference to Figure 38 changes.In this example, be same as Figure 35 for the number of plies of 1 to 4 etching of mask, even if position A and position J have exchanged, also remain identical for the layer that is located in of each position A to P, comprising for A position is layer 0, is layer 9 for J position.But, for two examples of Figure 35 and Figure 36, all identical for the etching of each position A to P.The contact layer place of being located in (that is being etched to) causing at each position J, B, C etc. is as shown for being located in layer 9,1,2,3 etc.
Figure 39 illustrates the result that the etching order that adopts the first case of Figure 35 and make Figure 36 changes, the mask order of Figure 37 changes and the position of Figure 38 changes.But this structure causing still has 16 different layers that are located in for 16 different positions.The contact layer place of being located in (that is being etched to) causing at each position J, B, C etc. is as shown for being located in layer 9,8,4,12 etc.
Publication as open in above referenced any patent, patent application case and printing is to be incorporated into this as reference.
In sum, although the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion of defining depending on the claim scope of enclosing.
Claims (9)
1. a 3-D stacks integrated circuit (IC) apparatus, comprising:
At least first, second, third and a lamination of the 4th contact layer, be positioned at an interconnect area;
Respectively this contact layer comprises a conductive layer and an insulating barrier;
First, second, third and the 4th electric conductor through the part of this lamination of the plurality of contact layer;
This first, second, third and the 4th electric conductor respectively with this first, second, third and the 4th conductive layer in electrical contact; And
One dielectric sidewall spacer is around changed around this second, third and the 4th electric conductor so that this second, third and the 4th electric conductor only in electrical contact separately this second, third and the 4th conductive layer.
2. stacked integrated circuit device according to claim 1, wherein this first, second, third and the 4th electric conductor there is a constant spacing.
3. stacked integrated circuit device according to claim 2, wherein this first, second, third and the position of the 4th electric conductor be to be determined by a common mask.
4. stacked integrated circuit device according to claim 1, wherein this first, second, third and the position of the 4th electric conductor be to be determined by a common mask.
5. stacked integrated circuit device according to claim 1, more comprise a grounded conductive body through the part of this lamination of the plurality of contact layer and in electrical contact respectively this first, second, third and the 4th conductive layer.
6. stacked integrated circuit device according to claim 5, wherein this first, second, third and the position of the 4th electric conductor and this grounded conductive body be to be determined by a common mask.
7. a 3-D stacks integrated circuit (IC) apparatus comprises:
At least first, second, third and a lamination of the 4th contact layer, be positioned at an interconnect area;
Respectively this contact layer comprises a conductive layer and an insulating barrier;
First, second, third and the 4th electric conductor through the part of this lamination of the plurality of contact layer;
This first, second, third and the 4th electric conductor respectively with this first, second, third and the 4th conductive layer in electrical contact; And
This first, second, third and the 4th electric conductor there is a constant spacing.
8. stacked integrated circuit device according to claim 7, wherein this first, second, third and the position of the 4th electric conductor be to be determined by a common mask.
9. a 3-D stacks integrated circuit (IC) apparatus, comprising:
At least first, second, third and a lamination of the 4th contact layer, be positioned at an interconnect area;
Respectively this contact layer comprises a conductive layer and an insulating barrier;
First, second, third and the 4th electric conductor through the part of this lamination of the plurality of contact layer;
This first, second, third and the 4th electric conductor respectively with this first, second, third and the 4th conductive layer in electrical contact;
One dielectric sidewall spacer is around changed around this second, third and the 4th electric conductor so that this second, third and the 4th electric conductor only in electrical contact separately this second, third and the 4th conductive layer;
One grounded conductive body through the part of this lamination of the plurality of contact layer and in electrical contact respectively this first, second, third and the 4th conductive layer;
This first, second, third and the 4th electric conductor there is a constant spacing; And
This first, second, third and the position of the 4th electric conductor and this grounded conductive body be to be determined by a common mask.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161434423P | 2011-01-19 | 2011-01-19 | |
| US61/434,423 | 2011-01-19 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110182911.7A Division CN102610614B (en) | 2011-01-19 | 2011-06-27 | 3-D stacks integrated circuit (IC) apparatus and manufacture method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103904084A true CN103904084A (en) | 2014-07-02 |
Family
ID=46527885
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410153001.XA Pending CN103904084A (en) | 2011-01-19 | 2011-06-27 | Multilayer connection structure and making method |
| CN201110182911.7A Active CN102610614B (en) | 2011-01-19 | 2011-06-27 | 3-D stacks integrated circuit (IC) apparatus and manufacture method thereof |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110182911.7A Active CN102610614B (en) | 2011-01-19 | 2011-06-27 | 3-D stacks integrated circuit (IC) apparatus and manufacture method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (2) | CN103904084A (en) |
| TW (1) | TWI447851B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111448648A (en) * | 2020-03-13 | 2020-07-24 | 长江存储科技有限责任公司 | Contact structure for three-dimensional memory |
| JP2022501828A (en) * | 2018-09-26 | 2022-01-06 | 長江存儲科技有限責任公司Yangtze Memory Technologies Co., Ltd. | Methods for Forming 3D Memory Devices and 3D Memory Devices |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8643078B2 (en) | 2012-04-10 | 2014-02-04 | Macronix International Co., Ltd. | Semiconductor structure and manufacturing method of the same |
| US8704205B2 (en) | 2012-08-24 | 2014-04-22 | Macronix International Co., Ltd. | Semiconductor structure with improved capacitance of bit line |
| US9165823B2 (en) | 2013-01-08 | 2015-10-20 | Macronix International Co., Ltd. | 3D stacking semiconductor device and manufacturing method thereof |
| US8921225B2 (en) * | 2013-02-13 | 2014-12-30 | Globalfoundries Inc. | Method for off-grid routing structures utilizing self aligned double patterning (SADP) technology |
| US8993429B2 (en) * | 2013-03-12 | 2015-03-31 | Macronix International Co., Ltd. | Interlayer conductor structure and method |
| CN104637900B (en) * | 2013-11-12 | 2017-07-14 | 旺宏电子股份有限公司 | IC apparatus and its manufacture method |
| KR102241248B1 (en) * | 2014-09-23 | 2021-04-16 | 삼성디스플레이 주식회사 | Curved display device |
| CN105590934B (en) * | 2014-11-13 | 2018-12-14 | 旺宏电子股份有限公司 | Three-dimensional storage and its manufacturing method |
| US9449966B2 (en) | 2015-01-14 | 2016-09-20 | Macronix International Co., Ltd. | Three-dimensional semiconductor device and method of manufacturing the same |
| TWI576986B (en) * | 2015-09-30 | 2017-04-01 | 旺宏電子股份有限公司 | Memory structure |
| US9953993B2 (en) * | 2016-07-25 | 2018-04-24 | Toshiba Memory Corporation | Semiconductor memory device |
| US10446437B2 (en) * | 2016-10-10 | 2019-10-15 | Macronix International Co., Ltd. | Interlevel connectors in multilevel circuitry, and method for forming the same |
| CN106847822B (en) * | 2017-03-08 | 2018-11-16 | 长江存储科技有限责任公司 | 3D nand memory part, manufacturing method and step calibration method |
| US10276497B2 (en) | 2017-09-27 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Tapering discrete interconnection for an integrated circuit (IC) |
| US11004726B2 (en) * | 2017-10-30 | 2021-05-11 | Macronix International Co., Ltd. | Stairstep structures in multilevel circuitry, and method for forming the same |
| CN107863351B (en) | 2017-11-21 | 2019-03-19 | 长江存储科技有限责任公司 | A kind of production method and 3D nand flash memory of high stacking number 3D nand flash memory |
| US10892267B2 (en) * | 2018-02-15 | 2021-01-12 | Sandisk Technologies Llc | Three-dimensional memory device containing through-memory-level contact via structures and method of making the same |
| KR102624625B1 (en) * | 2018-04-20 | 2024-01-12 | 삼성전자주식회사 | Vertical memory devices and methods of manufacturing the same |
| KR20220012120A (en) | 2020-07-22 | 2022-02-03 | 삼성전자주식회사 | Memory device |
| US11289130B2 (en) | 2020-08-20 | 2022-03-29 | Macronix International Co., Ltd. | Memory device |
| TWI747634B (en) * | 2020-11-25 | 2021-11-21 | 旺宏電子股份有限公司 | Memory device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060030144A1 (en) * | 2003-03-28 | 2006-02-09 | Hasan Nejad | Method of fabricating integrated circuitry |
| CN101179079A (en) * | 2000-08-14 | 2008-05-14 | 矩阵半导体公司 | Rail stack array of charge storage devices and method of making same |
| CN101286480A (en) * | 2007-02-07 | 2008-10-15 | 旺宏电子股份有限公司 | Structures for and method of silicide formation on memory array and peripheral logic devices |
| US20090020744A1 (en) * | 2007-06-29 | 2009-01-22 | Kabushiki Kaisha Toshiba | Stacked multilayer structure and manufacturing method thereof |
| US20100013107A1 (en) * | 2008-07-16 | 2010-01-21 | Micron Technology, Inc. | Interconnect structures for integration of multi-layered integrated circuit devices and methods for forming the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7528066B2 (en) * | 2006-03-01 | 2009-05-05 | International Business Machines Corporation | Structure and method for metal integration |
| CN101303935A (en) * | 2007-01-05 | 2008-11-12 | 阿维科斯公司 | Very low profile multilayer components |
| US8829646B2 (en) * | 2009-04-27 | 2014-09-09 | Macronix International Co., Ltd. | Integrated circuit 3D memory array and manufacturing method |
-
2011
- 2011-06-07 TW TW100119885A patent/TWI447851B/en active
- 2011-06-27 CN CN201410153001.XA patent/CN103904084A/en active Pending
- 2011-06-27 CN CN201110182911.7A patent/CN102610614B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101179079A (en) * | 2000-08-14 | 2008-05-14 | 矩阵半导体公司 | Rail stack array of charge storage devices and method of making same |
| US20060030144A1 (en) * | 2003-03-28 | 2006-02-09 | Hasan Nejad | Method of fabricating integrated circuitry |
| CN101286480A (en) * | 2007-02-07 | 2008-10-15 | 旺宏电子股份有限公司 | Structures for and method of silicide formation on memory array and peripheral logic devices |
| US20090020744A1 (en) * | 2007-06-29 | 2009-01-22 | Kabushiki Kaisha Toshiba | Stacked multilayer structure and manufacturing method thereof |
| US20100013107A1 (en) * | 2008-07-16 | 2010-01-21 | Micron Technology, Inc. | Interconnect structures for integration of multi-layered integrated circuit devices and methods for forming the same |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022501828A (en) * | 2018-09-26 | 2022-01-06 | 長江存儲科技有限責任公司Yangtze Memory Technologies Co., Ltd. | Methods for Forming 3D Memory Devices and 3D Memory Devices |
| EP3811410A4 (en) * | 2018-09-26 | 2022-05-18 | Yangtze Memory Technologies Co., Ltd. | 3d memory device and method for forming 3d memory device |
| CN111448648A (en) * | 2020-03-13 | 2020-07-24 | 长江存储科技有限责任公司 | Contact structure for three-dimensional memory |
| CN111448648B (en) * | 2020-03-13 | 2021-06-08 | 长江存储科技有限责任公司 | Contact structure for three-dimensional memory |
| WO2021179273A1 (en) * | 2020-03-13 | 2021-09-16 | Yangtze Memory Technologies Co., Ltd. | Contact structures for three-dimensional memory |
| US11862565B2 (en) | 2020-03-13 | 2024-01-02 | Yangtze Memory Technologies Co., Ltd. | Contact structures for three-dimensional memory |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI447851B (en) | 2014-08-01 |
| CN102610614A (en) | 2012-07-25 |
| CN102610614B (en) | 2015-11-25 |
| TW201232701A (en) | 2012-08-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102610614B (en) | 3-D stacks integrated circuit (IC) apparatus and manufacture method thereof | |
| KR101812987B1 (en) | Method of reducing number of masks for ic device with stacked contact levels and a set of masks for ic device | |
| CN102088019B (en) | Three-dimensional laminated element with an interconnect structure and manufacturing method thereof | |
| US9269660B2 (en) | Multilayer connection structure | |
| US10388720B2 (en) | Capacitor with 3D NAND memory | |
| CN103579093B (en) | IC apparatus and in order to be used in the method in this IC apparatus | |
| US8659946B2 (en) | Non-volatile memory devices including vertical NAND strings and methods of forming the same | |
| US9263674B2 (en) | ETCH bias homogenization | |
| US8981567B2 (en) | 3-D IC device with enhanced contact area | |
| TWI440137B (en) | Reduced number of masks for ic device with stacked contact levels | |
| JP5751552B2 (en) | Method for reducing the number of masks for integrated circuit devices having stacked connection levels | |
| CN104051467A (en) | 3-D IC Device with Enhanced Contact Area | |
| CN103972151B (en) | Connect the forming method of the intermediate connector of the conductive layer of laminated construction | |
| TWI440167B (en) | Memory device and method for manufacturing the same | |
| CN102637629B (en) | Mask assembly of IC (integrated circuit) device with laminated contact layers for reducing number, as well as method thereof | |
| KR20120131115A (en) | Multilayer connection structure and making method | |
| CN103094201B (en) | Memorizer device and manufacturing method thereof | |
| CN106601751A (en) | Multi-layer three-dimensional structure with mirror landing area, and integrated circuit | |
| TW201301468A (en) | 3D memory array | |
| US20150091076A1 (en) | Isolation formation first process simplification |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140702 |