TWI747634B - Memory device - Google Patents

Abstract

A memory device includes a periphery wafer, a memory array chip stack, and a plurality of first conductive contacts. The periphery wafer has a functional surface. The memory array chip stack is disposed on the periphery wafer and has a functional surface, in which the functional surface of the periphery wafer faces toward the functional surface of the memory array chip stack, and a first side of the memory array chip stack is in a staircase configuration. The first conductive contacts are on the first side of the memory array chip stack, and between and interconnecting the functional surface of the periphery wafer and the functional surface of the memory array chip stack.

Description

Memory device

This disclosure relates to a memory device.

In recent years, the structure of semiconductor devices has continued to change, and the storage capacity of semiconductor devices has continued to increase. Memory devices are used in storage components of many products (such as MP3 players, digital cameras, and computer files). With the increase of these applications, the demand for memory devices is focused on small size and large storage capacity. In order to meet this condition, a memory device with high component density and small size and a manufacturing method thereof are required.

The technical aspect of this disclosure is a memory device.

According to some embodiments of the present disclosure, the memory device includes a peripheral wafer, a stack of memory array chips, and a plurality of first conductive contacts. The peripheral wafer has a functional surface, and the peripheral wafer includes controller logic. The memory array chip is stacked on the peripheral wafer and has a functional surface. The functional surface of the peripheral wafer faces the functional surface of the memory array chip stack, the first side of the memory array chip stack is configured in a stepped shape, the memory array chip stack includes a plurality of memory array chips, and the memory array chip includes Non-volatile memory. The first conductive contact is arranged on the first side of the memory array chip stack, and is located between the functional surface of the peripheral wafer and the functional surface of the memory array chip stack, and connects the functional surface of the peripheral wafer and the memory array chip stack The functional surface.

According to some embodiments of the present disclosure, the memory device includes a peripheral wafer, a stack of memory array chips, and a plurality of first conductive contacts. The peripheral wafer has a functional surface, and the peripheral wafer includes controller logic. The memory array chip is stacked on the peripheral wafer and has a functional surface. The functional surface of the peripheral wafer faces the functional surface of the memory array chip stack, the first side of the memory array chip stack is configured in a stepped shape, the memory array chip stack includes a plurality of memory array chips, and the memory array chip includes Volatile memory. The first conductive contact is arranged on the first side of the memory array chip stack, and is located between the functional surface of the peripheral wafer and the functional surface of the memory array chip stack, and connects the functional surface of the peripheral wafer and the memory array chip stack The functional surface.

In some embodiments of the present disclosure, the second side of the memory array chip stack is configured in a stepped shape, and the second side is adjacent to the first side of the memory array chip stack.

In some embodiments of the present disclosure, the memory device further includes a plurality of second conductive contacts disposed on the second side of the memory array chip stack and located between the functional surface of the peripheral wafer and the functional surface of the memory array chip stack And connect the functional surface of the peripheral wafer and the functional surface of the memory array chip stack.

In some embodiments of the present disclosure, the third side of the memory array chip stack relative to the first side is configured in an inverted step shape.

In some embodiments of the present disclosure, the memory array chip stack includes a plurality of memory array chips, which are vertically stacked face-to-back.

In some embodiments of the present disclosure, each memory array chip is exposed at the same interval from one of the adjacent memory array chips.

In some embodiments of the present disclosure, the length and width of the peripheral wafer are larger than the length and width of the memory array chip stack, respectively.

In some embodiments of the present disclosure, the memory device further includes a plurality of third conductive contacts disposed on the functional surface of the peripheral wafer and stacked around the memory array chip.

In some embodiments of the present disclosure, the memory device further includes a first dielectric layer that extends laterally above the peripheral wafer and surrounds the memory array chip stack and the first conductive contact.

In some embodiments of the present disclosure, the fourth side of the memory array chip stack relative to the second side is configured in an inverted step shape.

According to the above-mentioned embodiments of the present disclosure, since the first side of the memory array chip stack is configured in a stepped shape, a large number of first conductive contacts can be formed on the first side of the memory array chip stack and located between the peripheral wafers and the memory. Between array wafer stacks. In this way, a high-density and high-speed memory device can be formed. In addition, since the memory array chip stack is disposed above the peripheral wafer, and is not laterally adjacent to the peripheral wafer, the conductive patterns on the memory array chip stack and the conductive patterns on the peripheral wafer can be fabricated separately. In this way, the optimized conditions of the two processes (for example, thermal process) can be adjusted separately for the memory array chip stack and the surrounding wafers, so that the memory array chip stack and the surrounding wafer processes do not restrict each other And interference.

Hereinafter, multiple implementation manners of the present disclosure will be disclosed in diagrams. For the sake of clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this disclosure. That is to say, in some implementations of this disclosure, these practical details are unnecessary, and therefore should not be used to limit this disclosure. In addition, in order to simplify the drawings, some conventionally used structures and elements are shown in the drawings in a simple and schematic manner. In addition, for the convenience of readers, the size of each element in the drawings is not drawn according to actual scale.

As used herein, "about", "approximately" or "substantially" shall generally mean within 20 percent of a given value or range, preferably within 10 percent, and more preferably within 5 percent . The numerical values given here are approximate, which means that the meaning of the terms "about", "approximately" or "substantially" can be inferred if not explicitly stated.

FIG. 1A shows a top view of a memory device 100 according to some embodiments of the present disclosure. FIG. 1B illustrates a cross-sectional view of the memory device 100 in FIG. 1A according to some embodiments of the present disclosure, taken along the line 1B-1B′. FIG. 1C is a cross-sectional view of the memory device 100 in FIG. 1A according to some embodiments of the present disclosure, taken along the line 1C-1C′. Please refer to FIGS. 1A to 1C at the same time. The memory device 100 includes a peripheral wafer 110 and a memory array chip stack 120 disposed on the peripheral wafer 110. The peripheral wafer 110 includes a silicon substrate 112 with a functional surface 113. The memory array chip stack 120 includes a plurality of memory array chips 124 vertically stacked above the peripheral wafer 110. Each memory array chip 124 includes a silicon substrate 122 with a functional surface 123. It should be understood that the "functional surface" herein refers to a surface having conductive patterns such as conductive traces, wires, or conductive layers thereon, and can be depicted as a "functional layer" in Figure 1B. In some embodiments, the memory array chip 124 is vertically stacked above the peripheral wafer 110 in a face-to-bottom manner, so that the silicon substrate 122 of each memory array chip 124 faces The functional surface 123 of the adjacent memory array chip 124 directly contacts the functional surface 123 of the adjacent memory array chip 124. In addition, the functional surface 123 of the memory array chip 124 is collectively regarded as the functional surface of the memory array chip stack 120, and the functional surface of the memory array chip stack 120 faces the functional surface 113 of the peripheral wafer 110.

In some embodiments, the peripheral wafer 110 includes peripheral circuits for the memory array chip 124 or control logics for the memory array chip 124. Controller logic includes controllers. The memory array chip 124 includes non-volatile memory (NAND, AND, NOR or other flash memory) or volatile memory (DRAM or SRAM).

In some embodiments, the memory array chip 124 includes a non-volatile memory array area, and the peripheral wafer 110 includes peripheral circuits for the non-volatile memory array area.

In some embodiments, the memory array chip 124 includes a non-volatile memory array area and peripheral circuits for the non-volatile memory array area, and the peripheral wafer 110 includes controller logic for the non-volatile memory. .

In some embodiments, the memory array chip 124 includes a DRAM or SRAM memory array area and peripheral circuits for the DRAM or SRAM memory array area, and the peripheral wafer 110 includes controller logic for DRAM or SRAM memory. .

In some embodiments, the memory array chips 124 are stacked in an offset manner, that is, each memory array chip 124 is stacked on an adjacent memory array chip 124, and does not completely cover the adjacent memory.体array chip 124. For example, each memory array chip 124 may be rectangular, and two of its four sides are exposed by the adjacent memory array chip 124 from a top view angle, as shown in FIG. 1A. In other words, the edge portion of the non-functional surface 121 of each memory array chip 124 (that is, the surface of the silicon substrate 122 of the memory array chip 124 facing away from the functional surface 123) from the top view angle shown in Figure 1A Adjacent memory array chips 124 are exposed to form an inverted stepped configuration. On the other hand, the other two of the four sides of each memory array chip 124 are exposed from the adjacent memory array chip 124 from the bottom view, and Figure 1B only shows one of the two sides. One side is exposed by the adjacent memory array chip 124. In other words, the edge portion of the functional surface 123 of each memory array chip 124 is exposed by the adjacent memory array chip 124 from the bottom view, thereby forming a stepped configuration.

According to the above, since the memory array chip 124 is stacked in the aforementioned manner, the formed memory array chip stack 120 will have four sides, two of which are in a stepped configuration, and the other two are in an inverted stepped configuration. . For example, the first side S1 and the second side S2 of the memory array chip stack 120 are configured in a stepped shape, wherein the first side S1 of the memory array chip stack 120 is adjacent to the second side S2, and the memory array chip The edge portions of the functional surfaces 123 of 124 collectively form part of a stepped configuration. For another example, the third side S3 and the fourth side S4 of the memory array chip stack 120 are in an inverted stepped configuration, wherein the third side S3 is adjacent to the fourth side S4, and the third side S3 and the fourth side S4 Relative to the first side S1 and the second side S2, respectively, the edge portions of the non-functional surface 121 of the memory array chip 124 collectively form a partial inverted stepped configuration. It should be understood that the four sides of the memory array chip stack 120 are adjacent to and adjacent to the top surface TS of the memory array chip stack 120 (that is, the non-functional surface 121 of the topmost memory array chip 124) and the memory array The bottom surface BS of the chip stack 120 (that is, the functional surface 123 of the bottommost memory array chip 124).

In some embodiments, the peripheral wafer 110 and the memory array chip stack 120 are separated from each other, and the memory device 100 further includes a plurality of first conductive contacts 130 vertically disposed on the peripheral wafer 110 and the memory array chip stack 120 Thereby, the peripheral wafer 110 and the memory array chip stack 120 are electrically connected. For example, the first conductive contact 130 may be disposed on the first side S1 of the memory array chip stack 120, and disposed on the exposed edge portion of the functional surface 123 of the memory array chip 124, and located on the memory array chip 124 Between the functional surface 123 (that is, the functional surface of the memory array chip stack 120) and the functional surface 113 of the peripheral wafer 110, and connect the functional surface 123 of the memory array chip 124 and the functional surface 113 of the peripheral wafer 110. In some embodiments, the first conductive contact 130 is electrically connected to word lines (WLs). In some embodiments, the memory device 100 further includes a plurality of second conductive contacts 140 vertically disposed between the peripheral wafer 110 and the memory array chip stack 120, thereby electrically connecting the peripheral wafer 110 and the memory array chip Stack 120. For example, the second conductive contact 140 may be disposed on the second side S2 of the memory array chip stack 120, and disposed on the exposed edge portion of the functional surface 123 of the memory array chip 124, and located on the memory array chip 124 Between the functional surface 123 of the peripheral wafer 110 and the functional surface 113 of the peripheral wafer 110, and connect the functional surface 123 of the memory array chip 124 and the functional surface 113 of the peripheral wafer 110. In some embodiments, the second conductive contact 140 is electrically connected to bit lines (BLs).

In some embodiments, the first conductive contact 130 and the second conductive contact 140 may include copper, gold, or other suitable conductive metal materials. With the configuration of the first conductive contact 130 and the second conductive contact 140, the electronic components (for example, memory control unit, etc.) located on the peripheral wafer 110 can be electrically connected to the memory array chip stack 120, thereby maintaining the memory device 100 operations. In some embodiments, the total number of the first conductive contacts 130 and the second conductive contacts 140 is between about 100,000 and about 100,000,000, or preferably between about 1,000,000 and about 10,000,000. In detail, if the total number of the first conductive contact 130 and the second conductive contact 140 is less than 100,000, it may not be possible to form a high-density and high-speed memory device 100; and if the first conductive contact 130 and the second conductive contact When the total number of 140 is greater than 100,000,000, the first conductive contact 130 and the second conductive contact 140 are likely to be electrically short-circuited due to the high density. In some embodiments, each of the first conductive contact 130 and the second conductive contact 140 has a length L1, L2 and a width W1, W2 (please refer to FIG. 3 first) of each between about 0.1 μm and about 2 μm. In detail, if the lengths L1, L2 and widths W1, W2 are less than about 0.1 μm, it may be difficult to control the bonding of the first conductive contact 130 (and the second conductive contact 140) during the manufacturing process; and if the length is When L1, L2 and widths W1, W2 are greater than about 2 microns, high-density first and second conductive second conductive contacts 130, 140 and high-speed memory device 100 may not be formed.

In some embodiments, the memory array chip stack 120 may include at least four memory array chips 124 stacked above the peripheral wafer 110 so that the functional surface 123 of the memory array chip 124 has sufficient surface area to be exposed. In this way, a large number of first conductive contacts 130 and second conductive contacts 140 can be disposed on the exposed functional surface 123. In some embodiments, each memory array chip 124 has the same size (that is, has the same length and the same width), so that the stacking of the memory array chip 124 is simple and stable. In some embodiments, the edge portions of each memory array chip 124 located on the same side (for example, the first side S1, the second side S2, the third side S3, or the fourth side S4) are exposed at the same interval. In other words, the lateral distance D between the sidewalls S of the memory array chip 124 on the same side (for example, the third side S3) is the same. For example, the lateral distance D between the topmost memory array chip 124 on the side wall S of the third side S3 and the next top memory array chip 124 on the side wall S of the third side S3 is substantially equal to that of the next top The lateral distance D between the memory array chip 124 on the side wall S of the third side S3 and the memory array chip 124 on the third top side of the side wall S on the third side S3. In this way, the stacking of the memory array chip 124 can be simpler and more stable.

In some embodiments, the thickness T1 of each memory array chip 124 is between about 1 micrometer and about 50 micrometers, so that the overall thickness of the memory device 100 can be maintained in an appropriate range, and the memory The stacking of the array chip 124 is simple and stable. For example, if the thickness T1 of each memory array chip 124 is less than about 1 micron, the memory array chip 124 may be too thin to be functionalized, and the memory array chip 124 may be difficult to stack because it is difficult to pick up If the thickness T1 of each memory array chip 124 is greater than about 50 microns, the overall thickness of the memory device 100 may be too thick, which is not conducive to reducing the volume of the memory device 100.

In some embodiments, the memory device 100 further includes a plurality of third conductive contacts 150 vertically disposed on the functional surface 113 of the peripheral wafer 110 and surrounds the memory array chip stack 120. The third conductive contact 150 is configured to electrically connect the electronic components on the peripheral wafer 110 and external electronic components (for example, input/output power). In some embodiments, the top surface 151 of the third conductive contact 150 may be further connected to an external electronic component by a wire. The third conductive contact 150 may be further configured to connect the first conductive contact 130 and the second conductive contact 140 to the word line and the bit line, respectively. In some embodiments, the top surface 151 of each third conductive contact 150 is substantially coplanar with the top surface TS of the memory array chip stack 120 (that is, the non-functional surface 121 of the topmost memory array chip 124). In some embodiments, the height H3 of each third conductive contact 150 is greater than the respective heights H1 and H2 of each of the first conductive contact 130 and the second conductive contact 140. In some embodiments, the length L3 and width W3 of each third conductive contact 150 are between about 0.1 micrometers and about 2 micrometers. In detail, if the length L3 and the width W3 are less than about 0.1 μm, it may not be easy to control the bonding of the third conductive contact 150 during the manufacturing process; and if the length L3 and the width W3 are greater than about 2 μm, it may not be possible A high-density third conductive contact 150 and a high-speed memory device 100 are formed. In some embodiments, the third conductive contact 150 may include copper, gold, or other suitable conductive metal materials.

In some embodiments, the length X1 and the width Y1 of the peripheral wafer 110 are respectively greater than the length X2 and the width Y2 of the memory array chip stack 120, so that the third conductive contact 150 can be formed on the functional surface 113 of the peripheral wafer 110 and Around the memory array chip stack 120. In other words, since the length X1 and the width Y1 of the peripheral wafer 110 are respectively greater than the length X2 and the width Y2 of the memory array chip stack 120, a space is reserved on the peripheral wafer 110 for the third conductive contact 150 to be formed. In addition, since the length X1 and width Y1 of the peripheral wafer 110 are respectively greater than the length X2 and the width Y2 of the memory array chip stack 120, it is not necessary to accurately bond the memory array chip stack 120 to the peripheral wafer 110. Alignment, and therefore can save the cost for alignment. In some embodiments, the third conductive contacts 150 are arranged in an array on the peripheral wafer 110, as shown in FIG. 1A. In some embodiments, the number of third conductive contacts 150 adjacent to each side of the memory array chip stack 120 (for example, the first side S1, the second side S2, the third side S3, or the fourth side S4) Can be different.

In some embodiments, the memory device 100 further includes a first dielectric layer 160 that extends laterally above the peripheral wafer 110 and surrounds the memory array chip stack 120. In some embodiments, the first dielectric layer 160 further surrounds the first conductive contact 130, the second conductive contact 140 and the third conductive contact 150. In other words, the first dielectric layer 160 is completely filled in the space between the peripheral wafer 110, the memory array chip stack 120, the first conductive contact 130, the second conductive contact 140, and the third conductive contact 150, To electrically insulate the above-mentioned components. In some embodiments, the top surface 161 of the first dielectric layer 160 is substantially aligned with the top surface TS of the memory array chip stack 120 (that is, the non-functional surface 121 of the topmost memory array chip 124) and the third conductive layer. The top surface 151 of the contact 150 is coplanar. In some embodiments, the first dielectric layer 160 may include an organic material such as polyimide. In an alternative embodiment, the first dielectric layer 160 may include an inorganic material such as _{silicon dioxide (SiO 2) such as spin-on glass (SOG).}

According to the above, because at least one side of the memory array chip stack is configured in a stepped shape, a large number of first conductive contacts can be formed on the side of the memory array chip stack and located between the peripheral wafer and the memory array chip stack. between. In this way, a high-density and high-speed memory device can be formed. In addition, since the size of the peripheral wafers (that is, the length and width) is larger than the size of the memory array chip stack, when the memory array chip stack is bonded to the peripheral wafer, precise alignment is not required, which can save The cost used for alignment.

Figures 2A, 3A, 4A, 5A, 6A, and 7A show top views of the steps of the method of manufacturing the memory device 100 according to some embodiments of the present disclosure. FIGS. 2B and 2C, 3B and 3C, 4B and 4C, 5B and 5C, 6B and 6C, and 7B and 7C are cross-sectional views of various steps of the method of manufacturing the memory device 100 according to some embodiments of the present disclosure. It should be understood that the connection relationship, materials and effects of the components that have been described will not be repeated, and will be described first. In the following description, a method of manufacturing the memory device 100 will be explained.

Please refer to FIGS. 2A to 2C, where FIG. 2B is a cross-sectional view taken along the line 2B-2B' of FIG. 2A, and FIG. 2C is a cross-sectional view taken along the line 2C-2C' of FIG. 2A. In step S10, a carrier board 170 is provided. In some embodiments, the carrier 170 may be a silicon dioxide wafer, but it is not used to limit the disclosure. After the carrier 170 is provided, the plurality of memory array chips 124 are then face-to-back (that is, the silicon substrate 122 of each memory array chip 124 faces the functional surface 123 of the adjacent memory array chip 124) It is stacked on the surface 171 of the carrier 170 in an offset manner to form a plurality of memory array chip stacks 120 having a stepped/inverted stepped configuration. For example, the first side S1 and the second side S2 of each memory array chip stack 120 are configured in a stepped shape, and the third side S3 and the fourth side S4 are configured in an inverted stepped shape. In some embodiments, the directions of each memory array chip stack 120 are substantially the same, as shown in FIG. 2A.

Please refer to FIGS. 3A to 3C, where FIG. 3B is a cross-sectional view taken along the line 3B-3B' of FIG. 3A, and FIG. 3C is a cross-sectional view taken along the line 3C-3C' of FIG. 3A. In step S20, the first dielectric layer 160 is formed laterally above the carrier 170 and covers the memory array chip stack 120. After the first dielectric layer 160 is formed, the first conductive contact 130 and the second conductive contact 140 are formed in the first dielectric layer 160 and each memory array chip stack 120 is located between the first side S1 and the second side S2 Part of the function on the surface. In some embodiments, the first conductive contact 130 and the second conductive contact 140 are formed by removing a portion of the first dielectric layer 160 to form a functional surface 123 that exposes a portion of each memory array chip stack 120 The groove R is filled with conductive material to complete the groove R. In some embodiments, removing a portion of the first dielectric layer 160 is performed through a dry or wet etching process. In some embodiments, a hard mask (not shown) may be formed over a portion of the first dielectric layer 160 during the etching process to remove the exposed portion of the first dielectric layer 160 that is not covered by the hard mask . In addition, a planarization process such as a chemical mechanical polishing process may be performed to remove the remaining conductive material and the first dielectric layer 160, so that the top surface 163 of the first dielectric layer 160 (which will be formed in the memory device 100 The bottom surface 163 of the first dielectric layer 160 is substantially connected to the top surface 133 of the first conductive contact 130 (which will become the bottom surface 133 of the first conductive contact 130 after the memory device 100 is formed) and the bottom surface of the second conductive contact 140 The top surface 143 (the bottom surface 143 that will become the second conductive contact 140 after the memory device 100 is formed) is coplanar.

In some embodiments, the heights H1 and H2 of the first conductive contact 130 and the second conductive contact 140 formed on different memory array chips 124 can be different, and the memory array formed closer to the carrier 170 The first conductive contact 130 and the second conductive contact 140 on the chip 124 have larger heights H1, H2, and the first conductive contact 130 and the second conductive contact 130 and the second conductive contact formed on the memory array chip 124 farther from the carrier 170 The contact 140 has a small height H1, H2. In some embodiments, a plurality of conductive pads (not shown) can be pre-formed on the functional surface 123 of each memory array chip 124, so that the first conductive contact 130 and the second conductive contact 140 can be directly formed on the conductive pad , To form an electrical connection. In some embodiments, the conductive pad may include copper, gold, or other suitable conductive metal materials. In a preferred embodiment, the conductive pad, the first conductive contact 130, and the second conductive contact 140 may include the same material.

Please refer to FIGS. 4A to 4C, where FIG. 4B is a cross-sectional view taken along the line 4B-4B' of FIG. 4A, and FIG. 4C is a cross-sectional view taken along the line 4C-4C' of FIG. 4A. In step S30, the structures in FIG. 3A to FIG. 3C are separated by the memory array chip stack 120. In detail, the first dielectric layer 160 and the carrier 170 located between the memory array chip stack 120 are vertically cut to form the carrier 170 including a memory array chip stack 120 thereon.

Please refer to FIGS. 5A to 5C, where FIG. 5B is a cross-sectional view taken along the line 5B-5B' of FIG. 5A, and FIG. 5C is a cross-sectional view taken along the line 5C-5C' of FIG. 5A. In step S40, the carrier 170 (see FIG. 4B) is separated from the memory array chip stack 120 and the first dielectric layer 160, so that the bottom surface 161 of the first dielectric layer 160 (after the memory device 100 is formed) The top surface 161 of the first dielectric layer 160 and the bottom surface TS of the memory array chip stack 120 (which will become the top surface TS of the memory array chip stack 120 after the memory device 100 is formed) are exposed. In some embodiments, step S40 can be selectively performed, which will be described in detail later.

Please refer to FIGS. 6A to 6C, where FIG. 6B is a cross-sectional view taken along the line 6B-6B' of FIG. 6A, and FIG. 6C is a cross-sectional view taken along the line 6C-6C' of FIG. 6A. In step S50, the peripheral wafer 110 is provided, and then the structures shown in FIGS. 5A to 5C are inverted (that is, arranged in an upside-down manner) on the functional surface 113 of the peripheral wafer 110 so as to face-to-face ( Face-to-face, that is, the bonding of the functional surface 113 of the peripheral wafer 110 facing the functional surface of the memory array chip stack 120). In some embodiments, a plurality of conductive pads (not shown) can be pre-formed on the functional surface 113 of the peripheral wafer 110, so that the first conductive contact 130 and the second conductive contact 140 can be directly formed on the conductive pad to form Electrical connection. In some embodiments, the conductive pad may include copper, gold, or other suitable conductive metal materials. In a preferred embodiment, the conductive pad, the first conductive contact 130, and the second conductive contact 140 may include the same material.

During the bonding process, the conductive metal material at the connection between the conductive pad and the first conductive contact 130 and the connection between the conductive pad and the second conductive contact 140 is subjected to relatively high temperature and high pressure (relative to the normal temperature and pressure state, normal temperature and pressure, NTP). The diffusion may result in the connection between the conductive pad and the first conductive contact 130 and the connection between the conductive pad and the second conductive contact 140. In some embodiments, the conductive pad and the first conductive contact 130 are integrally formed after the bonding process, and there is no interface between the two. Similarly, the conductive pad and the second conductive contact 140 are integrally formed after the bonding process, and there is no interface between the two. Since this bonding process is a solderless process, the respective lengths L1, L2 and widths W1, W2 (see Figure 3A) of each of the first conductive contact 130 and the second conductive contact 140 can be very small (that is, (Between about 0.1 μm and about 2 μm), so as to provide a small resistance for the current passing through the first conductive contact 130 and the second conductive contact 140.

Please refer to FIGS. 7A to 7C, where FIG. 7B is a cross-sectional view taken along the line 7B-7B' of FIG. 7A, and FIG. 7C is a cross-sectional view taken along the line 7C-7C' of FIG. 7A. In step S60, the third conductive contact 150 is formed in the first dielectric layer 160 and on the functional surface 113 of the peripheral wafer 110. In some embodiments, the third conductive contact 150 is formed by removing part of the first dielectric layer 160 to form a groove R exposing a portion of the functional surface 113 of the peripheral wafer 110, and filling the groove R Conductive material to complete. In some embodiments, removing a portion of the first dielectric layer 160 is performed through a dry or wet etching process. In some embodiments, a hard mask (not shown) may be formed over a portion of the first dielectric layer 160 during the etching process to remove the exposed portion of the first dielectric layer 160 that is not covered by the hard mask . In addition, a planarization process such as a chemical mechanical polishing process may be performed to remove the remaining conductive material and the first dielectric layer 160, so that the top surface 161 of the first dielectric layer 160 is substantially stacked with the memory array chip The top surface TS of 120 (that is, the non-functional surface 121 of the topmost memory array chip 124) and the top surface 151 of the third conductive contact 150 are coplanar. After step S60 is completed, the memory device 100 as shown in FIG. 1A to FIG. 1C can be formed.

FIG. 8 is a cross-sectional view of a memory device 100a according to another embodiment of the present disclosure. At least one difference between the memory device 100a of FIG. 8 and the memory device 100 of FIG. 1B is that the memory device 100a further includes a second dielectric layer 180 extending laterally above the first dielectric layer 160 and covering the memory The bulk array wafer is stacked 120. In some embodiments, the third conductive contact 150 may further penetrate the second dielectric layer 180, so that the top surface 151 of the third conductive contact 150 is higher than the top surface TS of the memory array chip stack 120, and the third conductive contact 150 The top surface 151 of the conductive contact 150 is further exposed by the second dielectric layer 180. In some embodiments, the second dielectric layer 180 may include an organic material such as polyimide. In an alternative embodiment, the second dielectric layer 180 may include an inorganic material such as silicon dioxide of spin-on glass. In detail, when the material included in the second dielectric layer 180 is different from the material included in the first dielectric layer 160, an interface can be observed between the first dielectric layer 160 and the second dielectric layer 180 F; and when the material included in the second dielectric layer 180 is substantially the same as the material included in the first dielectric layer 160, the interface cannot be observed between the first dielectric layer 160 and the second dielectric layer 180 F, that is, the first dielectric layer 160 and the second dielectric layer 180 are integrally formed, and there is no interface F between them. However, when the memory device 100 is immersed in an acid solution (for example, a hydrogen fluoride solution), even if the material included in the second dielectric layer 180 is different from the material included in the first dielectric layer 160, it can still be used in the first dielectric layer. An interface F is observed between the dielectric layer 160 and the second dielectric layer 180.

In some embodiments, the second dielectric layer 180 may be formed before the formation of the third conductive contact 150 and after the face-to-face bonding process. In an alternative embodiment, the second dielectric layer 180 may be the carrier 170 in the aforementioned step S10 (see FIG. 2B). In detail, as described in the foregoing step S40, the step of detaching the carrier plate 170 can be selectively performed, and when the carrier plate 170 is not detached in step S40, the carrier plate 170 can be retained as the second step here. The dielectric layer 180. In this case, the second dielectric layer 180 may include substantially the same material as the carrier 170 (for example, silicon dioxide). Since the carrier plate 170 can be retained before the face-to-face bonding process, the convenience of placing the structures shown in FIGS. 5A to 5C upside down on the functional surface 113 of the peripheral wafer 110 can be improved.

FIG. 9 is a cross-sectional view of a memory device 100b according to another embodiment of the present disclosure. At least one difference between the memory device 100b in FIG. 9 and the memory device 100a in FIG. 8 is that the memory device 100b further includes a plurality of redistribution layers (RDLs) 190 in the second dielectric layer 180. And connected to the third conductive contact 150. In some embodiments, the redistribution layer 190 may include copper, gold, or other suitable conductive metal materials. In some embodiments, the thickness T3 of the second dielectric layer 180 in the memory device 100b is greater than the thickness T2 of the second dielectric layer 180 in the memory device 100a, so as to reserve space for the redistribution layer 190 to be formed .

FIG. 10 is a cross-sectional view of a memory device 100c according to another embodiment of the present disclosure. At least one difference between the memory device 100c of FIG. 10 and the memory device 100a of FIG. 8 is that the memory device 100c includes a plurality of dielectric layers 200 that extend laterally and are stacked on the peripheral wafer 110, instead of only including A dielectric layer (for example, the first dielectric layer 160) is located above the peripheral wafer 110. In addition, the dielectric layer 200 surrounds the memory array chip stack 120, the first conductive contact 130, the second conductive contact 140 (not shown), and the third conductive contact 150. In some embodiments, the dielectric layer 200 may be further inserted between the memory array chips 124 laterally. In other words, adjacent memory array chips 124 can be separated by the dielectric layer 200. For example, the dielectric layer 200 inserted between the topmost memory array chip 124 and the next-top memory array chip 124 can directly contact the functional surface 123 of the topmost memory array chip 124 and the next-top memory The non-functional surface 121 of the bulk array wafer 124. In some embodiments, the dielectric layer 200 may include an organic material such as polyimide. In an alternative embodiment, the dielectric layer 200 may include an inorganic material such as silicon dioxide of spin-on glass. In some embodiments, each dielectric layer 200 may include the same material. In other embodiments, each dielectric layer 200 may include different materials. In alternative embodiments, adjacent dielectric layers 200 may include different materials.

According to the above-mentioned embodiments of the present disclosure, since at least one side of the memory array chip stack is configured in a stepped shape, a large number of first conductive contacts can be formed on the side of the memory array chip stack and located between the peripheral wafers and the memory. Between array wafer stacks. In this way, a high-density and high-speed memory device can be formed. In addition, since the memory array chip stack is disposed above the peripheral wafer, and is not laterally adjacent to the peripheral wafer, the conductive patterns on the memory array chip stack and the conductive patterns on the peripheral wafer can be fabricated separately. In this way, the optimized conditions of the two processes (for example, thermal process) can be adjusted separately for the memory array chip stack and the surrounding wafers, so that the memory array chip stack and the surrounding wafer processes do not restrict each other And interference. In addition, since the size of the peripheral wafer is larger than the size of the memory array chip stack, when the memory array chip stack is bonded to the peripheral wafer in a face-to-face manner, it does not need to be precisely aligned, so it can save money. The cost of alignment. In addition, a stacked volatile working memory (DRAM or SRAM) chip with a controller can achieve high-bandwidth-memory (HBM) and high-speed read and write capabilities, and this disclosure uses through dielectric perforation (through dielectric Via) instead of through silicon via, it can bring the advantage of low cost. In addition, the number of input/output (I/O) of a stacked volatile working memory (DRAM or SRAM) chip can be greater than or equal to 1024.

Although this disclosure has been disclosed in the above implementation manner, it is not intended to limit this disclosure. Anyone who is familiar with this technique can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure is protected The scope shall be subject to those defined in the attached patent scope.

100, 100a, 100b, 100c: memory device 110: Peripheral wafer 112: Silicon substrate 113: functional surface 120: Memory array chip stacking 121: non-functional surface 122: Silicon substrate 123: functional surface 124: Memory Array Chip 130: first conductive contact 133: bottom surface (top surface) 140: second conductive contact 143: bottom surface (top surface) 150: third conductive contact 151: Top Surface 160: first dielectric layer 161: top surface (bottom surface) 163: bottom surface (top surface) 170: carrier board 171: Surface 180: second dielectric layer 190: Redistribution layer 200: Dielectric layer S1: First side S2: second side S3: Third side S4: Fourth side S: sidewall R: groove D: Horizontal distance F: Interface TS: Top surface (bottom surface) BS: bottom surface (top surface) L1~L3, X1~X2: length W1~W3, Y1~Y2: width T1~T3: thickness H1~H3: height S10~S60: steps 1B-1B'~7B-7B',1C-1C'~7C-7C': line segment

In order to make the above and other objectives, features, advantages and embodiments of the present disclosure more comprehensible, the description of the accompanying drawings is as follows: FIG. 1A shows a top view of a memory device according to some embodiments of the present disclosure; 1B shows a cross-sectional view of the memory device in FIG. 1A according to some embodiments of the present disclosure taken along line 1B-1B'; FIG. 1C shows a cross-sectional view of the memory device in FIG. 1A according to some embodiments of the present disclosure 1C-1C' cross-sectional view; FIG. 2A, FIG. 3A, FIG. 4A, FIG. 5A, FIG. 6A, and FIG. 7A illustrate the steps of the method of manufacturing a memory device according to some embodiments of the present disclosure The top view of Figures 2B and 2C, Figures 3B and 3C, Figures 4B and 4C, Figures 5B and 5C, Figures 6B and 6C, and Figures 7B and 7C show the memory according to some embodiments of the present disclosure Cross-sectional views of the manufacturing method of the device at each step; and FIGS. 8 to 10 are cross-sectional views of memory devices according to other embodiments of the present disclosure.

Domestic deposit information (please note in the order of deposit institution, date and number) none Foreign hosting information (please note in the order of hosting country, institution, date, and number) none

100: Memory device

110: Peripheral wafer

112: Silicon substrate

113: functional surface

120: Memory array chip stacking

121: non-functional surface

122: Silicon substrate

123: functional surface

124: Memory Array Chip

130: first conductive contact

150: third conductive contact

151: Top Surface

160: first dielectric layer

161: top surface

S1: First side

S3: second side

TS: top surface

BS: bottom surface

T1: thickness

H1, H3: height

Claims (10)

A memory device includes: a peripheral wafer with a functional surface, wherein the peripheral wafer includes controller logic; a stack of memory array chips arranged on the peripheral wafer and having a functional surface, wherein the peripheral wafer The functional surface of the wafer faces the functional surface of the memory array chip stack, a first side of the memory array chip stack is a stepped configuration, and a second side of the memory array chip stack is a step Shape configuration, and the second side is adjacent to the first side of the memory array chip stack, the memory array chip stack includes a plurality of memory array chips, and the memory array chips include non-volatile memory And a plurality of first conductive contacts, disposed on the first side of the memory array chip stack, and located between the functional surface of the peripheral wafer and the functional surface of the memory array chip stack, and connected to the The functional surface of the peripheral wafer and the functional surface of the memory array chip stack. A memory device includes: a peripheral wafer with a functional surface, wherein the peripheral wafer includes controller logic; a stack of memory array chips arranged on the peripheral wafer and having a functional surface, wherein the peripheral wafer The functional surface of the wafer faces the functional surface of the memory array chip stack, a first side of the memory array chip stack is configured in a stepped shape, and a second side of the memory array chip stack The side is a stepped configuration, and the second side is adjacent to the first side of the memory array chip stack, the memory array chip stack includes a plurality of memory array chips, and the memory array chips include volatile Memory; and a plurality of first conductive contacts disposed on the first side of the memory array chip stack and located between the functional surface of the peripheral wafer and the functional surface of the memory array chip stack, And connect the functional surface of the peripheral wafer and the functional surface of the memory array chip stack. The memory device according to claim 1 or 2, further comprising a plurality of second conductive contacts, arranged on the second side of the memory array chip stack, and located on the functional surface of the peripheral wafer and the memory Between the functional surfaces of the array chip stack, and connect the functional surface of the peripheral wafer and the functional surface of the memory array chip stack. The memory device according to claim 1 or 2, wherein a third side of the memory array chip stack relative to the first side is an inverted stepped configuration. The memory device according to claim 1 or 2, wherein the memory array chips are vertically stacked in a face-to-back manner. The memory device according to claim 1 or 2, wherein each of the memory array chips is composed of adjacent memory array chips One of them is exposed at the same interval. The memory device according to claim 1 or 2, wherein a length and a width of the peripheral wafer are respectively greater than a length and a width of the memory array chip stack. The memory device according to claim 1 or 2, further comprising a plurality of third conductive contacts arranged on the functional surface of the peripheral wafer and stacked around the memory array chip. The memory device according to claim 1 or 2, further comprising a first dielectric layer that extends laterally above the peripheral wafer and surrounds the memory array chip stack and the first conductive contacts. The memory device according to claim 1 or 2, wherein a fourth side of the memory array chip stack relative to the second side is an inverted stepped configuration.

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