TWI433284B - Stackable package and method for making the same and semiconductor package - Google Patents

Description

Stackable package structure, manufacturing method thereof and semiconductor package structure

The present invention relates to a package structure and a method of fabricating the same, and more particularly to a stackable package structure, a method of fabricating the same, and a stacked semiconductor package structure.

Referring to Figure 1, a cross-sectional view of a first stackable package structure is shown. The first stackable package structure 1 includes a substrate 11, a wafer 12, a plurality of wires 13, a gel 14 and a plurality of solder balls 15. The substrate 11 includes a first surface 111 , a second surface 112 , a plurality of through holes 113 , and a plurality of electrical connection points 114 . The through holes 113 extend through the substrate 11 , and the electrical connection points 114 are located at the periphery of the first surface 111 of the substrate 11 and are exposed on the first surface 111 . The wafer 12 is located on the first surface 111 of the substrate 11. The wires 13 are electrically connected to the substrate 11 and the wafer 12. The encapsulant 14 covers a portion of the substrate 11, the wafer 12, and the wires 13. The solder balls 15 are located on the second surface 112 of the substrate 11.

The disadvantages of the first stackable package structure 1 are as follows. The electrical connection points 114 are located on the periphery of the first surface 111 of the substrate 11, so that the distribution of the electrical connection points 114 does not conform to the distribution of the solder balls of a standard memory, and the stack cannot be stacked. A standard memory is at the top of the conventional first stackable package structure 1.

Referring to Figure 2, a cross-sectional view of a conventional second stackable package structure is shown. The second stackable package structure 2 includes a first substrate 21, a first wafer 22, a primer 23, a dielectric layer 24, a second substrate 25, a plurality of wires 26, and a gel. 27 and a plurality of solder balls 28. The first substrate 21 has a first surface 211 and a second surface 212. The first wafer 22 is located on the first substrate 21 and includes a plurality of first bumps 221 . The primer 23 covers the first bumps 221 of the first wafer 22 . The dielectric layer 24 is on the first wafer 22. The second substrate 25 is disposed on the dielectric layer 24 and includes a first surface 251 , a second surface 252 , and a plurality of electrical connection points 253 . The first surface 251 contacts the dielectric layer 24 . Electrical connection points 253 are located on the second surface 252. The wires 26 are electrically connected to the second substrate 25 and the first substrate 21. The encapsulant 27 covers the first surface 211 of the first substrate 21, the first wafer 22, the dielectric layer 24, the first surface 251 of the second substrate 25, and the wires 26, and the first surface is exposed. The electrical connection point 253 of the two substrates 25 is obtained. The solder balls 28 are located on the second surface 212 of the first substrate 21.

The disadvantages of the conventional second stackable package structure 2 are as follows. The package structure 2 can be stacked by a standard memory, but an additional dielectric layer 24 is disposed between the first wafer 22 and the second substrate 25 to make the thickness of the package structure 2. Increase and increase costs.

Therefore, it is necessary to provide a stackable package structure, a method of fabricating the same, and a semiconductor package structure to solve the above problems.

The invention provides a stackable package structure comprising a substrate, a wafer, a gel, a circuit layer and an insulating material. The substrate has an upper surface, a lower surface and at least one first bonding pad, and the first bonding pad is located on the upper surface. The wafer is located on an upper surface of the substrate and is electrically connected to the substrate. The encapsulant covers the upper surface of the substrate and the wafer, and the encapsulant has an upper surface. The circuit layer is located on the upper surface of the encapsulant, and a portion of the circuit layer is directly above the wafer. The circuit layer includes at least one electrical connection point electrically connected to the first pad. The insulating material covers the circuit layer and exposes the electrical connection point.

The present invention further provides a method for fabricating a stackable package structure, comprising the steps of: (a) providing a substrate having an upper surface, a lower surface, and at least one first bonding pad, the first bonding pad being located The upper surface; (b) a wafer is disposed on the upper surface of the substrate, the wafer is electrically connected to the substrate; (c) a gel is formed to cover the upper surface of the substrate and the wafer, the sealant has An upper surface; (d) forming at least one first hole, at least one second hole and at least one groove on the upper surface of the sealant by using a laser, the position of the first hole is corresponding to the first welding a pad, the second hole is located above the wafer, the groove is located between the first hole and the second hole, and the second hole and the bottom of the groove are opposite to the wafer Having a spacing between the upper surfaces; (e) forming a conductive metal on the upper surface of the encapsulant; (f) removing conductive metal located outside the first bore, the second bore, and the trench to respectively Forming a first conductor layer, a second conductor layer and a third conductor layer, the first hole and the first Forming at least one via hole, the second hole and the second conductor layer forming at least one electrical connection point, the trench and the third conductor layer forming at least one conductive trace, the electrical connection point and the The conductive traces form a circuit layer, and the first pad is electrically connected to the electrical connection point through the via hole and the conductive trace; and (g) an insulating material is formed to cover the circuit layer, and The electrical connection point is revealed.

The present invention further provides a method for fabricating a stackable package structure, comprising the steps of: (a) providing a substrate having an upper surface, a lower surface, and at least one first bonding pad, the first bonding pad being located The upper surface; (b) a wafer is disposed on the upper surface of the substrate, the wafer is electrically connected to the substrate; (c) a gel is formed to cover the upper surface of the substrate and the wafer, the sealant has An upper surface; (d) forming at least one first hole and at least one second hole on the upper surface of the sealant by using a laser, the position of the first hole corresponds to the first pad, and the second The drilling hole is located above the wafer, and a bottom of the second drilling hole has a spacing from an upper surface of the wafer; (e) a photoresist is formed on the upper surface of the sealing body, the photoresist has a plurality of Opening to expose the first hole, the second hole and a portion of the upper surface of the sealant; (f) forming a conductive metal to expose the first hole, the second hole and a portion of the sealant An upper surface to respectively form a first conductor layer, a second conductor layer and at least one guide The first hole and the first conductor layer form at least one via hole, and the second hole and the second conductor layer form at least one electrical connection point, and the electrical connection point and the conductive trace form a circuit layer, and the first pad is electrically connected to the electrical connection point through the via hole and the conductive trace; (g) removing the photoresist; and (h) forming an insulating material to cover The circuit layer and the electrical connection point are revealed.

The present invention further provides a semiconductor package structure including a stackable package structure and at least one upper package structure. The stackable package structure comprises a substrate, a wafer, a gel, a circuit layer and an insulating material. The substrate has an upper surface, a lower surface and at least one first bonding pad, and the first bonding pad is located on the upper surface. The wafer is located on an upper surface of the substrate and is electrically connected to the substrate. The encapsulant covers the upper surface of the substrate and the wafer, and the encapsulant has an upper surface. The circuit layer is located on the upper surface of the encapsulant, and a portion of the circuit layer is directly above the wafer. The circuit layer includes at least one electrical connection point electrically connected to the first pad. The insulating material covers the circuit layer and exposes the electrical connection point. The upper package structure is located on the stackable package structure and electrically connected to the stackable package structure.

The invention further provides a stackable package structure comprising a substrate, a wafer, a gel, a circuit layer and an insulating material. The substrate has an upper surface, a lower surface and at least one first bonding pad, and the first bonding pad is located on the upper surface. The wafer is located on an upper surface of the substrate and is electrically connected to the substrate. The encapsulant covers the upper surface of the substrate and the wafer. The encapsulant has an upper surface and at least one via hole, and the position of the via hole corresponds to the first pad. The circuit layer is located on the upper surface of the encapsulant, the circuit layer includes at least one electrical connection point and at least one conductive trace, and the electrical connection point is electrically connected to the first solder through the conductive trace and the via hole a pad, the depth of the electrical connection point is less than the depth of the via hole, a bottom of the electrical connection point and a bottom of the conductive trace have a spacing from an upper surface of the wafer, and the electrical connection point includes At least one first electrical connection point, the at least one first electrical connection point being directly above the wafer. The insulating material covers the circuit layer, and the electrical connection point and the guiding hole are exposed, and an upper surface of the insulating material is flush with the top of the sealing body.

The invention also provides a stackable package structure comprising a gel body, a circuit layer, an insulating material, a wafer and a substrate. The encapsulant has a bonding surface and at least one via hole, the bonding surface exposing at least one electrical connection point. The circuit layer is located on the bonding surface of the encapsulant, and includes the electrical connection point and the at least one conductive trace. The conductive trace is electrically connected to the via hole and the electrical connection point. The insulating material fills the via and covers the conductive trace. The wafer is located within the encapsulant and the wafer is located below the circuit layer. The substrate has a first surface, a second surface, and at least one first pad. The first pad is located on the first surface, and the first surface of the substrate is used to carry the wafer and the encapsulant. The chip is electrically connected to the substrate, and the first pad of the substrate is electrically connected to the electrical connection points through the via hole and the conductive trace.

Therefore, in the present invention, the electrical connection point is located above the wafer, and the distribution thereof conforms to the distribution of the solder balls of a standard memory, and the standard memory is stacked in the stackable type of the present invention. The top of the package structure. Furthermore, the conductor layer avoids the use of additional dielectric layers and reduces the overall thickness of the stackable package structure of the present invention.

Referring to Figures 3 through 16, there are shown schematic views of a method of fabricating a first embodiment of the stackable package structure of the present invention. Referring to FIG. 3, a substrate 31 is provided. The substrate 31 has an upper surface 311, a lower surface 312, at least one first bonding pad 313, and a plurality of second bonding pads 314. The first bonding pad 313 and the second bonding pads are provided. A pad 314 is located on the upper surface 311. Referring to FIG. 4, at least one first solder ball 32 is provided on the first pad 313 of the substrate 31.

Referring to FIG. 5, a wafer is disposed on the upper surface 311 of the substrate 31, and the wafer is electrically connected to the substrate 31. In the present embodiment, the wafer is a wire wafer 33 that is electrically connected to the second pad 314 of the substrate 31 through a plurality of wires 331 and attached to the substrate 31 by an adhesive layer 332. . However, in other applications, referring to FIG. 6 , the wafer system can be a flip chip 34 including a back surface 341 , an active surface 342 , and a plurality of bumps 343 . The bumps 343 are located on the active surface 342 . The flip chip 34 is electrically connected to the second pad 314 of the substrate 31 through the bumps 343 .

Referring to FIG. 7, a colloid 35 is formed to cover the upper surface 311 of the substrate 31 and the wire bonding die 33. The encapsulant 35 has an upper surface 351. Referring to FIG. 8 and FIG. 9 , at least one first drilling hole 352 , at least one second drilling hole 353 and at least one groove 354 are formed by using a laser on the upper surface 351 of the sealing body 35 , and the position of the first drilling hole 352 is Corresponding to the first pad 313, the second hole 353 is located above the wire wafer 33, the groove 354 is located between the first hole 352 and the second hole 353, and the second The hole 353 and the bottom of the groove 354 have a spacing from the upper surface 333 of one of the wire wafers 33. In this embodiment, the depth of the second bore 353 is less than the depth of the first bore 352, and the first bore 352 reveals the first solder ball 32. However, in other applications, the thickness of the first pad 313 is greater than or equal to 20 μm, and the first solder ball 32 may not be used, and the first pad 352 exposes the first pad 313.

Referring to FIG. 10, a conductive metal 36 is formed on the upper surface 351 of the encapsulant 35. Referring to FIG. 11 and FIG. 12, the conductive metal 36 outside the first hole 352, the second hole 353 and the groove 354 is removed to form a first conductor layer 361 and a second conductor layer 362, respectively. And a third conductor layer 363, the first hole 352 and the first conductor layer 361 form at least one via hole 355, and the second hole 353 and the second conductor layer 362 form at least one electrical connection point. In this embodiment, the electrical connection point includes a plurality of first electrical connection points 382. However, in other embodiments, the electrical connection point further includes a plurality of second electrical connection points 384 (FIG. 20). The first electrical connection points 382 are located directly above the wire bonding die 33, and the second electrical connection points 384 are located at opposite positions outside the wire bonding die 33. The trench 354 and the third conductor layer 363 form at least one conductive trace 383. The electrical connection point (the first electrical connection point 382 and the second electrical connection point 384) and the conductive trace 383 form a circuit. The layer 38 is electrically connected to the electrical connection point (the first electrical connection point 382 and the second electrical connection point 384) through the via 355 and the conductive trace 383.

In the embodiment, the first conductive layer 361 is electrically connected to the first pad 313 through the first solder ball 32 . In this embodiment, the bottom of the electrical connection point (the first electrical connection point 382 and the second electrical connection point 384) and the bottom of the conductive trace 383 and the upper surface 333 of the wire bonding die 33 have a spacing. Referring to FIG. 13 and FIG. 14, an insulating material 39 is formed to cover the circuit layer 38, and the electrical connection point (the first electrical connection point 382 and the second electrical connection point 384) is exposed, and the present invention is formed. Stacked package structure 3. In the embodiment, the insulating material 39 fills the first hole 352 and the groove 354 to expose an upper end of the first conductor layer 361, and an upper surface 391 of the insulating material 39 and the sealing body 35 The top is flush.

Referring to FIG. 15, a plurality of second solder balls 41 are formed on the lower surface 312 of the substrate 31. Referring to FIG. 16, a schematic diagram of the package structure 3 stacked on an upper package structure 6 is shown. In this embodiment, the upper package structure 6 is a Ball Grid Array Package, which includes a plurality of third solder balls 61. Each of the third solder balls 61 is electrically connected and directly in contact. Each electrical connection point of the circuit layer 38 (the first electrical connection point 382 and the second electrical connection point 384). However, in other applications, the upper package structure 6 is not limited to a ball grid array package structure, and the package structure 3 may also stack more than two upper package structures 9, and the upper package structures 9 are side by side. As shown in Figure 17.

Referring again to Figure 13, a cross-sectional view of a first embodiment of a stackable package structure of the present invention is shown. The stackable package structure 3 includes a substrate 31, at least one first solder ball 32, a wafer, a gel 35, a circuit layer 38, and an insulating material 39. The substrate 31 has an upper surface 311 , a lower surface 312 , at least one first bonding pad 313 , and a plurality of second bonding pads 314 . The first bonding pads 313 and the second bonding pads 314 are located on the upper surface 311 . The first solder ball 32 is located on the first pad 313 of the substrate 31.

The wafer is located on the upper surface 311 of the substrate 31 and electrically connected to the substrate 31. In the present embodiment, the wafer is a wire wafer 33 that is electrically connected to the second pad 314 of the substrate 31 through a plurality of wires 331 and attached to the substrate 31 by an adhesive layer 332. .

The sealing body 35 covers the upper surface 311 of the substrate 31 and the wire bonding die 33. The sealing body 35 includes an upper surface 351, at least one first drilling hole 352, at least one second drilling hole 353 and at least one groove 354. . The first hole 352 is exposed to the first solder ball 32. The depth of the second hole 353 is smaller than the depth of the first hole 352, and the bottom of the second hole 353 and the groove 354 is The upper surface 333 of one of the wire wafers 33 has a pitch.

The circuit layer 38 is located on the upper surface 351 of the encapsulant 35, and a portion of the circuit layer 38 is located directly above the wire bonding die 33. In this embodiment, the circuit layer 38 includes a first conductor layer 361, a second conductor layer 362, and a third conductor layer 363, which are simultaneously formed. The first conductor layer 361 is located in the first hole 352, and the first hole 352 and the first conductor layer 361 form a guiding hole 355 of the sealing body 35. The first conductor layer 361 is electrically connected to the first pad 313 through the first solder ball 32 . The position of the via 355 corresponds to the first pad 313. The second conductive layer 362 is located in the second hole 353, and the second hole 353 and the second conductor layer 362 form at least one electrical connection point of the circuit layer 38 (the first electrical connection point 382) And a second electrical connection point 384). The third conductor layer 363 is located in the trench 354, and the trench 354 and the third conductor layer 363 form at least one conductive trace 383 of the circuit layer 38.

The circuit layer 38 further includes the electrical connection point (the first electrical connection point 382 and the second electrical connection point 384) and the conductive trace 383. The electrical connection point (the first electrical connection point 382 and the The second electrical connection point 384 is electrically connected to the first pad 313 through the conductive trace 383 and the via 355. In this embodiment, the bottom of the electrical connection point (the first electrical connection point 382 and the second electrical connection point 384) and the bottom of the conductive trace 383 and the upper surface 333 of the wire bonding die 33 have A pitch, and the first electrical connection points 382 are located directly above the wire bonding die 33. The insulating material 39 covers the circuit layer 38 and exposes the electrical connection point (the first electrical connection point 382 and the second electrical connection point 384). The insulating material 39 fills the first hole 352 and the groove 354 to expose an upper end of the first conductor layer 361, and an upper surface 391 of the insulating material 39 is flush with the top of the sealing body 35.

Referring again to Figure 13, a cross-sectional view of a first embodiment of a stackable package structure of the present invention is shown. The stackable package structure 3 includes a glue body 35, a circuit layer 38, an insulator 39, a wafer, and a substrate 31. The encapsulant 35 has a bonding surface (ie, the upper surface 351) and at least one via 355. The bonding surface (ie, the upper surface 351) exposes at least one electrical connection point (the first electrical connection point 382 and the second electrical property). Connection point 384). The circuit layer 38 is located on the bonding surface (ie, the upper surface 351) of the encapsulant 35, and includes the electrical connection point (the first electrical connection point 382 and the second electrical connection point 384) and the at least one conductive trace 383. The conductive trace 383 is electrically connected to the via 355 and the electrical connection point (the first electrical connection point 382 and the second electrical connection point 384). The insulating material 39 fills the via 355 and covers the conductive trace 383. The wafer is located within the encapsulant 35 and the wafer is located below the circuit layer 38. The substrate 31 has a first surface (ie, an upper surface 311), a second surface (ie, a lower surface 312), and at least a first bonding pad 313. The first bonding pad 313 is located on the first surface (ie, the upper surface) 311) The first surface (ie, the upper surface 311) of the substrate 31 is used to carry the wafer and the encapsulant 35. The wafer is electrically connected to the substrate 31, and the first pad 313 of the substrate 31 passes through the substrate. The via 355 and the conductive trace 383 are electrically connected to the electrical connection points (the first electrical connection point 382 and the second electrical connection point 384).

Referring further to Figure 13, a cross-sectional view of a first embodiment of a stackable package structure of the present invention is shown. The stackable package structure 3 includes a substrate 31, at least one first solder ball 32, a wafer, a gel 35, a circuit layer 38, and an insulating material 39. The substrate 31 has an upper surface 311 , a lower surface 312 , at least one first bonding pad 313 , and a plurality of second bonding pads 314 . The first bonding pads 313 and the second bonding pads 314 are located on the upper surface 311 . The first solder ball 32 is located on the first pad 313 of the substrate 31.

The wafer is located on the upper surface 311 of the substrate 31 and electrically connected to the substrate 31. In the present embodiment, the wafer is a wire wafer 33 that is electrically connected to the second pad 314 of the substrate 31 through a plurality of wires 331 and attached to the substrate 31 by an adhesive layer 332. . The encapsulant 35 covers the upper surface 311 of the substrate 31 and the wire bonding die 33. The encapsulant 35 includes an upper surface 351.

The circuit layer 38 is located on the upper surface 351 of the encapsulant 35. The circuit layer 38 includes at least one electrical connection point, at least one conductive trace 383, and a connection circuit layer (ie, the first conductor layer 361). The electrical connection point is electrically connected to the first pad 313 through the conductive trace 383 and the connection layer (ie, the first conductor layer 361). In this embodiment, the electrical connection point includes a plurality of first electrical connection points 382. However, in other embodiments, the electrical connection point further includes a plurality of second electrical connection points 384 (FIG. 20). The first electrical connection points 382 are located directly above the wire bonding die 33, and the second electrical connection points 384 are located at opposite positions outside the wire bonding die 33.

In this embodiment, the bottom of the electrical connection point (the first electrical connection point 382 and the second electrical connection point 384) and the bottom of the conductive trace 383 and the upper surface 333 of the wire bonding die 33 have a spacing.

The conductive trace 383 connects the electrical connection point (the first electrical connection point 382 and the second electrical connection point 384) and the connection line layer (ie, the first conductor layer 361). The conductive trace 383 is parallel to the lower surface 312 of the substrate 31 and is positioned lower than the upper surface 351 of the sealant 35. However, in other applications, the conductive trace 383 is located on the upper surface 351 of the encapsulant 35 (Fig. 30).

The connection line layer (ie, the first conductor layer 361) has an angle with the conductive trace 383. The bottom of the connecting circuit layer (ie, the first conductive layer 361) is lower than the bottom of the electrical connection point (the first electrical connection point 382 and the second electrical connection point 384), and directly contacts and covers the first The solder ball 32 is electrically connected to the first pad 313 through the first solder ball 32. However, in other applications, the thickness of the first pad 313 may be greater than or equal to 20 μm, and the connection layer (ie, the first conductor layer 361) directly contacts and covers the first pad 313.

The insulating material 39 covers the circuit layer 38 and exposes the electrical connection point (the first electrical connection point 382 and the second electrical connection point 384). In this embodiment, the insulating material 39 covers the conductive trace 383 and the connecting circuit layer (ie, the first conductive layer 361), and exposes an upper end of the connecting circuit layer (ie, the first conductive layer 361), and the insulating One of the upper surfaces 391 of the material 39 is flush with the top of the sealant 35.

Referring again to Figure 16, a cross-sectional view of a semiconductor package structure of the present invention is shown. The semiconductor package structure 7 includes a stackable package structure and at least one upper package structure 6. The stackable package structure is the same as the first embodiment of the stackable package structure 3 of the present invention. The upper package structure 6 is located on the stackable package structure 3 and electrically connected to the stackable package structure 3.

Referring to Figure 18, there is shown a cross-sectional view of a second embodiment of the stackable package structure of the present invention. The package structure 4 of the present embodiment is substantially the same as the package structure 3 (FIG. 13) of the first embodiment, wherein the same elements are given the same reference numerals. The difference between this embodiment and the first embodiment is that the structure of the wafer is different. In this embodiment, the wafer is a flip chip 34, which includes a back surface 341, an active surface 342, and a plurality of bumps 343. The bumps 343 are located on the active surface 342, and the flip chip The 34 series is electrically connected to the second pad 314 of the substrate 31 through the bumps 343.

Referring to Figure 19, there is shown a cross-sectional view of a third embodiment of the stackable package structure of the present invention. The package structure 5 of the present embodiment is substantially the same as the package structure 3 (FIG. 13) of the first embodiment, wherein the same elements are given the same reference numerals. The difference between this embodiment and the first embodiment is that the package structure 5 does not include the first solder ball 32. In this embodiment, the thickness of the first pad 313 is greater than or equal to 20 μm, the first hole 352 exposes the first pad 313, and the first conductor layer 361 directly contacts the first pad. 313.

Referring to Figure 20, there is shown a cross-sectional view of a fourth embodiment of the stackable package structure of the present invention. The package structure 10 of the present embodiment is substantially the same as the package structure 3 (FIG. 13) of the first embodiment, wherein the same elements are given the same reference numerals. The difference between the embodiment and the first embodiment is that the electrical connection point of the package structure 6 further includes at least one second electrical connection point 384, and the at least one second electrical connection point 384 is located outside the wire bonding die 33. Relative position.

Referring to Figures 21 to 30, there are shown schematic views of a manufacturing method of a fifth embodiment of the stackable package structure of the present invention. Referring to FIG. 21, a substrate 31 is provided. The substrate 31 has an upper surface 311, a lower surface 312, at least one first bonding pad 313, and a plurality of second bonding pads 314. The first bonding pad 313 and the second bonding pads are provided. A pad 314 is located on the upper surface 311. Referring to FIG. 22, at least one first solder ball 32 is preferably provided on the first pad 313 of the substrate 31.

Referring to FIG. 23, a wafer is disposed on the upper surface 311 of the substrate 31, and the wafer is electrically connected to the substrate 31. In the present embodiment, the wafer is a wire wafer 33 that is electrically connected to the second pad 314 of the substrate 31 through a plurality of wires 331 and attached to the substrate 31 by an adhesive layer 332. . However, in other applications, referring to FIG. 24, the wafer system can be a flip chip 34 including a back surface 341, an active surface 342, and a plurality of bumps 343. The bumps 343 are located on the active surface 342. The flip chip 34 is electrically connected to the second pad 314 of the substrate 31 through the bumps 343 .

Referring to FIG. 25, a colloid 35 is formed to cover the upper surface 311 of the substrate 31 and the wire bonding wafer 33. The encapsulant 35 has an upper surface 351. Referring to FIG. 26, at least one first drilling hole 352 and at least one second drilling hole 353 are formed on the upper surface 351 of the sealing body 35 by a laser. The position of the first drilling hole 352 corresponds to the first bonding pad 313. The second hole 353 is located above the wafer, and a bottom of the second hole 353 has a distance from an upper surface 333 of the wire wafer 33. In the embodiment, the first hole 352 exposes the first solder ball 32. The depth of the second bore 353 is less than the depth of the first bore 352.

Referring to FIG. 27, a photoresist 37 is formed on the upper surface 351 of the encapsulant 35. The photoresist 37 has a plurality of openings to expose the first hole 352, the second hole 353 and a portion of the encapsulant 35. Surface 351. Referring to FIG. 28, a conductive metal 36 is formed on the exposed first hole 352, the second hole 353, and a portion of the upper surface 351 of the sealant 35 to simultaneously form a first conductor layer 361 and a second conductor. The layer 362 and the at least one conductive trace 383, the first hole 352 and the first conductor layer 361 form at least one via hole 355, and the second hole 353 and the second conductor layer 362 form at least one electrical connection point. The electrical connection point and the conductive trace 383 form a circuit layer 38, and the first pad 313 is electrically connected to the electrical connection point through the via 355 and the conductive trace 383. In this embodiment, the electrical connection point includes a plurality of first electrical connection points 382. However, in other embodiments, the electrical connection point further includes a plurality of second electrical connection points 384 (FIG. 20). The first electrical connection points 382 are located directly above the wire bonding die 33, and the second electrical connection points 384 are located at opposite positions outside the wire bonding die 33. In this embodiment, the conductive metal 36 is formed by sputtering, and the first conductive layer 361 is electrically connected to the first bonding pad 313 through the first solder ball 32, and the electrical connection point (the first A bottom of an electrical connection point 382 and a second electrical connection point 384) and a bottom of the conductive trace 383 have a spacing from an upper surface 333 of the wire bonding die 33.

Referring to Figure 29, the photoresist 37 is removed (Figure 28). Referring to FIG. 30, an insulating material 39 is formed to cover the circuit layer 38, and the electrical connection points (the first electrical connection point 382 and the second electrical connection point 384) are exposed. In the embodiment, the insulating material 39 fills the first hole 352 and exposes an upper end of the first conductor layer 361. Then, a plurality of second solder balls (not shown) are formed on the lower surface 312 of the substrate 31, and at least one upper package structure (not shown) is stacked on the package structure 8.

Therefore, in the present invention, the electrical connection point is located above the wafer (the wire wafer 33 or the flip chip 34), and the distribution thereof conforms to the distribution of the solder balls of a standard memory. The standard memory can be stacked on top of the stackable package structures 3, 4, 5 of the present invention. Moreover, the first via 355 can avoid the use of an additional dielectric layer 24 (FIG. 2), while reducing the overall thickness of the stackable package structures 3, 4, 5 of the present invention.

However, the above embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims.

1. . . The first stackable package structure

2. . . The second stackable package structure

3. . . First embodiment of the stackable package structure of the present invention

4. . . Second embodiment of the stackable package structure of the present invention

5. . . Third embodiment of the stackable package structure of the present invention

6. . . Upper package structure

7. . . Semiconductor package structure of the invention

8. . . Fifth embodiment of the stackable package structure of the present invention

9. . . Upper package structure

10. . . Fourth embodiment of the stackable package structure of the present invention

11. . . Substrate

12. . . Wafer

13. . . wire

14. . . Sealant

15. . . Solder ball

twenty one. . . First substrate

twenty two. . . First wafer

twenty three. . . Primer

twenty four. . . Dielectric layer

25. . . Second substrate

26. . . wire

27. . . Sealant

28. . . Solder ball

31. . . Substrate

32. . . First solder ball

33. . . Wire wafer

34. . . Flip chip

35. . . Sealant

36. . . Conductive metal

37. . . Photoresist

38. . . Circuit layer

39. . . Insulating material

41. . . Second solder ball

61. . . Third solder ball

111. . . First surface

112. . . Second surface

113. . . Through hole

114. . . Electrical connection point

211. . . First surface

212. . . Second surface

221. . . First bump

251. . . First surface

252. . . Second surface

253. . . Electrical connection point

311. . . Upper surface

312. . . lower surface

313. . . First pad

314. . . Second pad

331. . . wire

332. . . Adhesive layer

333. . . Upper surface

341. . . back

342. . . Active surface

343. . . Bump

351. . . Upper surface

352. . . First hole

353. . . Second hole

354. . . Trench

355. . . Guide hole

361. . . First conductor layer

362. . . Second conductor layer

363. . . Third conductor layer

382. . . First electrical connection point

383. . . Conductive trace

384. . . Second electrical connection point

391. . . Upper surface

1 shows a schematic cross-sectional view showing a conventional first stackable package structure;

2 is a cross-sectional view showing a conventional second stackable package structure;

3 to 16 are schematic views showing a manufacturing method of a first embodiment of the stackable package structure of the present invention;

17 is a cross-sectional view showing a first embodiment of a stackable package structure of the present invention, wherein the package structure is stacked with two upper package structures;

Figure 18 is a cross-sectional view showing a second embodiment of the stackable package structure of the present invention;

Figure 19 is a cross-sectional view showing a third embodiment of the stackable package structure of the present invention;

20 is a cross-sectional view showing a fourth embodiment of the stackable package structure of the present invention; and

21 to 30 are views showing a manufacturing method of a fifth embodiment of the stackable package structure of the present invention.

3. . . First embodiment of the stackable package structure of the present invention

31. . . Substrate

32. . . First solder ball

33. . . Wire wafer

35. . . Sealant

38. . . Circuit layer

39. . . Insulating material

311. . . Upper surface

312. . . lower surface

313. . . First pad

314. . . Second pad

331. . . wire

332. . . Adhesive layer

333. . . Upper surface

351. . . Upper surface

352. . . First hole

353. . . Second hole

354. . . Trench

355. . . Guide hole

361. . . First conductor layer

362. . . Second conductor layer

363. . . Third conductor layer

382. . . First electrical connection point

383. . . Conductive trace

391. . . Upper surface

Claims (105)

A stackable package structure comprising: a substrate having an upper surface, a lower surface, and at least one first pad, the first pad is located on the upper surface; a wafer on the upper surface of the substrate, and electrically Connecting to the substrate; a gel covering the upper surface of the substrate and the wafer, the encapsulant having an upper surface and at least one via hole, the via hole being located corresponding to the first pad; a circuit layer, The circuit layer includes at least one electrical connection point and at least one conductive trace. The electrical connection point is electrically connected to the first pad through the conductive trace and the via hole. The depth of the electrical connection point is less than the depth of the via hole, and the bottom of the electrical connection point and the bottom of the conductive trace have a spacing from the upper surface of the wafer, and the electrical connection point includes at least one An electrical connection point, the at least one first electrical connection point is directly above the wafer; and an insulating material covering the circuit layer, and exposing the electrical connection point and the via hole, and the insulating material An upper surface is flush with the top of the sealant . The package structure of claim 1, wherein the substrate further comprises a plurality of second pads, the second pads being located on the upper surface. The package structure of claim 2, wherein the wafer comprises a back surface, an active surface and a plurality of bumps, the bumps are located on the active surface, and the wafer is electrically connected to the substrate through the bumps The second pads. The package structure of claim 2, wherein the wafer is electrically connected to the second pads of the substrate through a plurality of wires, and the wafer is attached to the substrate by an adhesive layer. The package structure of claim 1, wherein the sealant comprises at least one first drilled hole and at least one second drilled hole, the circuit layer further comprising a first conductor layer and a second conductor layer, the first conductor layer being located In the first bore, the second conductor layer is located in the second bore, and the first bore and the first conductor layer form the guide hole, and the second bore and the second conductor layer form the Electrically connecting the dots, and a bottom of the second bore has a spacing from an upper surface of the wafer. The package structure of claim 5, wherein the first pad has a thickness greater than or equal to 20 μm, the first hole reveals the first pad, and the first conductor layer directly contacts the first pad. The package structure of claim 5, further comprising at least one first solder ball on the first pad, the first hole revealing the first solder ball, and the first conductor layer is transmitted through the first solder ball Electrically connected to the first pad. The package structure of claim 5, wherein the depth of the second bore is less than the depth of the first bore. The package structure of claim 5, wherein the insulating material fills the first hole and exposes an upper end of the first conductor layer. The package structure of claim 1, wherein the electrical connection point further comprises at least one second electrical connection point, the at least one second electrical connection point being located at a relative position outside the wafer. The package structure of claim 1, wherein the encapsulant further comprises at least one trench, the circuit layer further comprising a third conductor layer, the third conductor layer being located in the trench, and the trench and the third conductor The layer forms the conductive trace and the bottom of the trench has a spacing from the upper surface of one of the wafers. The package structure of claim 11, wherein the insulating material fills the trench. The package structure of claim 1, further comprising a plurality of second solder balls on a lower surface of the substrate. A stackable package structure comprising: a glue body having a bonding surface and at least one via hole, the bonding surface exposing at least one electrical connection point; a circuit layer located on the bonding surface of the encapsulant, including the electrical property a connection point and at least one conductive trace electrically connected to the via hole and the electrical connection point; an insulating material filling the via hole and covering the conductive trace; a wafer located at the sealant In the body, the wafer is located below the circuit layer; and a substrate having a first surface, a second surface, and at least one first pad, the first pad being located on the first surface, the substrate The first surface is used to carry the wafer and the encapsulant. The wafer is electrically connected to the substrate, and the first pad of the substrate is electrically connected to the electrical connection point through the via hole and the conductive trace. . The package structure of claim 14, wherein the substrate further comprises a plurality of second pads, the second pads being located on the first surface. The package structure of claim 15, wherein the wafer comprises a back surface, an active surface, and a plurality of bumps, wherein the bumps are located on the active surface, and the wafer is electrically connected to the substrate through the bumps The second pads. The package structure of claim 15, wherein the wafer is electrically connected to the second pads of the substrate through a plurality of wires, and the wafer is attached to the substrate by an adhesive layer. The package structure of claim 14, wherein the encapsulant further comprises at least one via hole, the circuit layer comprising at least one conductive trace, the via hole is located corresponding to the first pad, and the first pad is through the The via hole and the conductive trace are electrically connected to the electrical connection point. The package structure of claim 18, wherein the encapsulant comprises at least one first hole and at least one second hole, the circuit layer further comprising a first conductor layer and a second conductor layer, the first conductor layer being located In the first bore, the second conductor layer is located in the second bore, and the first bore and the first conductor layer form the guide hole, and the second bore and the second conductor layer form the Electrically connecting the dots, and a bottom of the second bore has a spacing from an upper surface of the wafer. The package structure of claim 19, wherein the first pad has a thickness greater than or equal to 20 μm, the first hole reveals the first pad, and the first conductor layer directly contacts the first pad. The package structure of claim 19, further comprising at least one first solder ball on the first pad, the first hole revealing the first solder ball, and the first conductor layer is transmitted through the first solder ball Electrically connected to the first pad. The package structure of claim 19, wherein the depth of the second bore is less than the depth of the first bore. The package structure of claim 19, wherein the insulating material fills the first bore and exposes an upper end of the first conductor layer. The package structure of claim 18, wherein the conductive traces are on the bonding surface of the encapsulant. The package structure of claim 18, wherein the encapsulant further comprises at least one trench, the circuit layer further comprising a third conductor layer, the third conductor layer being located in the trench, and the trench and the third conductor The layer forms the conductive trace and the bottom of the trench has a spacing from the upper surface of one of the wafers. The package structure of claim 25, wherein the insulating material fills the trench, and a first surface of the insulating material is flush with a top of the encapsulant. The package structure of claim 18, wherein a bottom of the electrical connection point and a bottom of the conductive trace have a spacing from a first surface of the wafer. The package structure of claim 14, wherein the electrical connection point comprises at least one first electrical connection point, the at least one first electrical connection point being directly above the wafer. The package structure of claim 28, wherein the electrical connection point further comprises at least one second electrical connection point, the at least one second electrical connection point being located at a relative position outside the wafer. The package structure of claim 14, further comprising a plurality of second solder balls on the second surface of the substrate. A stackable package structure comprising: a substrate having an upper surface, a lower surface, and at least one first pad, the first pad is located on the upper surface; a wafer on the upper surface of the substrate, and electrically Connecting to the substrate; a gel covering the upper surface of the substrate and the wafer, the encapsulant having an upper surface; a circuit layer on the upper surface of the encapsulant, and a portion of the circuit layer being located on the wafer Upper, the circuit layer includes at least one electrical connection point electrically connected to the first pad; and an insulating material covering the circuit layer and exposing the electrical connection point. The package structure of claim 31, wherein the substrate further comprises a plurality of second pads, the second pads being located on the upper surface. The package structure of claim 32, wherein the wafer comprises a back surface, an active surface and a plurality of bumps, wherein the bumps are located on the active surface, and the wafer is electrically connected to the substrate through the bumps The second pads. The package structure of claim 32, wherein the wafer is electrically connected to the second pads of the substrate through a plurality of wires, and the wafer is attached to the substrate by an adhesive layer. The package structure of claim 31, wherein the circuit layer further comprises at least one conductive trace and a connection circuit layer, the conductive trace is connected to the electrical connection point and the connection circuit layer, and the first pad is transparent The connecting circuit layer and the conductive trace are electrically connected to the electrical connection point. The package structure of claim 35, wherein the conductive trace is parallel to a lower surface of the substrate, the connection layer layer having an angle with the conductive trace. The package structure of claim 35, wherein the conductive trace is on an upper surface of the sealant, and a bottom of the conductive trace has a spacing from an upper surface of the wafer. The package structure of claim 35, wherein the conductive trace is positioned lower than the top of the encapsulant and the bottom of the conductive trace has a spacing from an upper surface of the wafer. The package structure of claim 38, wherein the insulating material covers the conductive trace, and an upper surface of the insulating material is flush with a top of the sealant. The package structure of claim 35, wherein a bottom of the electrical connection point has a spacing from an upper surface of the wafer. The package structure of claim 35, wherein the thickness of the first pad is greater than or equal to 20 μm, and the connection layer directly contacts the first pad. The package structure of claim 41, wherein the connection line layer covers the first pad. The package structure of claim 35, further comprising at least one first solder ball on the first pad, the connection circuit layer directly contacting the first solder ball, and the connection circuit layer is electrically transmitted through the first solder ball Sexually connected to the first pad. The package structure of claim 43, wherein the connection line layer covers the first solder ball. The package structure of claim 35, wherein the bottom of the connection layer is lower than the bottom of the electrical connection point. The package structure of claim 35, wherein the insulating material covers the connecting wiring layer, and an upper surface of the insulating material is flush with a top of the sealing body, and an upper end of the connecting wiring layer is exposed. The package structure of claim 31, wherein the electrical connection point comprises at least one first electrical connection point, the at least one first electrical connection point being directly above the wafer. The package structure of claim 47, wherein the electrical connection point further comprises at least one second electrical connection point, the at least one second electrical connection point being located at a relative position outside the wafer. The package structure of claim 31 further includes a plurality of second solder balls on a lower surface of the substrate. A semiconductor package structure comprising: a stackable package structure comprising: a substrate having an upper surface, a lower surface, and at least one first pad, the first pad being located on the upper surface; and a wafer on the substrate An upper surface electrically connected to the substrate; a gel covering the upper surface of the substrate and the wafer, the encapsulant having an upper surface; a circuit layer on the upper surface of the encapsulant, part of the circuit The layer is located directly above the wafer, the circuit layer includes at least one electrical connection point electrically connected to the first pad; and an insulating material covering the circuit layer and exposing the electrical connection point; At least one upper package structure is disposed on the stackable package structure and electrically connected to the stackable package structure. The package structure of claim 50, wherein the substrate further comprises a plurality of second pads, the second pads being located on the upper surface. The package structure of claim 51, wherein the wafer comprises a back surface, an active surface, and a plurality of bumps, wherein the bumps are located on the active surface, and the wafer is electrically connected to the substrate through the bumps The second pads. The package structure of claim 51, wherein the wafer is electrically connected to the second pads of the substrate through a plurality of wires, and the wafer is attached to the substrate by an adhesive layer. The package structure of claim 50, wherein the encapsulant further comprises at least one via hole, the circuit layer includes at least one conductive trace, the via hole is located corresponding to the first pad, and the first pad is through the The via hole and the conductive trace are electrically connected to the electrical connection point. The package structure of claim 54, wherein the encapsulant comprises at least one first hole and at least one second hole, the circuit layer further comprising a first conductor layer and a second conductor layer, the first conductor layer being located In the first bore, the second conductor layer is located in the second bore, and the first bore and the first conductor layer form the guide hole, and the second bore and the second conductor layer form the Electrically connecting the dots, and a bottom of the second bore has a spacing from an upper surface of the wafer. The package structure of claim 55, wherein the first pad has a thickness greater than or equal to 20 μm, the first hole reveals the first pad, and the first conductor layer directly contacts the first pad. The package structure of claim 55, wherein the stackable package structure further comprises at least one first solder ball on the first pad, the first hole reveals the first solder ball, and the first conductor layer The first solder ball is electrically connected to the first solder pad. The package structure of claim 55, wherein the depth of the second bore is less than the depth of the first bore. The package structure of claim 55, wherein the insulating material fills the first bore and exposes an upper end of the first conductor layer. The package structure of claim 54, wherein the conductive trace is on an upper surface of the encapsulant. The package structure of claim 54, wherein the encapsulant further comprises at least one trench, the circuit layer further comprising a third conductor layer, the third conductor layer being located in the trench, and the trench and the third conductor The layer forms the conductive trace and the bottom of the trench has a spacing from the upper surface of one of the wafers. The package structure of claim 61, wherein the insulating material fills the trench, and an upper surface of the insulating material is flush with a top of the encapsulant. The package structure of claim 54, wherein a bottom of the electrical connection point and a bottom of the conductive trace have a spacing from an upper surface of the wafer. The package structure of claim 50, wherein the electrical connection point comprises at least one first electrical connection point, the at least one first electrical connection point being located directly above the wafer. The package structure of claim 64, wherein the electrical connection point further comprises at least one second electrical connection point, the at least one second electrical connection point being located at a relative position outside the wafer. The package structure of claim 50, wherein the stackable package structure further comprises a plurality of second solder balls on a lower surface of the substrate. The package structure of claim 50 includes at least two upper package structures, which are side by side. The package structure of claim 50, wherein the upper package structure is a Ball Grid Array Package. The package structure of claim 68, wherein the upper package structure comprises a plurality of third solder balls, each of the third solder balls electrically connecting each electrical connection point of the circuit layer. The package structure of claim 69, wherein each of the third solder balls directly contacts each of the electrical connection points of the circuit layer. A method for manufacturing a stackable package structure, comprising: (a) providing a substrate having an upper surface, a lower surface, and at least one first bonding pad, the first bonding pad being located on the upper surface; (b) Forming a wafer on the upper surface of the substrate, the wafer is electrically connected to the substrate; (c) forming a gel to cover the upper surface of the substrate and the wafer, the encapsulant having an upper surface; (d) Forming at least one first hole, at least one second hole and at least one groove by using a laser on an upper surface of the sealant, the position of the first hole corresponding to the first pad, the second hole Is located above the wafer, the trench is located between the first hole and the second hole, and the bottom of the second hole and the groove has a distance from an upper surface of the wafer; (e) forming a conductive metal on the upper surface of the encapsulant; (f) removing conductive metal located outside the first hole, the second hole and the trench to form a first conductor layer, a second conductor layer and a third conductor layer, the first hole and the first conductor layer forming at least one via hole The second hole and the second conductor layer form at least one electrical connection point, the groove and the third conductor layer form at least one conductive trace, and the electrical connection point and the conductive trace form a circuit layer. And the first pad is electrically connected to the electrical connection point through the via hole and the conductive trace; and (g) forms an insulating material to cover the circuit layer and expose the electrical connection point. The method of claim 71, wherein in the step (a), the substrate further comprises a plurality of second pads located on the upper surface. The method of claim 72, wherein in the step (b), the wafer comprises a back surface, an active surface, and a plurality of bumps, wherein the bumps are located on the active surface, and the wafer is electrically transmitted through the bumps The second pads are connected to the substrate. The method of claim 72, wherein in the step (b), the wafer is electrically connected to the second pads of the substrate through a plurality of wires, and the wafer is attached to the substrate by an adhesive layer. The method of claim 71, wherein the thickness of the first pad is greater than or equal to 20 μm in the step (a), in the step (d), the first hole reveals the first pad, the step In (f), the first conductor layer is in direct contact with the first pad. The method of claim 71, wherein after the step (a), further comprising the step of providing at least one first solder ball on the first bonding pad, in the step (d), the first drilling system revealing the first a solder ball, in the step (f), the first conductor layer is electrically connected to the first pad through the first solder ball. The method of claim 71, wherein in the step (d), the depth of the second bore is less than the depth of the first bore. The method of claim 71, wherein in the step (f), a bottom of the electrical connection point and a bottom of the conductive trace have a spacing from an upper surface of the wafer. The method of claim 71, wherein in the step (f), the electrical connection point comprises at least one first electrical connection point, the at least one first electrical connection point being directly above the wafer. The method of claim 79, wherein the electrical connection point further comprises at least one second electrical connection point, the at least one second electrical connection point being located at a relative position outside the wafer. The method of claim 71, wherein in the step (g), the insulating material fills the first hole and the groove to expose an upper end of the first conductor layer, and an upper surface of the insulating material The top of the sealant is flush. The method of claim 71, wherein after the step (g), the step of forming a plurality of second solder balls on the lower surface of the substrate is further included. The method of claim 71, wherein the step (g) further comprises the step of stacking at least one upper package structure. The method of claim 83, wherein at least two upper package structures are stacked, the upper package structures being side by side. The method of claim 83, wherein the upper package structure is a Ball Grid Array Package. The method of claim 85, wherein the upper package structure comprises a plurality of third solder balls, each of the third solder balls electrically connecting each electrical connection point of the circuit layer. The method of claim 86, wherein each of the third solder balls is in direct contact with each of the electrical connection points of the circuit layer. A method for manufacturing a stackable package structure, comprising: (a) providing a substrate having an upper surface, a lower surface, and at least one first bonding pad, the first bonding pad being located on the upper surface; (b) Forming a wafer on the upper surface of the substrate, the wafer is electrically connected to the substrate; (c) forming a gel to cover the upper surface of the substrate and the wafer, the encapsulant having an upper surface; (d) Forming at least a first drilling hole and at least one second drilling hole on the upper surface of the sealing body by using a laser, the first drilling hole is located corresponding to the first bonding pad, and the second drilling hole is located on the chip Above, and a bottom of the second hole has a spacing from an upper surface of the wafer; (e) forming a photoresist on the upper surface of the sealing body, the photoresist having a plurality of openings to expose the first drill a hole, the second hole and a portion of the upper surface of the sealant; (f) forming a conductive metal on the exposed first hole, the second hole and a portion of the upper surface of the sealant to form a surface a first conductor layer, a second conductor layer and at least one conductive trace, the first hole and the Forming at least one via hole, the second hole and the second conductor layer forming at least one electrical connection point, the electrical connection point and the conductive trace forming a circuit layer, and the first pad is Electrically connecting to the electrical connection point through the via hole and the conductive trace; (g) removing the photoresist; and (h) forming an insulating material to cover the circuit layer and revealing the electrical connection point . The method of claim 88, wherein in the step (a), the substrate further comprises a plurality of second pads on the upper surface. The method of claim 89, wherein in the step (b), the wafer comprises a back surface, an active surface and a plurality of bumps, wherein the bumps are located on the active surface, and the wafer is electrically transmitted through the bumps The second pads are connected to the substrate. The method of claim 89, wherein in the step (b), the wafer is electrically connected to the second pads of the substrate through a plurality of wires, and the wafer is attached to the substrate by an adhesive layer. The method of claim 88, wherein the thickness of the first pad is greater than or equal to 20 μm in the step (a), in the step (d), the first hole is exposed to the first pad, the step In (f), the first conductor layer is in direct contact with the first pad. The method of claim 88, wherein after the step (a), further comprising the step of providing at least one first solder ball on the first bonding pad, in the step (d), the first drilling system revealing the first a solder ball, in the step (f), the first conductor layer is electrically connected to the first pad through the first solder ball. The method of claim 88, wherein in the step (d), the depth of the second bore is less than the depth of the first bore. The method of claim 88, wherein in the step (f), the conductive metal is formed by sputtering. The method of claim 88, wherein in the step (f), a bottom of the electrical connection point and a bottom of the conductive trace have a spacing from an upper surface of the wafer. The method of claim 88, wherein in the step (f), the electrical connection point comprises at least one first electrical connection point, the at least one first electrical connection point being directly above the wafer. The method of claim 97, wherein the electrical connection point further comprises at least one second electrical connection point, the at least one second electrical connection point being located at a relative position outside the wafer. The method of claim 88, wherein in the step (h), the insulating material fills the first bore and the upper end of the first conductor layer is exposed. The method of claim 88, wherein after the step (h), the step of forming a plurality of second solder balls on the lower surface of the substrate is further included. The method of claim 88, wherein after the step (h), the step of stacking at least one upper package structure is further included. The method of claim 101, wherein at least two upper package structures are stacked, and the upper package structures are side by side. The method of claim 101, wherein the upper package structure is a Ball Grid Array Package. The method of claim 103, wherein the upper package structure comprises a plurality of third solder balls, each of the third solder balls electrically connecting each electrical connection point of the circuit layer. The method of claim 104, wherein each third solder ball is in direct contact with each electrical connection point of the circuit layer.