TWI576986B - Memory structure - Google Patents

Description

Memory structure

This invention relates to a semiconductor structure, and more particularly to a memory structure.

Semiconductor components are gradually becoming denser and smaller. Along with this trend, various three-dimensional (3D) memory structures have been developed. The three-dimensional memory structure typically includes a three-dimensional array of memory cells located in the array region. However, components and devices in the perimeter area may retain a two-dimensional (2D) structure.

In the present invention, a memory structure is provided in which a three-dimensional design is applied to a peripheral region of a memory structure.

According to some embodiments, such a memory structure includes a first wafer. The first wafer has an array area and a peripheral area. The first wafer includes a first stack and a plurality of through structures. The first stack is disposed in the peripheral zone. The first stack includes a plurality of electrically conductive layers and a plurality of insulating layers that are alternately stacked. The through structure includes an opening, a dielectric layer and a channel material, respectively. The opening passes through the first stack. The dielectric layer is disposed on a sidewall of the opening. The channel material is disposed in the opening and covers the dielectric layer.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

10: First chip
12: word line decoder
20: second chip
22: Bit line decoder
24: page buffer
26: State machine
28: Peripheral circuit
102: substrate
104: First stack
106: conductive layer
108: insulation layer
110: conductive layer
112: insulating layer
114: Through structure
114a: end
114b: end
116: opening
118: dielectric layer
120: channel material
124: transistor
126: global character line
128: second stack
130: conductive layer
132: insulation layer
134: Serial
136: bit line
138: Through structure
140: Connector
142: Connecting line
144: Connector
146: Connector
148: Connector
150: connection layer
152: connection layer
214: Through structure
220: channel layer
222: Insulation material
250: connection layer
314: Through structure
316: opening
318: Dielectric layer
320: channel layer
350: connection layer
450: connection layer
A: Array area
D1: first diameter
D2: second diameter
G1: Group
G2: Group
L: channel length
P: surrounding area
t: thickness
W: channel width

1A-1C are schematic views of a memory structure in accordance with an embodiment.
2 is a circuit diagram of a local word line driver in accordance with an embodiment.
Figure 3 is a schematic illustration of a through structure in accordance with an embodiment.
Figure 4 is a schematic illustration of a through structure in accordance with an embodiment.
Figure 5 is a schematic illustration of a peripheral region of a memory structure in accordance with an embodiment.
Figure 6 is a schematic illustration of a peripheral region of a memory structure in accordance with an embodiment.
Figure 7 is a schematic illustration of a peripheral region of a memory structure in accordance with an embodiment.
Figure 8 is a schematic illustration of a peripheral region of a memory structure in accordance with an embodiment.
Figure 9 is a schematic illustration of a memory structure in accordance with an embodiment.

Various embodiments will be described in more detail below with reference to the drawings. It should be noted that, for the sake of clarity, elements in the drawings may not be shown in their actual relative proportions. In addition, in some of the figures, elements that are not discussed in the detailed description may be omitted, and some parts of the elements discussed may be omitted.

Referring to FIGS. 1A-1C, a memory structure is illustrated in accordance with an embodiment, wherein FIG. 1B is a cross-sectional view of the memory structure along line B-B' in FIG. 1A. The memory structure includes a first wafer 10. The first wafer 10 has an array area A and a peripheral area P. The first wafer 10 includes a first stack 104 and a plurality of through structures 114.

The first stack 104 is disposed in the peripheral area P. More specifically, the first wafer 10 may include a substrate 102, and the first stack 104 is disposed on the substrate 102 in the peripheral region P. In some embodiments, as shown in FIG. 1B, the first stack 104 may not be directly disposed on the substrate 102, and at least one conductive layer 110 and/or at least one insulating layer 112 may be disposed on the first stack 104 and the substrate 102. between. The first stack 104 includes a plurality of electrically conductive layers 106 and a plurality of insulating layers 108 that are alternately stacked. According to some embodiments, the number of conductive layers 106 of the first stack 104 is greater than five, preferably greater than 24. It should be noted that in the example including the conductive layer 110 and the insulating layer 112 in the structure, they may be substantially the same as the conductive layer 106 and the insulating layer 108, respectively. That is, the conductive layers 110 and 106 are formed by a similar process and exhibit similar properties, and the insulating layers 112 and 108 are formed by a similar process and exhibit similar properties.

The through structure 114 includes an opening 116, a dielectric layer 118, and a channel material 120, respectively. The opening 116 passes through the first stack 104. In the present embodiment, the opening 116 is a hole. A dielectric layer 118 is disposed on a sidewall of the opening 116. Channel material 120 is disposed in opening 116 and overlies dielectric layer 118. In the present embodiment, the channel material 120 fills the opening 116. FIG. 1C shows an enlarged view of the through structure 114. As shown in FIG. 1C, the dielectric layer 118 has a thickness t. The thickness t is preferably greater than 250 Å. Channel material 120 has a channel length L. The channel length L is preferably greater than 1 micron.

1A to 1B illustrate an exemplary structure that can be disposed in the array area A. However, other memory array structures, particularly other three-dimensional memory array structures, can also be applied. As shown in FIGS. 1A-1B, the first wafer 10 may further include a second stack 128 and a plurality of strings 134.

The second stack 128 is disposed in the array area A. More specifically, the second stack 128 is disposed on the substrate 102 in the array area A. The second stack 128 includes a plurality of electrically conductive layers 130 and a plurality of insulating layers 132 that are alternately stacked. The string 134 passes through the second stack 128. A three dimensional array of memory cells is defined by the intersection of the series 134 and the conductive layer 130 of the second stack 128. According to some embodiments, the conductive layer 130 of the second stack 128 may be configured as a string select line, a local word line, and/or a ground select line. For example, the uppermost conductive layer 130 can be configured as a tandem select line, the lowermost conductive layer 130 can be configured as a ground select line, and the other conductive layers 130 can be configured as local word lines. At the same time, bit line 136 can be provided on serial 134, and a global word line 126 can be provided across structure 114.

The first stack 104 and the second stack 128 are preferably formed by the same process. In the structure thus constructed, the conductive layer 106 of the first stack 104 and the conductive layer 130 of the second stack 128 are formed of the same material and disposed at the same level, the insulating layer 108 of the first stack 104 and the second stack The insulating layer 132 of 128 is formed of the same material and disposed at the same level. Moreover, the process of forming the through structure 114 and the process of forming the series 134 can be compatible with each other. Moreover, in some embodiments, bit line 136 and global word line 126 are formed from the same metal layer. This saves process time and costs. It should be noted that the through structure 114 may have a first diameter d1 (shown in FIG. 1C), and the series 134 may have a second diameter d2 (shown in FIG. 1B), and the first diameter d1 may be greater than the second diameter. D2 to provide a larger channel width W.

According to some embodiments, the through structure 114 provides a multilayer gate structure, respectively. In some examples, the upper side can be the drain side and the lower side can be the source side. In some embodiments, the through structure 114 can be provided to a local word line driver. More specifically, the memory structure can include at least one local word line driver. A local word line driver can include a through structure 114. Alternatively, a local word line driver can include two or more through structures 114 connected in parallel. According to some embodiments, the memory structure may include a word line decoder 12 disposed in the peripheral region P, wherein the word line decoder 12 includes a first stack 104 and a through structure 114. That is, word line decoder 12 includes the at least one local word line driver.

Please refer to FIG. 2, which illustrates a circuit of a local word line driver in accordance with an embodiment. A plurality of transistors 124 are formed at the intersection of the channel material 120 and the conductive layer 106 of the first stack 104. In addition, each local word line driver can be coupled to a global word line 126 and a local word line disposed in array area A. For example, the local word line driver can be coupled to a global word line 126 at one end 114a, such as by connector 146, as shown in FIG. 1B. The local word line driver can be coupled to a local word line at the other end 114b, such as by a U-shaped connection path (as indicated by the dashed line in FIG. 1B), the connector 140, the connection line 142, and the connection. Piece 144, as shown in Figure 1B. The U-shaped connection path shown in FIG. 1B includes a through structure 114, a conductive layer 110, and another through structure 138 similar to the through structure 114. Local word line drivers can be provided in different groups G1 and G2 to select different blocks in array area A. Referring back to FIG. 1B, in some embodiments, the conductive layer 106 corresponding to the through structure 114 can be coupled to a block selector by the connector 148 and the connection layer 150.

Referring now to Figures 3 and 4, other types of through structures 214 and 314 are provided. In the embodiment illustrated in FIG. 3, the channel material penetrating the structure 214 forms a thin channel layer 220 on the dielectric layer 118. The through structure 214 also includes an insulating material 222. Insulating material 222 fills opening 116 and covers channel layer 220 formed of channel material. In the embodiment illustrated in FIG. 4, the opening 316 of the through structure 314 is a groove. Two dielectric layers 318 may be formed on opposite sidewalls of the trench, respectively. The channel material can be disposed along the two dielectric layers 318 and form two channel layers 320 thereon. At this time, the channel width W depends on how long the groove extends.

Figures 5-8 illustrate various different configurations that may be applied for the first stack 104 and the through structure 114. In the embodiment illustrated in FIG. 5, the conductive layers 106 corresponding to one of the through structures 114 are fully coupled together, such as by the tie layer 250. As such, the multilayer gate structure can have a common gate. In the embodiment illustrated in FIG. 6, the conductive layers 106 corresponding to one of the through structures 114 are partially coupled together, such as by the tie layer 350. As such, the multilayer gate structure can have a partial common gate. In the embodiment shown in FIG. 7, the conductive layers 106 corresponding to one through structure 114 are not coupled to each other. That is, the connection layer 450 is divided into a plurality of portions that are independently connected to the conductive layer 106, respectively. As such, the multilayer gate structure can have independently controlled gates. In the embodiment shown in Fig. 8, similar to the embodiment shown in Fig. 5, the conductive layers 106 corresponding to one through structure 114 are completely coupled together. However, two or more through structures 114 are joined together, such as by connecting layer 152. The through structures 114 are particularly connectable in parallel to obtain a longer total channel width, resulting in a higher current. For example, as shown in FIG. 8, the three through structures 114 are connected in parallel, and the total channel width is three times the circumference of the channel material 120, so that a higher current can be obtained.

According to the embodiments described above, a local word line driver formed in a three-dimensional structure can be provided. In order to pass a high voltage typically used as an operating voltage from the global word line to the local word line, the local word line driver is preferably a high voltage MOS device. The local word line driver acts as the "last" transistor for the word line decoder, and its operating environment is typically above 20V. Therefore, the local word line driver preferably has a long channel and a thick gate. In a two-dimensional structure, a large area may be required. According to the invention, however, the local word line driver is formed in a three-dimensional structure. According to the embodiments described herein, the long channel system extends in the vertical direction, reducing the required area.

Due to the setting of the local word line driver, the number of lines leaving the word line decoder can be greatly reduced. Thus, the embodiments described herein are also applicable to "off-chip" memory designs. As shown in FIG. 9, the memory structure may further include a second wafer 20. The second wafer 20 is coupled to the first wafer 10. The second wafer 20 can include a bit line decoder 22, a page buffer 24, a state machine 26, peripheral circuitry 28, and/or other components typically disposed in the peripheral region of the memory and Device. These components and devices are typically formed by processes other than the three-dimensional memory array used in fabricating the array regions. Therefore, the process can be simplified by forming them on different wafers. Furthermore, since the components and devices that need to be formed in the substrate are now formed on another wafer, the substrate 102 of the first wafer 10 may not be formed of a germanium wafer. For example, the substrate 102 of the first wafer 10 may be formed of hafnium oxide. Therefore, the cost can be reduced.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

102: substrate

104: First stack

106: conductive layer

108: insulation layer

114: Through structure

116: opening

118: dielectric layer

120: channel material

126: global character line

148: Connector

250: connection layer

Claims (10)

A memory structure that includes:
a first wafer having an array region and a peripheral region, the first wafer comprising:
a first stack is disposed in the peripheral region, the first stack includes a plurality of alternating conductive layers and a plurality of insulating layers; and a plurality of through structures, respectively:
An opening through the first stack;
a dielectric layer disposed on a sidewall of the opening; and a channel material disposed in the opening and covering the dielectric layer. The memory structure of claim 1, wherein the channel material has a channel length greater than 1 micron. The memory structure of claim 1, wherein the conductive layers corresponding to one of the through structures are coupled together completely or partially. The memory structure of claim 1, wherein the conductive layers corresponding to one of the through structures are not coupled to each other. The memory structure of claim 1 further includes:
At least one local word line driver, respectively comprising:
One of the through structures; or two or more through structures connected in parallel in the through structure. The memory structure of claim 5, wherein each of the at least one local word line driver is coupled to a global word line and a local word line. The memory structure of claim 1 further includes:
A word line decoder is disposed in the peripheral area, the word line decoder including the first stack and the through structures. The memory structure of claim 1, wherein the first chip further comprises:
a second stack disposed in the array region, the second stack including a plurality of alternating conductive layers and a plurality of insulating layers; and a plurality of strings passing through the second stack;
A three-dimensional array of memory cells is defined by intersections of the series and the conductive layers of the second stack. The memory structure of claim 8, wherein the through structures have a first diameter, the series having a second diameter, the first diameter being greater than the second diameter. The memory structure of claim 1 further includes:
A second chip is coupled to the first chip, and the second chip includes at least one of a bit line decoder, a page buffer, a state machine, and a peripheral circuit.