TWI576986B - Memory structure - Google Patents
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Description
本發明是關於一種半導體結構,特別是關於一種記憶體結構。This invention relates to a semiconductor structure, and more particularly to a memory structure.
半導體元件正逐漸地變得更密集且更小。隨著這股潮流,各種三維(3D)記憶體結構被發展出來。三維記憶體結構典型地包括位在陣列區中的記憶胞的一三維陣列。然而,周邊區中的元件及裝置可能保有二維(2D)結構。Semiconductor components are gradually becoming denser and smaller. Along with this trend, various three-dimensional (3D) memory structures have been developed. The three-dimensional memory structure typically includes a three-dimensional array of memory cells located in the array region. However, components and devices in the perimeter area may retain a two-dimensional (2D) structure.
在本發明中,提供一種記憶體結構,其中三維設計係應用至記憶體結構的周邊區。In the present invention, a memory structure is provided in which a three-dimensional design is applied to a peripheral region of a memory structure.
根據一些實施例,此種記憶體結構包括一第一晶片。第一晶片具有一陣列區及一周邊區。第一晶片包括一第一堆疊及複數貫穿結構。第一堆疊設置在周邊區中。第一堆疊包括交替堆疊的複數導電層及複數絕緣層。貫穿結構分別包括一開口、一介電層及一通道材料。開口穿過第一堆疊。介電層設置在開口的一側壁上。通道材料設置在開口中,並覆蓋介電層。According to some embodiments, such a memory structure includes a first wafer. The first wafer has an array area and a peripheral area. The first wafer includes a first stack and a plurality of through structures. The first stack is disposed in the peripheral zone. The first stack includes a plurality of electrically conductive layers and a plurality of insulating layers that are alternately stacked. The through structure includes an opening, a dielectric layer and a channel material, respectively. The opening passes through the first stack. The dielectric layer is disposed on a sidewall of the opening. The channel material is disposed in the opening and covers the dielectric layer.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下:In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:
10:第一晶片
12:字元線解碼器
20:第二晶片
22:位元線解碼器
24:頁緩衝區
26:狀態機
28:周邊電路
102:基板
104:第一堆疊
106:導電層
108:絕緣層
110:導電層
112:絕緣層
114:貫穿結構
114a:端
114b:端
116:開口
118:介電層
120:通道材料
124:電晶體
126:全域字元線
128:第二堆疊
130:導電層
132:絕緣層
134:串列
136:位元線
138:貫穿結構
140:連接件
142:連接線
144:連接件
146:連接件
148:連接件
150:連接層
152:連接層
214:貫穿結構
220:通道層
222:絕緣材料
250:連接層
314:貫穿結構
316:開口
318:介電層
320:通道層
350:連接層
450:連接層
A:陣列區
d1:第一直徑
d2:第二直徑
G1:群組
G2:群組
L:通道長度
P:周邊區
t:厚度
W:通道寬度
10: First chip
12: word line decoder
20: second chip
22: Bit line decoder
24: page buffer
26: State machine
28: Peripheral circuit
102: substrate
104: First stack
106: conductive layer
108: insulation layer
110: conductive layer
112: insulating layer
114: Through structure
114a: end
114b: end
116: opening
118: dielectric layer
120: channel material
124: transistor
126: global character line
128: second stack
130: conductive layer
132: insulation layer
134: Serial
136: bit line
138: Through structure
140: Connector
142: Connecting line
144: Connector
146: Connector
148: Connector
150: connection layer
152: connection layer
214: Through structure
220: channel layer
222: Insulation material
250: connection layer
314: Through structure
316: opening
318: Dielectric layer
320: channel layer
350: connection layer
450: connection layer
A: Array area
D1: first diameter
D2: second diameter
G1: Group
G2: Group
L: channel length
P: surrounding area
t: thickness
W: channel width
第1A~1C圖為根據一實施例的記憶體結構的示意圖。
第2圖為根據一實施例的局部字元線驅動器(local word line driver)的電路圖。
第3圖為根據一實施例的貫穿結構的示意圖。
第4圖為根據一實施例的貫穿結構的示意圖。
第5圖為根據一實施例的記憶體結構的周邊區的示意圖。
第6圖為根據一實施例的記憶體結構的周邊區的示意圖。
第7圖為根據一實施例的記憶體結構的周邊區的示意圖。
第8圖為根據一實施例的記憶體結構的周邊區的示意圖。
第9圖為根據一實施例的記憶體結構的示意圖。
1A-1C are schematic views of a memory structure in accordance with an embodiment.
2 is a circuit diagram of a local word line driver in accordance with an embodiment.
Figure 3 is a schematic illustration of a through structure in accordance with an embodiment.
Figure 4 is a schematic illustration of a through structure in accordance with an embodiment.
Figure 5 is a schematic illustration of a peripheral region of a memory structure in accordance with an embodiment.
Figure 6 is a schematic illustration of a peripheral region of a memory structure in accordance with an embodiment.
Figure 7 is a schematic illustration of a peripheral region of a memory structure in accordance with an embodiment.
Figure 8 is a schematic illustration of a peripheral region of a memory structure in accordance with an embodiment.
Figure 9 is a schematic illustration of a memory structure in accordance with an embodiment.
以下將參照所附圖式,對於各種不同的實施例進行更詳細的說明。須注意的是,為了清楚起見,圖式中的元件可能未依照其實際上的相對比例繪示。此外,在部分圖式中,可能省略未在細節敘述中討論的元件,亦可能省略所討論之元件的一些部分。Various embodiments will be described in more detail below with reference to the drawings. It should be noted that, for the sake of clarity, elements in the drawings may not be shown in their actual relative proportions. In addition, in some of the figures, elements that are not discussed in the detailed description may be omitted, and some parts of the elements discussed may be omitted.
請參照第1A~1C圖,其繪示根據一實施例的記憶體結構,其中第1B圖為記憶體結構沿著第1A圖中B-B’線的剖面圖。記憶體結構包括一第一晶片10。第一晶片10具有一陣列區A及一周邊區P。第一晶片10包括一第一堆疊104及複數貫穿結構114。Referring to FIGS. 1A-1C, a memory structure is illustrated in accordance with an embodiment, wherein FIG. 1B is a cross-sectional view of the memory structure along line B-B' in FIG. 1A. The memory structure includes a first wafer 10. The first wafer 10 has an array area A and a peripheral area P. The first wafer 10 includes a first stack 104 and a plurality of through structures 114.
第一堆疊104設置在周邊區P中。更具體地說,第一晶片10可包括一基板102,而第一堆疊104在周邊區P中設置在基板102上。在一些實施例中,如第1B圖所示,第一堆疊104可以不直接設置在基板102上,至少一導電層110及/或至少一絕緣層112可設置在第一堆疊104及基板102之間。第一堆疊104包括交替堆疊的複數導電層106及複數絕緣層108。根據一些實施例,第一堆疊104的導電層106的數目大於5,較佳地大於24。須注意的是,在結構中包括導電層110及絕緣層112的例子中,它們可實質上分別相同於導電層106及絕緣層108。亦即,導電層110及106係由類似的製程形成並展現出類似的性質,絕緣層112及108係由類似的製程形成並展現出類似的性質。The first stack 104 is disposed in the peripheral area P. More specifically, the first wafer 10 may include a substrate 102, and the first stack 104 is disposed on the substrate 102 in the peripheral region P. In some embodiments, as shown in FIG. 1B, the first stack 104 may not be directly disposed on the substrate 102, and at least one conductive layer 110 and/or at least one insulating layer 112 may be disposed on the first stack 104 and the substrate 102. between. The first stack 104 includes a plurality of electrically conductive layers 106 and a plurality of insulating layers 108 that are alternately stacked. According to some embodiments, the number of conductive layers 106 of the first stack 104 is greater than five, preferably greater than 24. It should be noted that in the example including the conductive layer 110 and the insulating layer 112 in the structure, they may be substantially the same as the conductive layer 106 and the insulating layer 108, respectively. That is, the conductive layers 110 and 106 are formed by a similar process and exhibit similar properties, and the insulating layers 112 and 108 are formed by a similar process and exhibit similar properties.
貫穿結構114分別包括一開口116、一介電層118及一通道材料120。開口116穿過第一堆疊104。在本實施例中,開口116為孔洞。介電層118設置在開口116的一側壁上。通道材料120設置在開口116中,並覆蓋介電層118。在本實施例中,通道材料120填充開口116。第1C圖示出貫穿結構114的放大圖。如第1C圖所示,介電層118具有一厚度t。厚度t較佳地大於250 Å。通道材料120具有一通道長度L。通道長度L較佳地大於1微米。The through structure 114 includes an opening 116, a dielectric layer 118, and a channel material 120, respectively. The opening 116 passes through the first stack 104. In the present embodiment, the opening 116 is a hole. A dielectric layer 118 is disposed on a sidewall of the opening 116. Channel material 120 is disposed in opening 116 and overlies dielectric layer 118. In the present embodiment, the channel material 120 fills the opening 116. FIG. 1C shows an enlarged view of the through structure 114. As shown in FIG. 1C, the dielectric layer 118 has a thickness t. The thickness t is preferably greater than 250 Å. Channel material 120 has a channel length L. The channel length L is preferably greater than 1 micron.
第1A~1B圖示出可設置在陣列區A中的一示例性結構。然而,也可以應用其他記憶體陣列結構,特別是其他三維的記憶體陣列結構。如第1A~1B圖所示,第一晶片10還可包括一第二堆疊128及複數串列134。1A to 1B illustrate an exemplary structure that can be disposed in the array area A. However, other memory array structures, particularly other three-dimensional memory array structures, can also be applied. As shown in FIGS. 1A-1B, the first wafer 10 may further include a second stack 128 and a plurality of strings 134.
第二堆疊128設置在陣列區A中。更具體地說,第二堆疊128在陣列區A中設置在基板102上。第二堆疊128包括交替堆疊的複數導電層130及複數絕緣層132。串列134穿過第二堆疊128。記憶胞的一三維陣列係由串列134及第二堆疊128的導電層130的交點所定義。根據一些實施例,第二堆疊128的導電層130可配置為串列選擇線(string select line)、局部字元線(local word line)、及/或接地選擇線(ground select line)。舉例而言,最上方的導電層130可配置為串列選擇線,最下方的導電層130可配置為接地選擇線,而其他的導電層130可配置為局部字元線。同時,位元線136可提供在串列134上,全域字元線(global word line)126可提供在貫穿結構114上。The second stack 128 is disposed in the array area A. More specifically, the second stack 128 is disposed on the substrate 102 in the array area A. The second stack 128 includes a plurality of electrically conductive layers 130 and a plurality of insulating layers 132 that are alternately stacked. The string 134 passes through the second stack 128. A three dimensional array of memory cells is defined by the intersection of the series 134 and the conductive layer 130 of the second stack 128. According to some embodiments, the conductive layer 130 of the second stack 128 may be configured as a string select line, a local word line, and/or a ground select line. For example, the uppermost conductive layer 130 can be configured as a tandem select line, the lowermost conductive layer 130 can be configured as a ground select line, and the other conductive layers 130 can be configured as local word lines. At the same time, bit line 136 can be provided on serial 134, and a global word line 126 can be provided across structure 114.
第一堆疊104及第二堆疊128較佳地是由相同的製程形成。在這麼做的結構中,第一堆疊104的導電層106及第二堆疊128的導電層130係由相同的材料形成並設置在相同的水平高度,第一堆疊104的絕緣層108及第二堆疊128的絕緣層132係由相同的材料形成並設置在相同的水平高度。此外,形成貫穿結構114的製程及形成串列134的製程可彼此相容。再者,在一些實施例中,位元線136及全域字元線126係由相同的金屬層形成。如此一來,便可節省製程時間及成本。須注意的是,貫穿結構114可具有一第一直徑d1(示於第1C圖),串列134可具有一第二直徑d2(示於第1B圖),第一直徑d1可大於第二直徑d2,以提供較大的通道寬度W。The first stack 104 and the second stack 128 are preferably formed by the same process. In the structure thus constructed, the conductive layer 106 of the first stack 104 and the conductive layer 130 of the second stack 128 are formed of the same material and disposed at the same level, the insulating layer 108 of the first stack 104 and the second stack The insulating layer 132 of 128 is formed of the same material and disposed at the same level. Moreover, the process of forming the through structure 114 and the process of forming the series 134 can be compatible with each other. Moreover, in some embodiments, bit line 136 and global word line 126 are formed from the same metal layer. This saves process time and costs. It should be noted that the through structure 114 may have a first diameter d1 (shown in FIG. 1C), and the series 134 may have a second diameter d2 (shown in FIG. 1B), and the first diameter d1 may be greater than the second diameter. D2 to provide a larger channel width W.
根據一些實施例,貫穿結構114分別提供多層閘極結構。在一些例子中,上側可為汲極側,而下側可為源極側。在一些實施例中,貫穿結構114可提供予局部字元線驅動器。更具體地說,記憶體結構可包括至少一局部字元線驅動器。一個局部字元線驅動器可包括一個貫穿結構114。或者,一個局部字元線驅動器可包括並聯連接的二或多個貫穿結構114。根據一些實施例,記憶體結構可包括設置在周邊區P中的一字元線解碼器12,其中該字元線解碼器12包括第一堆疊104及貫穿結構114。亦即,字元線解碼器12包括該至少一局部字元線驅動器。According to some embodiments, the through structure 114 provides a multilayer gate structure, respectively. In some examples, the upper side can be the drain side and the lower side can be the source side. In some embodiments, the through structure 114 can be provided to a local word line driver. More specifically, the memory structure can include at least one local word line driver. A local word line driver can include a through structure 114. Alternatively, a local word line driver can include two or more through structures 114 connected in parallel. According to some embodiments, the memory structure may include a word line decoder 12 disposed in the peripheral region P, wherein the word line decoder 12 includes a first stack 104 and a through structure 114. That is, word line decoder 12 includes the at least one local word line driver.
請參照第2圖,其繪示根據一實施例的局部字元線驅動器的電路。複數電晶體124係形成在通道材料120及第一堆疊104的導電層106的交點。此外,各個局部字元線驅動器可耦接至一全域字元線126及設置在陣列區A中的一局部字元線。舉例而言,局部字元線驅動器可在一端114a耦接至一全域字元線126,這例如是藉由連接件146,如第1B圖所示。局部字元線驅動器可在另一端114b耦接至一局部字元線,這例如是藉由U形連接路徑(如第1B圖中的虛線所指示者)、連接件140、連接線142及連接件144,如第1B圖所示。第1B圖所示的U形連接路徑包括貫穿結構114、導電層110及類似於貫穿結構114的另一貫穿結構138。局部字元線驅動器可提供在不同的群組G1及G2,以選擇陣列區A中不同的區塊。請再回頭參照第1B圖,在一些實施例中,對應至貫穿結構114的導電層106可藉由連接件148及連接層150耦接至一區塊選擇器(block selector)。Please refer to FIG. 2, which illustrates a circuit of a local word line driver in accordance with an embodiment. A plurality of transistors 124 are formed at the intersection of the channel material 120 and the conductive layer 106 of the first stack 104. In addition, each local word line driver can be coupled to a global word line 126 and a local word line disposed in array area A. For example, the local word line driver can be coupled to a global word line 126 at one end 114a, such as by connector 146, as shown in FIG. 1B. The local word line driver can be coupled to a local word line at the other end 114b, such as by a U-shaped connection path (as indicated by the dashed line in FIG. 1B), the connector 140, the connection line 142, and the connection. Piece 144, as shown in Figure 1B. The U-shaped connection path shown in FIG. 1B includes a through structure 114, a conductive layer 110, and another through structure 138 similar to the through structure 114. Local word line drivers can be provided in different groups G1 and G2 to select different blocks in array area A. Referring back to FIG. 1B, in some embodiments, the conductive layer 106 corresponding to the through structure 114 can be coupled to a block selector by the connector 148 and the connection layer 150.
現在請參照第3圖及第4圖,其提供其他類型的貫穿結構214及314。在第3圖所示的實施例中,貫穿結構214的通道材料形成位在介電層118上的一個薄的通道層220。貫穿結構214還包括一絕緣材料222。絕緣材料222填充開口116,並覆蓋由通道材料形成的通道層220。在第4圖所示的實施例中,貫穿結構314的開口316為溝槽。二個介電層318可分別形成在溝槽相對的側壁上。通道材料可沿著二個介電層318設置,並於其上形成二個通道層320。此時,通道寬度W取決於溝槽延伸多長。Referring now to Figures 3 and 4, other types of through structures 214 and 314 are provided. In the embodiment illustrated in FIG. 3, the channel material penetrating the structure 214 forms a thin channel layer 220 on the dielectric layer 118. The through structure 214 also includes an insulating material 222. Insulating material 222 fills opening 116 and covers channel layer 220 formed of channel material. In the embodiment illustrated in FIG. 4, the opening 316 of the through structure 314 is a groove. Two dielectric layers 318 may be formed on opposite sidewalls of the trench, respectively. The channel material can be disposed along the two dielectric layers 318 and form two channel layers 320 thereon. At this time, the channel width W depends on how long the groove extends.
第5~8圖示出可應用之用於第一堆疊104及貫穿結構114的各種不同配置。在第5圖所示的實施例中,對應至一個貫穿結構114的導電層106係完全地耦接在一起,這例如是藉由連接層250。如此一來,多層閘極結構可具有一共同閘極。在第6圖所示的實施例中,對應至一個貫穿結構114的導電層106係部分地耦接在一起,這例如是藉由連接層350。如此一來,多層閘極結構可具有局部共同閘極(partial common gate)。在第7圖所示的實施例中,對應至一個貫穿結構114的導電層106係未彼此耦接。亦即,連接層450分成分別獨立連接至導電層106的數個部分。如此一來,多層閘極結構可具有獨立控制的閘極。在第8圖所示的實施例中,類似於第5圖所示的實施例,對應至一個貫穿結構114的導電層106係完全地耦接在一起。然而,二或多個貫穿結構114係連接在一起,這例如是藉由連接層152。貫穿結構114特別是可並聯連接,以得到較長的總通道寬度,從而得到較高的電流。舉例而言,如第8圖所示,三個貫穿結構114係並聯連接,總通道寬度為通道材料120周長的三倍,從而可得到較高的電流。Figures 5-8 illustrate various different configurations that may be applied for the first stack 104 and the through structure 114. In the embodiment illustrated in FIG. 5, the conductive layers 106 corresponding to one of the through structures 114 are fully coupled together, such as by the tie layer 250. As such, the multilayer gate structure can have a common gate. In the embodiment illustrated in FIG. 6, the conductive layers 106 corresponding to one of the through structures 114 are partially coupled together, such as by the tie layer 350. As such, the multilayer gate structure can have a partial common gate. In the embodiment shown in FIG. 7, the conductive layers 106 corresponding to one through structure 114 are not coupled to each other. That is, the connection layer 450 is divided into a plurality of portions that are independently connected to the conductive layer 106, respectively. As such, the multilayer gate structure can have independently controlled gates. In the embodiment shown in Fig. 8, similar to the embodiment shown in Fig. 5, the conductive layers 106 corresponding to one through structure 114 are completely coupled together. However, two or more through structures 114 are joined together, such as by connecting layer 152. The through structures 114 are particularly connectable in parallel to obtain a longer total channel width, resulting in a higher current. For example, as shown in FIG. 8, the three through structures 114 are connected in parallel, and the total channel width is three times the circumference of the channel material 120, so that a higher current can be obtained.
根據上述的實施例,可提供形成在三維結構中的局部字元線驅動器。為了從全域字元線往局部字元線傳遞典型地用作操作電壓的高電壓,局部字元線驅動器較佳地為高壓MOS裝置。局部字元線驅動器作為字元線解碼器「最後」的電晶體,其操作環境典型地高於20 V。因此,局部字元線驅動器較佳地具有長的通道及厚的閘極。在二維結構中,可能需要一個大面積。而根據本發明,局部字元線驅動器係形成在三維結構中。根據此處所述的實施例,長的通道係延伸在垂直方向,能減少所需面積。According to the embodiments described above, a local word line driver formed in a three-dimensional structure can be provided. In order to pass a high voltage typically used as an operating voltage from the global word line to the local word line, the local word line driver is preferably a high voltage MOS device. The local word line driver acts as the "last" transistor for the word line decoder, and its operating environment is typically above 20V. Therefore, the local word line driver preferably has a long channel and a thick gate. In a two-dimensional structure, a large area may be required. According to the invention, however, the local word line driver is formed in a three-dimensional structure. According to the embodiments described herein, the long channel system extends in the vertical direction, reducing the required area.
由於局部字元線驅動器的設置,離開字元線解碼器的連接線數目可大幅地減少。因此,此處所述的實施例也可應用於「晶片外」(off-chip)的記憶體設計。如第9圖所示,記憶體結構還可包括一第二晶片20。第二晶片20耦接至第一晶片10。第二晶片20可包括位元線解碼器22、頁緩衝區(page buffer)24、狀態機(state machine)26、周邊電路28、及/或其他典型地設置在記憶體周邊區中的元件及裝置。這些元件及裝置典型地是由不同於用在製造陣列區中的三維記憶體陣列的製程所形成。因此,藉由將它們成在不同的晶片上,可簡化製程。此外,由於需要形成在基板中的元件及裝置現在是形成在另一晶片上,第一晶片10的基板102可以不是由矽晶圓形成。舉例而言,第一晶片10的基板102可由二氧化矽形成。因此,可降低成本。Due to the setting of the local word line driver, the number of lines leaving the word line decoder can be greatly reduced. Thus, the embodiments described herein are also applicable to "off-chip" memory designs. As shown in FIG. 9, the memory structure may further include a second wafer 20. The second wafer 20 is coupled to the first wafer 10. The second wafer 20 can include a bit line decoder 22, a page buffer 24, a state machine 26, peripheral circuitry 28, and/or other components typically disposed in the peripheral region of the memory and Device. These components and devices are typically formed by processes other than the three-dimensional memory array used in fabricating the array regions. Therefore, the process can be simplified by forming them on different wafers. Furthermore, since the components and devices that need to be formed in the substrate are now formed on another wafer, the substrate 102 of the first wafer 10 may not be formed of a germanium wafer. For example, the substrate 102 of the first wafer 10 may be formed of hafnium oxide. Therefore, the cost can be reduced.
綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
102:基板102: substrate
104:第一堆疊104: First stack
106:導電層106: conductive layer
108:絕緣層108: insulation layer
114:貫穿結構114: Through structure
116:開口116: opening
118:介電層118: dielectric layer
120:通道材料120: channel material
126:全域字元線126: global character line
148:連接件148: Connector
250:連接層250: connection layer
Claims (10)
一第一晶片,具有一陣列區及一周邊區,該第一晶片包括:
一第一堆疊,設置在該周邊區中,該第一堆疊包括交替堆疊的複數導電層及複數絕緣層;以及
複數貫穿結構,分別包括:
一開口,穿過該第一堆疊;
一介電層,設置在該開口的一側壁上;及
一通道材料,設置在該開口中,並覆蓋該介電層。 A memory structure that includes:
a first wafer having an array region and a peripheral region, the first wafer comprising:
a first stack is disposed in the peripheral region, the first stack includes a plurality of alternating conductive layers and a plurality of insulating layers; and a plurality of through structures, respectively:
An opening through the first stack;
a dielectric layer disposed on a sidewall of the opening; and a channel material disposed in the opening and covering the dielectric layer.
至少一局部字元線驅動器,分別包括:
該些貫穿結構中的一個貫穿結構;或
該些貫穿結構中並聯連接的二或多個貫穿結構。 The memory structure of claim 1 further includes:
At least one local word line driver, respectively comprising:
One of the through structures; or two or more through structures connected in parallel in the through structure.
一字元線解碼器,設置在該周邊區中,該字元線解碼器包括該第一堆疊及該些貫穿結構。 The memory structure of claim 1 further includes:
A word line decoder is disposed in the peripheral area, the word line decoder including the first stack and the through structures.
一第二堆疊,設置在該陣列區中,該第二堆疊包括交替堆疊的複數導電層及複數絕緣層;以及
複數串列,穿過該第二堆疊;
其中記憶胞的一三維陣列係由該些串列及該第二堆疊的該些導電層的交點所定義。 The memory structure of claim 1, wherein the first chip further comprises:
a second stack disposed in the array region, the second stack including a plurality of alternating conductive layers and a plurality of insulating layers; and a plurality of strings passing through the second stack;
A three-dimensional array of memory cells is defined by intersections of the series and the conductive layers of the second stack.
一第二晶片,耦接至該第一晶片,該第二晶片包括位元線解碼器、頁緩衝區、狀態機及周邊電路中的至少一者。
The memory structure of claim 1 further includes:
A second chip is coupled to the first chip, and the second chip includes at least one of a bit line decoder, a page buffer, a state machine, and a peripheral circuit.
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US20130341701A1 (en) * | 2010-10-18 | 2013-12-26 | Imec | Vertical Semiconductor Memory Device and Manufacturing Method Thereof |
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US20130341701A1 (en) * | 2010-10-18 | 2013-12-26 | Imec | Vertical Semiconductor Memory Device and Manufacturing Method Thereof |
TW201232701A (en) * | 2011-01-19 | 2012-08-01 | Macronix Int Co Ltd | Multilayer connection structure and making method |
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