CN103901675B - Thin-film transistor array base-plate and liquid crystal display device - Google Patents
Thin-film transistor array base-plate and liquid crystal display device Download PDFInfo
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Abstract
The invention discloses a kind of thin-film transistor array base-plate and the liquid crystal display device including the array base palte, the array base palte includes：First transparency conducting layer and the second transparency conducting layer, first transparency conducting layer and second transparency conducting layer are insulated from each other；Multiple sub-pixels；First transparency conducting layer includes the pixel electrode of first kind sub-pixel group and the public electrode of Equations of The Second Kind sub-pixel group；Second transparency conducting layer includes the pixel electrode of Equations of The Second Kind sub-pixel group and the public electrode of first kind sub-pixel group；The first kind sub-pixel group is disposed adjacent with Equations of The Second Kind sub-pixel group on the array base palte, and first kind sub-pixel group is non-conterminous each other, and Equations of The Second Kind sub-pixel group is non-conterminous each other.The present invention is by way of changing the set-up mode of array base palte pixel electrode and public electrode and eliminating or reduce ghost phenomena generation and simplify polarity inversion.
Description
Technical field
The present invention relates to technical field of liquid crystal display, more particularly to a kind of thin-film transistor array base-plate and liquid crystal display dress
Put.
Background technology
IPS mode LCDs by injecting liquid crystal in two-layer substrate, by the pixel electrode on array base palte
With the direction of rotation that the electric field that public electrode is formed changes liquid crystal molecule so as to adjust the amount light that can pass through, realize to image
Display.
In the manufacturing process of liquid crystal, moveable foreign ion is inevitably remained in liquid crystal, in liquid crystal quilt
When applying electric field, foreign ion can be subject to the attraction of electric charge opposite to that on electrode and be moved to electrode, if in array base
The voltage of identical polar is persistently remained on the electrode of plate（Namely DC offset voltage（DC bias））, for example, applying just to pixel
During negative alternating voltage, if positive voltage is higher than negative voltage, positivity bias voltage is formed, the bias voltage can attract in liquid crystal cell
Foreign ion forms internal electric field.The electric field can cause the liquid crystal molecule can not to reply initial position with desired speed, thus
Influence liquid crystal arrangement and penetration, change liquid crystal T-V curves so that even if completely not applied voltage when, the arrangement of liquid crystal
Can be different from original alignment state, and then cause the image for wishing away to remain on liquid crystal display device, form ghost
（Image Sticking）, influence the performance of liquid crystal display device.
In the prior art, the characteristics of arrangement mode is constant under antipodal electric field action using liquid crystal molecule, generally
By applying to exchange data-signal on the data line and coordinating the SECO of grid line so that same sub-pixel on array base palte
Electrode voltage periodically polarity inversion, so that foreign ion is moved back and forth with the upset of polarity of electrode, and then avoids
Foreign ion aggregation causes ghost phenomena to occur.Existing polarity inversion technology includes face polarity inversion, row polarity inversion and point
Polarity inversion.
Wherein, face polarity inversion is that the pixel electrode polarity of whole array base palte is just in a certain cycle, in next week
Phase is negative.Row polarity inversion is the pixel electrode opposite polarity in a certain cycle odd-numbered line and even number line, in next cycle
The polarity of the pixel electrode of parity rows is exchanged.Point-polarity is reversed to the pixel electrode polarity phase of the adjacent subpixels within a certain cycle
The anti-pixel electrode polarity in next cycle adjacent subpixels is exchanged.
Wherein, using point-polarity technology thin-film transistor array base-plate performance preferably, but, its SECO and number
Extremely complex according to driving, manufacturing process difficulty is larger, and power consumption is very high.
The content of the invention
It is an object of the invention to propose a kind of thin-film transistor array base-plate and liquid crystal display including the array base palte
Device, while ghost phenomena is reduced or eliminated, reduces power consumption and simplifies manufacturing process.
The invention discloses a kind of thin-film transistor array base-plate, including：
First transparency conducting layer and the second transparency conducting layer, first transparency conducting layer and second transparency conducting layer
It is insulated from each other；
Multiple sub-pixels；
The pixel electrode of first transparency conducting layer including first kind sub-pixel group and Equations of The Second Kind sub-pixel group it is public
Electrode；
The pixel electrode of second transparency conducting layer including Equations of The Second Kind sub-pixel group and first kind sub-pixel group it is public
Electrode；
The first kind sub-pixel group is disposed adjacent with Equations of The Second Kind sub-pixel group on the array base palte, and first kind
Pixel groups are non-conterminous each other, and Equations of The Second Kind sub-pixel group is non-conterminous each other.
Preferably, the first kind sub-pixel group is that pixel electrode is located at the first transparency conducting layer, and public electrode is located at the
The sub-pixel group of two transparency conducting layers；
The Equations of The Second Kind sub-pixel group is that pixel is located at the second transparency conducting layer, and public electrode is located at the first transparency conducting layer
Sub-pixel group.
Preferably, the sub-pixel group by independent sub-pixel group into；Or
The sub-pixel group includes at least two sub-pixels being disposed adjacent.
Preferably, also including viewing area；The public electrode pattern of first transparency conducting layer is transparent with described second to lead
The public electrode pattern of electric layer forms electrical connection outside the viewing area of the array base palte.
Preferably, the public electrode of the public electrode pattern of first transparency conducting layer and second transparency conducting layer
Pattern is formed at the array base palte edge and electrically connected, or forms electrical connection by substrate external circuit.
Preferably, the pixel electrode mutually insulated ground of first transparency conducting layer is set；
The pixel electrode mutually insulated ground of second transparency conducting layer is set.
Preferably, the substrate is applied in plane switching（IPS）Liquid crystal display device.
Preferably, it is provided with insulating barrier between first transparency conducting layer and the second transparency conducting layer.
Preferably, the electric field periodic inversion between the pixel electrode and public electrode.
The invention also discloses a kind of liquid crystal display device, it includes any one thin film transistor (TFT) array as described above
Substrate.
Set-up mode by changing array base palte pixel electrode and public electrode of the invention so that adjacent sub-pixel
Pixel electrode and the reverse setting of public electrode so that be applied in data wire applying identical polar signal, namely pixel electrode
In the case of DC offset voltage, remain to cause adjacent subpixels direction of an electric field conversely, by frame invert type of drive both
The effect of point pole sex reversal can be realized, ghost phenomena generation can be eliminated or reduce.
Brief description of the drawings
Fig. 1 is the schematic cross-section of the thin-film transistor array base-plate of first embodiment of the invention；
Fig. 2 a are the distribution of electrodes of the first transparency conducting layer of the thin-film transistor array base-plate of first embodiment of the invention
Schematic diagram；
Fig. 2 b are the distribution of electrodes of the second transparency conducting layer of the thin-film transistor array base-plate of first embodiment of the invention
Schematic diagram；
Fig. 2 c are the distribution of electrodes schematic diagrames of the first transparency conducting layer of another implementation method of first embodiment of the invention；
Fig. 2 d are the distribution of electrodes schematic diagrames of the second transparency conducting layer of another implementation method of first embodiment of the invention；
Fig. 2 e are the distribution of electrodes schematic diagrames of the first transparency conducting layer of another implementation method of first embodiment of the invention；
Fig. 2 f are the distribution of electrodes schematic diagrames of the second transparency conducting layer of another implementation method of first embodiment of the invention；
Fig. 2 g are the distribution of electrodes schematic diagrames of the first transparency conducting layer of another implementation method of first embodiment of the invention；
Fig. 2 h are the distribution of electrodes schematic diagrames of the second transparency conducting layer of another implementation method of first embodiment of the invention；
Fig. 3 a are the schematic cross section schematic diagrames of the thin-film transistor array base-plate of first embodiment of the invention；
Fig. 3 b are that Electric Field Distribution of the thin-film transistor array base-plate of first embodiment of the invention before polarity inversion is illustrated
Figure；
Fig. 3 c are that Electric Field Distribution of the thin-film transistor array base-plate of first embodiment of the invention after polarity inversion is illustrated
Figure；
Fig. 4 is the schematic cross-section of the thin-film transistor array base-plate of second embodiment of the invention；
Fig. 5 a are the first transparency conducting layer schematic diagrames of the thin-film transistor array base-plate of second embodiment of the invention；
Fig. 5 b are the schematic diagrames of the second transparency conducting layer of the thin-film transistor array base-plate of second embodiment of the invention.
Specific embodiment
Further illustrate technical scheme below in conjunction with the accompanying drawings and by specific embodiment.
Embodiment one
Fig. 1 is the schematic cross-section of the thin-film transistor array base-plate of first embodiment of the invention.It is brilliant that Fig. 1 has intercepted film
Two sections of adjacent sub-pixel unit on body pipe array base palte, show the first sub-pixel 10a and adjacent thereto in Fig. 1
Second sub-pixel 10b.Thin-film transistor array base-plate include substrate 11, the substrate 11 can be transparent material, such as glass,
The multiple sub-pixels on glass substrate 11 are formed at, each pixel includes the thin film transistor (TFT) for constituting pixel switch element
12.In Fig. 1, for convenience of explanation, thin film transistor (TFT) 12 shows that those skilled in the art can manage in the form of segment
Solution, it can also be multiple, its class for depending on used pixel switch element that the quantity of thin film transistor (TFT) 12 can be one
Type, and thin film transistor (TFT) 12, indeed through by semiconductor layer, insulating barrier and metal level are with specific structure multilayer layer
The folded active semiconductor device for being formed, thin film transistor (TFT) any existing and well known in the art may be applicable to this implementation
Example.
The corresponding thin film transistor (TFT) all same of all of sub-pixel on array base palte.Passivation layer 14 is covered in thin film transistor (TFT)
The insulating barrier for being available for being formed electrode is formed on 12, one can be formed in other embodiments of the invention, on passivation layer 14 flat
Change layer.Array base palte also includes the first transparency conducting layer 15 for patterning, the insulating barrier being formed on the first transparency conducting layer 15
16 and the second transparency conducting layer 17 of patterning for being formed on insulating barrier 16.
In the present embodiment, the sub-pixel of thin-film transistor array base-plate is divided into first kind sub-pixel group and Equations of The Second Kind sub-pixel
Group, the first kind sub-pixel group is that pixel electrode is located at the first transparency conducting layer 15, and public electrode is located at the second electrically conducting transparent
The sub-pixel group of layer 17；The Equations of The Second Kind sub-pixel group is that pixel electrode is located at the second transparency conducting layer 17, and public electrode is located at
The sub-pixel group of the first transparency conducting layer 15.
As shown in figure 1, the first sub-pixel 10a is first kind sub-pixel group, including positioned at the picture of the first transparency conducting layer 15
Plain electrode 151 and the public electrode 171 positioned at the second transparency conducting layer 17.
Second sub-pixel 10b is Equations of The Second Kind sub-pixel group, including positioned at the He of public electrode 152 of the first transparency conducting layer 15
Positioned at the pixel electrode 172 of the second transparency conducting layer 17.
In the present embodiment, the first kind sub-pixel group and Equations of The Second Kind sub-pixel group are on thin-film transistor array base-plate
It is disposed adjacent, and first kind sub-pixel group is non-conterminous each other, Equations of The Second Kind sub-pixel group is non-conterminous each other.
In the present embodiment, sub-pixel or sub-pixel group " adjacent " refer to the array of sub-pixels arranged in matrix array mode
Or in sub-pixel group, two sub-pixels or sub-pixel group are mutually adjoined or are mutually adjoined in the row direction on the column direction of array
It is adjacent.
In the present embodiment in the implementation method shown in Fig. 1, sub-pixel group is made up of an independent sub-pixel, Ye Jiyi
Individual sub-pixel is to constitute a sub-pixel group.Thus, the first sub-pixel 10a constitutes a first kind sub-pixel group, that is, first
Class sub-pixel group is spaced sub-pixel, for example, for including the N*M array of sub-pixel, first kind sub-pixel group can
With the sub-pixel that the sub-pixel and 2n+1 rows 2m+1 that are arranged including all 2n+2 rows 2m+2 on array base palte are arranged（N=0,
1 ... ..., N；N=0,1 ... ..., M）.
Similarly, the second sub-pixel 10b constitutes Equations of The Second Kind sub-pixel group.Equations of The Second Kind sub-pixel group is and first kind sub-pixel
The sub-pixel that group is disposed adjacent, in the above example, for including the N*M array of sub-pixel, Equations of The Second Kind sub-pixel group can
With the sub-pixel that the sub-pixel and 2n+1 rows 2m+2 that are arranged including all 2n+2 rows 2m+1 on array base palte are arranged（N=0,
1 ... ..., N；N=0,1 ... ..., M）.
Fig. 2 a show the electrode of the first transparency conducting layer of the thin-film transistor array base-plate of first embodiment of the invention
Distribution schematic diagram.Fig. 2 a show first transparency conducting layer of 3*3 array of sub-pixels, as shown in Figure 2 a, for adjacent
The pixel region of sub-pixel, corresponding electrode type is different, that is, one in the first transparency conducting layer of two adjacent sub-pixels
Individual formation pixel electrode 21a（Identified with P in figure）, another is formed as public electrode 22a（Identified with C in figure）.Wherein, first
Mutually insulated ground is set between pixel electrode 21a on transparency conducting layer, and the public electrode 22a shapes on the first transparency conducting layer
Pattern into connection so that form electrical connection each other.
In the present invention, " connection " refer to pattern any two points between all exist connection path.
In fig. 2 a, understand for convenience, pixel electrode and public electrode only show that those skilled in the art can with letter
To understand, pixel electrode can as needed be formed as strip, polyline shaped, herring-bone form or other existing or known pattern shapes
Shape.Similarly, public electrode can also as needed be formed as different shapes, as long as the common electrical on same transparency conducting layer
Extremely it is interconnected.
Fig. 2 b show the distribution of electrodes schematic diagram of the second transparency conducting layer of the array base palte of first embodiment of the invention.
Corresponding with Fig. 2 a, the second transparency conducting layer shown in Fig. 2 b is formed with the sub-pixel of pixel electrode in the first transparency conducting layer
The second transparency conducting layer formed corresponding sub-pixel public electrode 21b, be formed with public electrode in the first transparency conducting layer
Second transparency conducting layer of sub-pixel forms the pixel electrode 22b of corresponding sub-pixel.Identical with the first transparency conducting layer, second is saturating
In bright conductive layer, for adjacent pixel region, corresponding conductive pattern type is different, that is, two adjacent pixel regions,
One formation pixel electrode 21b, another forms public electrode 22b.Wherein, the pixel electrode on the second transparency conducting layer 17
21b mutually insulateds ground is set, and public electrode 22b on the second transparency conducting layer forms the pattern of connection so as to shape each other
Into electrical connection.
Wherein, the public electrode 152 of the first transparency conducting layer 15 communicates with each other, second transparency conducting layer 17 it is public
Electrode 172 communicates with each other.That is, in the first transparency conducting layer 15, the public affairs of the corresponding sub-pixel of all Equations of The Second Kind sub-pixel groups
Common electrode 152 is interconnected, and thus, the public electrode pattern of all Equations of The Second Kind sub-pixel groups is electrically connected each other.Correspondingly,
In the second transparency conducting layer 17, the public electrode 172 of the corresponding sub-pixel of all first kind sub-pixel groups is interconnected, by
This, the public electrode of the corresponding sub-pixel of all first kind sub-pixel groups is electrically connected each other.
In another preferred embodiment of the present embodiment, the sub-pixel group may be formed as including at least two
The sub-pixel being disposed adjacent.Fig. 2 c and Fig. 2 d are respectively first transparency conducting layer and the second transparency conducting layer of present embodiment
Distribution of electrodes schematic diagram.As shown in Fig. 2 c and Fig. 2 d, in the present embodiment, each sub-pixel group includes adjacent in the row direction
Two sub-pixels for setting, thus, on the first transparency conducting layer 15（Fig. 2 c）, the pixel electrode of each first kind sub-pixel group
（Represented with alphabetical P in figure）Pixel electrode 21a1,21a2 in the pixel region adjacent including being arranged on line direction；Each
The public electrode of two class sub-pixel groups（Represented with letter C in figure）Public affairs in the pixel region adjacent including being arranged on line direction
Common electrode 22a1 and 22a2.Meanwhile, on the second transparency conducting layer 17（Fig. 2 d）, the public electrode of each first kind pixel groups
（Represented with letter C in figure）Public electrode 21b1 and 21b2 in the pixel region adjacent including being arranged on line direction；Each
The pixel electrode of Equations of The Second Kind sub-pixel group（Represented with alphabetical P in figure）In the pixel region adjacent including being arranged on line direction
Pixel electrode 22b1 and 22b2.
First kind sub-pixel group and the equal interval setting of Equations of The Second Kind sub-pixel group, that is, first kind sub-pixel group is only with second
Class sub-pixel group is disposed adjacent, and first kind sub-pixel group is non-conterminous each other, and Equations of The Second Kind sub-pixel group is non-conterminous each other.
As shown in Figure 2 c, on the first transparency conducting layer 15, the pixel electrode of the sub-pixel of each first kind sub-pixel group except with its
Outside the pixel electrode of the sub-pixel in affiliated sub-pixel group is disposed adjacent, with the sub-pixel of other first kind sub-pixel groups
Pixel electrode is non-conterminous, meanwhile, the public electrode of the sub-pixel of each Equations of The Second Kind sub-pixel group except with the sub- picture belonging to it
The public electrode of the sub-pixel in plain group be disposed adjacent it is outer, with the public electrode of the sub-pixel of other Equations of The Second Kind sub-pixel groups not
It is adjacent.Similarly, as shown in Figure 2 d, on the second transparency conducting layer 17, the pixel of the sub-pixel of each Equations of The Second Kind sub-pixel group
Electrode in addition to the pixel electrode with the sub-pixel in the sub-pixel group belonging to it is disposed adjacent, with other Equations of The Second Kind sub-pixel groups
Sub-pixel pixel electrode it is non-conterminous, meanwhile, the public electrode of the sub-pixel of each first kind sub-pixel group except with its
The public electrode of the sub-pixel in affiliated sub-pixel group is disposed adjacent outer, the public affairs with the sub-pixel of other first kind sub-pixel groups
Common electrode is non-conterminous.
It will be understood by those skilled in the art that the quantity of sub-pixel that sub-pixel group is included is not limited to two, can be three
It is individual or more.Certainly, it will also be appreciated that sub-pixel group scale is bigger, the effect of its display can correspondingly be deteriorated, but manufacturing process
Difficulty can be reduced.
In another preferred embodiment of the present embodiment, the sub-pixel in the sub-pixel group can also be in row side
To being disposed adjacent.Fig. 2 e and Fig. 2 f are respectively the first transparency conducting layer of present embodiment and the electrode point of the second transparency conducting layer
Cloth schematic diagram.As shown in Fig. 2 e and Fig. 2 f, in the present embodiment, pixel electrode letter P is represented, public electrode letter C
Represent.Each sub-pixel group includes two sub-pixels being disposed adjacent in the row direction.First kind sub-pixel group and Equations of The Second Kind
Pixel groups are disposed adjacent, and first kind sub-pixel group is non-conterminous each other, and Equations of The Second Kind sub-pixel group is non-conterminous each other.
In another preferred embodiment of the present embodiment, the sub-pixel in the sub-pixel group can also include with battle array
What row mode was arranged be expert at, and column direction distinguishes 4 adjacent sub-pixels.Fig. 2 g and Fig. 2 h are respectively the first saturating of present embodiment
The distribution of electrodes schematic diagram of bright conductive layer and the second transparency conducting layer.As shown in Fig. 2 g and Fig. 2 h, in the present embodiment, pixel
Electrode letter P represents that public electrode is represented with letter C.First kind sub-pixel group and Equations of The Second Kind sub-pixel group are disposed adjacent, the
One class sub-pixel group is non-conterminous each other, and Equations of The Second Kind sub-pixel group is non-conterminous each other.
Fig. 3 a are the schematic cross section schematic diagrames of the array base palte of first embodiment of the invention.As shown in the above description, it is adjacent
Sub-pixel public electrode and pixel electrode be mutually opposing reverse setting, the opposite polarity that adjacent sub-pixel is formed
Remnant DC voltages make the direction of an electric field that liquid crystal molecule is reset conversely, in for Fig. 3, negatively charged foreign ion aggregation
Near the pixel electrode on upper strata, positively charged foreign ion is gathered near the position of public electrode, and due to adjacent
The position of its pixel electrode of pixel and public electrode is reverse, and thus, in the region of pixel 31, its foreign ion is formed upwards
The electric field in direction, and in the region of adjacent pixel 32, foreign ion forms electric field in downward direction, is consequently formed foreign ion
Electric field alternately changes with pixel region direction.For example, the impurity in the region foreign ion electric field of pixel 32 and the region of pixel 31 from
Influence of the sub- electric field to liquid crystal arrangement is cancelled out each other.Thus, with pixel region alternately change foreign ion electric field can weaken or
Eliminate the appearance of ghost phenomena.
Meanwhile, it is distributed as shown in Figure 3 b in the direction of an electric field of the array base palte of the first frame first embodiment of the invention, wherein
"+" represents that direction of an electric field points to the second transparency conducting layer by the first transparency conducting layer, and "-" indicates that the second transparency conducting layer is pointed to
First transparency conducting layer, in the first frame, when data wire applies identical polar voltage signal, thin-film transistor array base-plate is presented
The alternate Electric Field Distribution of outgoing direction.If carrying out polarity inversion in the unification of the second frame data line voltage（Namely using face reversion
Mode is driven）, the direction of an electric field distribution of the array base palte of first embodiment of the invention as shown in Figure 3 c, then all of son
The direction of an electric field of pixel realizes reversion, and due to two types sub-pixel group interval setting, still forms the alternate electric field in direction point
Cloth, thus, the type of drive overturn by face can both realize an effect for upset.It is miscellaneous due to during polarity inversion
Matter ion can be moved back and forth such that it is able to avoid the aggregation of foreign ion to a certain extent, further with the change of direction of an electric field
Weaken or eliminate the appearance of ghost phenomena.
Thus, the present embodiment need not be to be capable of achieving dot inversion by the signal type of drive of high power consumption, weaken and eliminate
Ghost and flicker（Flicker）Phenomenon, simplifies the type of drive of array base palte, reduces product power consumption.
The public electrode being additionally, since in first transparency electrode layer is interconnected, and it is directly formed by transparent electrode layer
Electrical connection, similarly, the public electrode of second transparency electrode layer is interconnected, and it is directly formed by transparent electrode layer and is electrically connected
Connect, the public electrode of the first transparency conducting layer and the second transparency conducting layer forms connection outside the viewing area of array base palte
（Not shown in accompanying drawing）.The public electrode in different pixels region forms connection without going through via is manufactured in pixel region, keeps away
Exempted from due to pixel region exist via cause liquid crystal molecule disorderly row and and then there is the defect of light leak, but also with respect to
The mode of via connection increases the aperture opening ratio of array base palte.
Embodiment two
Fig. 4 be the present invention be second embodiment array base palte schematic cross-section.Fig. 4 is shown two on array base palte
The section of adjacent pixel cell.Thin-film transistor array base-plate includes substrate 41, polysilicon layer 42, gate insulator 43, bag
The first metal layer of the patterning of grid 44a and grid line 44b is included, the first protective layer 45 is arranged at figure on the first protective layer 45
The second metal layer 46 of change, the second protective layer 47 and the first transparency conducting layer 48 on the second protective layer 47, covering are saturating
The insulating barrier 49 of bright conductive layer 48 and the second transparency conducting layer 40 being formed in above insulating barrier 49.Wherein, the first protective layer 45
Second protective layer 47 is insulating barrier, and polysilicon layer 42 is used to constitute the active area of thin film transistor (TFT), and second metal layer 46 is by wearing
The via of saturating first protective layer 45 and insulating barrier 43 is connected the source electrode and drain electrode and and source to form thin film transistor (TFT) with active area
The data wire of level connection.Meanwhile, polysilicon layer 42 extends to the part Chong Die with grid line 442 and forms storage capacitor electrode, its with
A part for grid line 442 constitutes storage capacitance.
The array base palte of second embodiment of the invention employs top gate type list gate low-temperature polysilicon（LTPS）Film crystal
Pipe builds pixel-driving circuit.But above-mentioned transistor and circuit constituted mode are not construed as limiting the invention, ability
Field technique personnel are appreciated that bigrid low temperature polycrystalline silicon（LTPS）Thin film transistor (TFT) is constituted using other structures or material
Thin film transistor (TFT) go for the present embodiment, meanwhile, the present embodiment is also not intended to limit for the quantity of transistor.
In the first pixel region 4a, the first transparency conducting layer 48 is connected by penetrating the via of the second protective layer with drain electrode
Connect, so that the first transparency conducting layer 48 is formed with drain electrode electrically connecting so that the pattern 481 of the first transparency conducting layer 48 is formed
It is the pixel electrode of the first pixel region 4a, it is mutual with the first transparency conducting layer 482 in the second adjacent pixel region 4b
Insulation, in the absence of any electrical connection.In the first pixel region 4a, the second transparency conducting layer 40 is formed as public electrode 401.
Meanwhile, in the second pixel region 4b, the second transparency conducting layer 40 is by penetrating insulating barrier 49, the first electrically conducting transparent
The via of the protective layer 47 of layer 48 and second is connected with drain electrode so that the pattern 402 of the second transparency conducting layer 40 is formed as the second picture
The pixel electrode of plain region 4b, it is mutually exhausted with the pattern 401 of the second transparency conducting layer in the second adjacent pixel region 4b
Edge, in the absence of any electrical connection.In the second pixel region 4b, the first transparency conducting layer 48 forms public electrode 482.
Fig. 5 a are the pattern schematic diagrames of the first transparency conducting layer of the array base palte of second embodiment of the invention.Fig. 5 a show
One the first transparency conducting layer of 3*3 array of sub-pixels, as shown in Figure 5 a, for adjacent pixel region, corresponding electrode
Type is different, that is, in two adjacent pixel regions, one is the pixel electricity set with the electrode insulation of other pixel regions
Pole 51a.Pixel electrode 51a is formed as two ends connection and the strip shaped electric poles be arrangeding in parallel.In adjacent pixel region first is saturating
Bright conductive layer is then the public electrode 52a connected with the electrode of the pixel region at interval.There is the public electrode 52a strip to engrave
Sky, so as to form the public electrode of strip.
Meanwhile, in other embodiments, public electrode of the invention need to be the pattern with hollow out, otherwise, when public
When electrode is located at the second transparency conducting layer, the electric field that public electrode can be formed to the first transparency conducting layer and the second transparency conducting layer
Shielding is constituted, the second conductive layer has openwork part can be so that electric field avoids being shielded by the second transparency conducting layer.
Fig. 5 b are the pattern schematic diagrames of the second transparency conducting layer of the array base palte of second embodiment of the invention.With Fig. 5 a phases
Correspondence, the second transparency conducting layer shown in Fig. 5 b, the pixel region for being formed with pixel electrode in the first transparency conducting layer forms public affairs
Common electrode 51b, the region for being formed with public electrode in the first transparency conducting layer forms pixel electrode 52b.With the first electrically conducting transparent
Layer is identical, and in the second transparency conducting layer, for adjacent pixel region, corresponding conductive pattern type is different, that is, adjacent
Two pixel regions one are the pixel electrode patterns set with the electrode insulation of other pixel regions, and another is and interval
The electrode of pixel region forms the public electrode of connection.Wherein, the pattern of pixel electrode 51a is formed as two ends connection and parallel sets
The strip shaped electric poles put.The pattern of the public electrode 52a has strip hollow out.
The setting of pixel electrode and public electrode causes that described array base palte is applied to conversion hysteria in field（IPS）Liquid crystal
Showing device.
It will be understood by those skilled in the art that when needing design to be applied to other types of liquid crystal display device, pixel
The shape of electrode and public electrode can be formed as other existing or known shapes.
First transparency conducting layer 48 is connected with the public electrode of the second transparency conducting layer 40 in conductive layer, that is, different
Pixel region public electrode in conductive layer be interconnected, there is electrical connection.And two public electrodes of transparency conducting layer
Can realize electrically connecting by external circuit or in array base palte edge.Thus, the array base palte of the present embodiment without going through
Manufacture via in pixel region and form connection, it is to avoid due to pixel region exist via cause liquid crystal molecule disorderly row simultaneously and then
There is the defect of light leak, but also the aperture opening ratio of array base palte is increased with respect to the mode that via is connected.
The preferred embodiments of the present invention are the foregoing is only, is not intended to limit the invention, for those skilled in the art
For, the present invention can have various changes and change.It is all any modifications made within spirit and principles of the present invention, equivalent
Replace, improve etc., should be included within the scope of the present invention.
Claims (9)
1. a kind of thin-film transistor array base-plate, including：
First transparency conducting layer and the second transparency conducting layer, first transparency conducting layer and second transparency conducting layer are each other
Insulation；
Multiple sub-pixels；
First transparency conducting layer includes the pixel electrode of first kind sub-pixel group and the public electrode of Equations of The Second Kind sub-pixel group；
Second transparency conducting layer includes the pixel electrode of Equations of The Second Kind sub-pixel group and the public electrode of first kind sub-pixel group；
Multiple first kind sub-pixel groups are with multiple Equations of The Second Kind sub-pixel groups on the array base palte；Wherein, it is described
First kind sub-pixel group is disposed adjacent with the Equations of The Second Kind sub-pixel group, and all first kind sub-pixel groups are mutually non-conterminous,
All Equations of The Second Kind sub-pixel groups are mutually non-conterminous；
The sub-pixel group includes at least two sub-pixels being disposed adjacent；
The public electrode of the first transparency electrode layer is directly interconnected by first transparency electrode layer, and described second is saturating
The public electrode of prescribed electrode layer is directly interconnected by second transparency electrode layer.
2. thin-film transistor array base-plate according to claim 1, it is characterised in that the first kind sub-pixel group is picture
Plain electrode is located at the first transparency conducting layer, and public electrode is located at the sub-pixel group of the second transparency conducting layer；
The Equations of The Second Kind sub-pixel group is that pixel is located at the second transparency conducting layer, and public electrode is located at the son of the first transparency conducting layer
Pixel groups.
3. thin-film transistor array base-plate according to claim 1, it is characterised in that also including viewing area；Described first
The public electrode pattern of the public electrode pattern of transparency conducting layer and second transparency conducting layer is in the aobvious of the array base palte
Show and formed outside area electrical connection.
4. thin-film transistor array base-plate according to claim 3, it is characterised in that the public affairs of first transparency conducting layer
Common electrode pattern is formed at the array base palte edge with the public electrode pattern of second transparency conducting layer and electrically connected, or logical
Cross substrate external circuit and form electrical connection.
5. thin-film transistor array base-plate according to claim 1, it is characterised in that the picture of first transparency conducting layer
Plain electrode mutually insulated ground is set；
The pixel electrode mutually insulated ground of second transparency conducting layer is set.
6. thin-film transistor array base-plate according to claim 1, it is characterised in that the substrate is applied to IPS patterns
Liquid crystal display mode.
7. thin-film transistor array base-plate according to claim 1, it is characterised in that first transparency conducting layer and
Insulating barrier is provided between two transparency conducting layers.
8. thin-film transistor array base-plate according to claim 7, it is characterised in that the pixel electrode and public electrode
Between electric field periodic inversion.
9. a kind of liquid crystal display device, it is characterised in that including the thin film transistor (TFT) battle array as any one of claim 1-8
Row substrate.
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| CN104516142B (en) * | 2014-11-10 | 2018-03-23 | 上海天马微电子有限公司 | Display panel, preparation method thereof and display device |
| US10101836B2 (en) | 2015-07-27 | 2018-10-16 | Boe Technology Group Co., Ltd. | Array substrate with dual gate structure touch panel and display apparatus containing the same |
| CN104951143B (en) * | 2015-07-27 | 2020-05-08 | 京东方科技集团股份有限公司 | Array substrate, touch panel and display device |
| CN106249490A (en) * | 2016-09-09 | 2016-12-21 | 京东方科技集团股份有限公司 | Array base palte, display floater and display device |
| CN106896595A (en) | 2017-03-21 | 2017-06-27 | 京东方科技集团股份有限公司 | A kind of liquid crystal display panel, liquid crystal display device and its control method |
| CN110780473B (en) * | 2019-10-30 | 2022-07-01 | 昆山龙腾光电股份有限公司 | Liquid crystal display device and method for manufacturing the same |
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| CN1109918C (en) * | 1998-08-13 | 2003-05-28 | 日本电气株式会社 | Liquid crystal display |
| CN1971364A (en) * | 2005-11-23 | 2007-05-30 | 统宝光电股份有限公司 | Liquid crystal display devices and manufacturing method thereof |
| CN101097366A (en) * | 2006-06-30 | 2008-01-02 | Lg.菲利浦Lcd株式会社 | Thin film transistor substrate for liquid crystal display |
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| TW387997B (en) * | 1997-12-29 | 2000-04-21 | Hyundai Electronics Ind | Liquid crystal display and fabrication method |
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