CN107818771B - Tft array substrate and its driving method, display panel and display device - Google Patents
Tft array substrate and its driving method, display panel and display device Download PDFInfo
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- CN107818771B CN107818771B CN201711103879.2A CN201711103879A CN107818771B CN 107818771 B CN107818771 B CN 107818771B CN 201711103879 A CN201711103879 A CN 201711103879A CN 107818771 B CN107818771 B CN 107818771B
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- 239000000758 substrate Substances 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The invention discloses a kind of tft array substrate and driving method, display panel and display device, tft array substrate includes: multiple data lines；First order grid line unit~N grades of grid line units, each grid line unit include first grid polar curve and second gate line, and the first grid polar curve and second gate line in the grid line unit are adjacent；It and include first row pixel~N+2 row's pixel pixel region；Wherein, the first grid polar curve of i-stage grid line unit drives multiple pixels of i-th row's pixel, the second gate line of i-stage grid line unit drives multiple pixels of i-th+2 row's pixel, and multiple pixels that multiple pixels of first grid polar curve driving of i-stage grid line unit drive with the second gate line of i-stage grid line unit are alternately arranged on spatial position, 1≤i≤N, N are integer.It drives tft array substrate with corresponding points inversion mode, improves crosstalk phenomenon, improve display image effect.
Description
The application has an application date of 2014, 08 and 20, and an application number of 201410400. X, and the invention name is as follows: the patent refers to the field of 'semiconductor devices and electric solid state devices'.
Technical Field
The present invention relates to the field of display technologies, and in particular, to a Thin Film Transistor (TFT) array substrate, a driving method thereof, a display panel, and a display device.
Background
Liquid crystal display devices have advantages of light and thin profile, low power consumption, no radiation pollution, etc., and have been widely used in electronic products such as computers, personal digital assistants, and mobile phones. A conventional driving method of a liquid crystal display device includes: the liquid crystal display device adopting the Frame Inversion (Frame Inversion) mode, the Line Inversion (Line Inversion) mode and the Dot Inversion (Dot Inversion) mode and adopting the Dot Inversion mode as the driving mode improves the cross talk phenomenon and the display effect. The dot inversion method is that the voltage polarity of each pixel unit is opposite to the voltage polarity of four adjacent pixel units in the horizontal direction and the vertical direction.
Disclosure of Invention
In view of this, the present invention provides a TFT array substrate, a driving method, a display panel and a display device, which achieve a dot inversion method by driving the TFT array substrate, thereby improving a cross talk phenomenon and improving a display image effect.
The technical scheme provided by the invention comprises the following steps:
a TFT array substrate, comprising:
a plurality of data lines for transmitting data signals;
the first-Nth-stage gate line units are used for transmitting gate driving signals, each gate line unit comprises a first gate line and a second gate line, the first gate line and the second gate line in the gate line units are adjacent, and the first gate line and the second gate line of any gate line unit simultaneously transmit the gate driving signals;
and a pixel region including first to N +2 th rows of pixels;
the first gate line of the ith-level gate line unit is used for driving a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels of the (i +2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< ═ i < > N, and N is an integer.
A driving method for driving a TFT array substrate, the TFT array substrate comprising: a plurality of data lines for transmitting data signals;
the first-Nth-stage gate line units are used for transmitting gate driving signals, each gate line unit comprises a first gate line and a second gate line, the first gate line and the second gate line in the gate line units are adjacent, and the first gate line and the second gate line of any gate line unit simultaneously transmit the gate driving signals;
and a pixel region including first to N +2 th rows of pixels;
the first gate line of the ith-level gate line unit is used for driving a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels of the (i +2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< ═ i < (N), and N is an integer;
the driving method includes:
and scanning step by step along the first-stage gate line unit to the Nth-stage gate line unit, and transmitting data signals through the plurality of data lines, wherein after the ith-stage gate line unit is scanned, the polarity of the data signals of the plurality of data lines is reversed every time the ith-stage gate line unit is scanned.
A display panel comprising a TFT array substrate, the TFT array substrate comprising: a plurality of data lines for transmitting data signals;
the first-Nth-stage gate line units are used for transmitting gate driving signals, each gate line unit comprises a first gate line and a second gate line, the first gate line and the second gate line in the gate line units are adjacent, and the first gate line and the second gate line of any gate line unit simultaneously transmit the gate driving signals;
and a pixel region including first to N +2 th rows of pixels;
the first gate line of the ith-level gate line unit is used for driving a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels of the (i +2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< ═ i < > N, and N is an integer.
A display device comprising a display panel including a TFT array substrate, the TFT array substrate comprising: a plurality of data lines for transmitting data signals;
the first-Nth-stage gate line units are used for transmitting gate driving signals, each gate line unit comprises a first gate line and a second gate line, the first gate line and the second gate line in the gate line units are adjacent, and the first gate line and the second gate line of any gate line unit simultaneously transmit the gate driving signals;
and a pixel region including first to N +2 th rows of pixels;
the first gate line of the ith-level gate line unit is used for driving a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels of the (i +2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< ═ i < > N, and N is an integer.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
the invention provides a TFT array substrate, a driving method, a display panel and a display device, wherein the TFT array substrate comprises: a plurality of data lines for transmitting data signals; the first-Nth-stage gate line units are used for transmitting gate driving signals, each gate line unit comprises a first gate line and a second gate line, the first gate line and the second gate line in the gate line units are adjacent, and the first gate line and the second gate line of any gate line unit simultaneously transmit the gate driving signals; and a pixel region including first to N +2 th rows of pixels; the first gate line of the ith-level gate line unit is used for driving a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels of the (i +2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< i < > N, and N is an integer.
As can be seen from the above, when the first-stage gate line unit to the nth-stage gate line unit are scanned step by step, the data lines transmit data signals simultaneously, wherein after the ith-stage gate line unit is scanned, the polarity of the data signals of the data lines is inverted every time the two-stage gate line units are scanned. The TFT array substrate is driven by the method, so that the pixel units of two adjacent pixels with the same voltage polarity in each row of pixels are realized in a dot inversion mode with the polarities of the pixel units in the horizontal direction and the vertical direction being opposite, the cross crosstalk phenomenon is improved, and the image display effect is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1a is a schematic diagram of a TFT array substrate capable of implementing dot inversion according to an embodiment of the present disclosure;
fig. 1b is a schematic diagram of another TFT array substrate capable of implementing dot inversion according to an embodiment of the present disclosure;
fig. 2a is a schematic view of another TFT array substrate capable of implementing dot inversion according to an embodiment of the present disclosure;
fig. 2b is a schematic diagram of another TFT array substrate capable of implementing dot inversion according to an embodiment of the present disclosure;
fig. 3a is a schematic diagram of pixel polarity distribution when driving a TFT array substrate according to an embodiment of the present disclosure;
fig. 3b is a schematic view of a pixel polarity distribution when another TFT array substrate is driven according to an embodiment of the present disclosure;
fig. 3c is a schematic view of a pixel polarity distribution when another TFT array substrate is driven according to an embodiment of the present disclosure;
fig. 4 is a schematic view of another TFT array substrate capable of implementing dot inversion according to an embodiment of the present disclosure;
FIG. 5a is a schematic diagram illustrating an arrangement of gate line units according to an embodiment of the present disclosure;
FIG. 5b is a schematic diagram illustrating another arrangement of gate line units according to an embodiment of the present disclosure;
FIG. 5c is a schematic diagram illustrating another arrangement of gate line units according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a TFT array substrate according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, the dot inversion driving method is used to drive the lcd device, so as to improve the cross talk phenomenon and improve the image display effect.
Based on this, the present application provides a TFT array substrate capable of implementing two-point inversion, and the technical solution provided by the present application is described in detail with reference to fig. 1a to 2 b.
Wherein, TFT array substrate includes:
a plurality of data lines (D1-Dm) for transmitting data signals, the plurality of data lines (D1-Dm) are electrically connected to the source driving circuit 100, and transmit data signals under the control of the source driving circuit 100;
first to nth gate line units G1 to Gn for transmitting gate driving signals, each gate line unit being electrically connected to the gate driving circuit 200 and transmitting the gate driving signals under the control of the gate driving circuit 200, each gate line unit including a first gate line and a second gate line, and the first gate line and the second gate line of any one gate line unit simultaneously transmitting the gate driving signals, i.e. the first gate line and the second gate line of any one gate line unit are electrically connected and simultaneously transmit the gate driving signals of the same polarity;
and a pixel region including first row pixels P1 to N +2 th row pixels Pn + 2;
the first gate line Gi1 of the ith gate line unit Gi is used to drive the pixels P100 of the ith row of pixels Pi, the second gate line Gi2 of the ith gate line unit Gi is used to drive the pixels P200 of the (i +2) th row of pixels Pi +2, and the pixels P100 driven by the first gate line Gi1 of the ith gate line unit Gi and the pixels P200 driven by the second gate line Gi2 of the ith gate line unit Gi are arranged alternately in space, 1 ═ i ═ N, and N is an integer.
In the above, the plurality of pixels P100 driven by the first gate line Gi1 of the ith-stage gate line unit Gi and the plurality of pixels P200 driven by the second gate line Gi2 of the ith-stage gate line unit Gi are arranged alternately in spatial position. The plurality of pixels P100 driven by the first gate line Gi1 of the ith-stage gate line unit Gi and the plurality of pixels P200 driven by the second gate line Gi2 of the ith-stage gate line unit Gi are alternately arranged in spatial positions, i.e., in the direction X parallel to the ith-row pixels Pi. In addition, the multi-row pixels and the multi-level gate line units provided by the embodiment of the application are arranged along the direction Y, and the plurality of data lines are arranged along the direction (along the direction parallel to the ith row of pixels) X.
As described in more detail below, in the application of the actual display device, since the uniformity of the display screen of the display device is required, the arrangement of the pixels in the pixel region is uniform and regular. Therefore, according to the arrangement of the driving pixels of the ith gate line unit, the finally obtained pixel region includes not only the first row to the N +2 th row of pixels but also a plurality of pixel columns formed by the first row to the N +2 th row of pixels. Therefore, in the odd-numbered position and the even-numbered position described in the embodiment of the present application, that is, in the direction parallel to the ith row of pixels, any one end of the formed multiple rows of pixel rows is selected as the first pixel row, that is, the odd-numbered position; the next pixel column is at an even position, and the subsequent pixel columns alternate between odd and even positions.
In the TFT array substrate shown in fig. 1a to 2b according to the embodiment of the present application, in the direction X parallel to the ith row of pixels Gi, an end of each of the plurality of rows of pixels formed in the direction of the data line D1 is selected as a first row, that is, an odd-numbered position.
Referring to fig. 1a, a schematic diagram of a TFT array substrate capable of implementing a dot inversion scheme according to an embodiment of the present invention is shown, wherein a first gate line Gi1 of an i-th gate line unit Gi is electrically connected to a plurality of pixels P100 of an i-th row of pixels Pi at odd-numbered positions, and a second gate line Gi2 of the i-th gate line unit Gi is electrically connected to a plurality of pixels P200 of an i + 2-th row of pixels Pi +2 at even-numbered positions; or,
in other embodiments of the present application, the TFT array substrate may be distributed in another arrangement, and specifically, as shown in fig. 1b, another TFT array substrate capable of implementing a dot inversion scheme is provided in the embodiments of the present application, that is, the first gate line Gi1 of the i-th gate line unit Gi is electrically connected to the pixels P100 of the i-th row of pixels Pi at even positions, and the second gate line Gi2 of the i-th gate line unit Gi is electrically connected to the pixels P200 of the i + 2-th row of pixels Pi +2 at odd positions.
In the array substrate shown in fig. 1a and 1b, the pixels electrically connected to the first gate line of all the gate line units form a plurality of pixel rows, and the pixel rows electrically connected to the second gate line form a plurality of pixel rows arranged alternately. In another embodiment of the present invention, the first gate line and the second gate line of two adjacent gate line units may further be electrically connected to a plurality of pixels at different positions, specifically refer to fig. 2a and 2b, where, referring to fig. 2a, for a schematic diagram of another TFT array substrate capable of implementing a dot inversion scheme provided in the embodiment of the present invention, the first gate line Gi1 of the i-th gate line unit Gi is electrically connected to a plurality of pixels P100 of the i-th row of pixels Pi at odd positions, and the second gate line Gi2 of the i-th gate line unit Gi is electrically connected to a plurality of pixels of the i + 2-th row of pixels Pi +2 at even positions; the first gate line G (i +1)1 of the (i +1) th level gate line unit Gi +1 is electrically connected to the pixels P100 of the (i +1) th row of pixels Pi +1 at the even positions, the second gate line G (i +1)2 of the (i +1) th level gate line unit Gi +1 is electrically connected to the pixels P200 of the (i + 3) th row of pixels Pi +3 at the odd positions, and i is an odd number; or,
referring to fig. 2b, in order to provide a schematic diagram of another TFT array substrate capable of implementing a dot inversion scheme according to an embodiment of the present invention, a first gate line Gi1 of an i-th gate line unit Gi is electrically connected to a plurality of pixels P100 of an i-th row of pixels Pi at even positions, and a second gate line Gi2 of the i-th gate line unit Gi is electrically connected to a plurality of pixels of an i + 2-th row of pixels Pi +2 at odd positions; the first gate line G (i +1)1 of the (i +1) -th gate line unit Gi +1 is electrically connected to the pixels P100 of the (i +1) -th row Pi +1 at odd-numbered positions, the second gate line G (i +1)2 of the (i +1) -th gate line unit Gi +1 is electrically connected to the pixels P200 of the (i + 3) -th row Pi +3 at even-numbered positions, and i is an odd number.
As can be seen from fig. 2a and 2b, in the TFT array substrate provided in the embodiment of the present application, a plurality of pixels driven by the first gate line of two adjacent gate line units are alternately arranged in the direction X parallel to the ith row of pixels Pi; and a plurality of pixels driven by the second gate line of the two adjacent stages of gate line units are alternately arranged along the direction X parallel to the ith row of pixels Pi.
In addition, with the TFT array substrate provided in the embodiment of the present application, the second row of pixels P2 through the N +1 th row of pixels Pn +1 are respectively and correspondingly located between the first gate line and the second gate line of the first-stage gate line unit G1 through the nth-stage gate line unit Gn; and the first row of pixels P1 is located at a side of the first-stage gate line unit G1 facing away from the second-stage gate line unit G2, and the (N +2) th row of pixels Pn +2 is located at a side of the nth-stage gate line unit Gn facing away from the (N-1) th-stage gate line unit Gn-1.
Corresponding to the TFT array substrate provided in the foregoing embodiment, an embodiment of the present application further provides a driving method for driving the TFT array substrate provided in the foregoing embodiment, where the TFT array substrate includes:
a plurality of data lines (D1-Dm) for transmitting data signals;
first to nth gate line units G1-Gn for transmitting gate driving signals, each gate line unit including a first gate line and a second gate line, the first gate line and the second gate line of any one gate line unit simultaneously transmitting the gate driving signals;
and a pixel region including first row pixels P1 to N +2 th row pixels Pn + 2;
wherein, the first gate line of the ith-level gate line unit is used for driving a plurality of pixels P100 of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels P200 of the (i +2) th row of pixels, and the plurality of pixels P100 driven by the first gate line of the ith-level gate line unit and the plurality of pixels P200 driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< i < > N, N is an integer, the driving method comprises:
the gate line units G1 of the first stage to the gate line units Gn of the nth stage are scanned stepwise, and data signals are transmitted through the plurality of data lines (D1 to Dm), wherein the polarity of the data signals of the plurality of data lines (D1 to Dm) is inverted every two-stage scanning of the gate line units when the gate line units of the ith stage are scanned.
Referring to fig. 3a, a schematic diagram of a pixel polarity distribution when driving a TFT array substrate according to an embodiment of the present invention is shown, wherein i may be defined as 1, and a polarity of a data signal of a plurality of data lines (D1-Dm) when scanning a first-stage gate line unit G1 is opposite to a polarity of a data signal of a plurality of data lines (D1-Dm) when scanning a second-stage gate line unit G2 and a third-stage gate line unit G3. That is, the polarity of the data signals of the plurality of data lines (D1 to Dm) when the first-stage gate line cell G1 is scanned is the same as the polarity of the data signals of the plurality of data lines (D1 to Dm) when the fourth-stage gate line cell G4 and the fifth-stage gate line cell G5 are scanned.
Alternatively, referring to fig. 3b, another schematic diagram of the pixel polarity distribution when driving the TFT array substrate according to the embodiment of the present application is shown, where i may be defined as 2, and the polarity of the data signals of the data lines (D1 to Dm) when scanning the first-stage gate line unit G1 and the second-stage gate line unit G2 is opposite to the polarity of the data signals of the data lines (D1 to Dm) when scanning the third-stage gate line unit G3 and the fourth-stage gate line unit G4. That is, the data signal polarities of the plurality of data lines (D1 to Dm) when the first-stage gate line cell G1 and the second-stage gate line cell G2 are scanned are the same as the data signal polarities of the plurality of data lines (D1 to Dm) when the fifth-stage gate line cell G5 and the sixth-stage gate line cell G6 are scanned.
The pixel distribution structure in the TFT array substrate shown in fig. 3a and 3b is consistent with the pixel distribution structure in the TFT array substrate shown in fig. 1a and 1b, and a plurality of pixels driven by the first gate line and the second gate line of all gate line units are arranged correspondingly. When selecting the pixel distribution structure to be: among all the gate line units, a plurality of pixels driven by the first gate line of two adjacent gate line units are alternately arranged in the direction parallel to the ith row of pixels Pi; and when the TFT array substrate is arranged in a direction parallel to the ith row of pixels Pi alternately between the plurality of pixels driven by the second gate line of the two adjacent gate line units, as shown in fig. 3c, a schematic view of pixel polarity distribution when driving the TFT array substrate is provided for according to another embodiment of the present application:
i is defined as 1, and the polarity of the data signals of the plurality of data lines (D1 to Dm) when the first-stage gate line cell G1 is scanned is opposite to the polarity of the data signals of the plurality of data lines (D1 to Dm) when the second-stage gate line cell G2 and the third-stage gate line cell G3 are scanned. That is, the polarity of the data signals of the plurality of data lines (D1 to Dm) when the first-stage gate line cell G1 is scanned is the same as the polarity of the data signals of the plurality of data lines (D1 to Dm) when the fourth-stage gate line cell G4 and the fifth-stage gate line cell G5 are scanned.
As can be seen from the above, when the TFT array substrate is driven by the driving method provided in the above embodiment, the pixel units of two adjacent pixels having the same voltage polarity in each row of pixels are implemented in a dot inversion manner, where the polarities of the pixel units in the horizontal direction and the vertical direction are opposite, so that the cross talk phenomenon is improved, and the image display effect is improved.
Further, referring to fig. 4, a schematic diagram of another TFT array substrate capable of implementing dot inversion according to an embodiment of the present application is shown; wherein, TFT array substrate includes:
a plurality of data lines (D1-Dm) for transmitting data signals, the plurality of data lines (D1-Dm) are electrically connected to the source driving circuit 100, and transmit data signals under the control of the source driving circuit 100;
first to nth gate line units G1 to Gn for transmitting gate driving signals, each gate line unit being electrically connected to the gate driving circuit 200 and transmitting the gate driving signals under the control of the gate driving circuit 200, each gate line unit including a first gate line and a second gate line, and the first gate line and the second gate line of any one gate line unit simultaneously transmitting the gate driving signals, i.e. the first gate line and the second gate line of any one gate line unit are electrically connected and simultaneously transmit the gate driving signals of the same polarity;
and a pixel region including first row pixels P1 to N +2 th row pixels Pn + 2;
the first gate line of the ith-level gate line unit is used for driving a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels of the (i +2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< i < > N, and N is an integer.
The TFT array substrate further includes: a compensation gate line unit including at least one of the first compensation gate line G1 ', the second compensation gate line G2', the third compensation gate line G3 'and the fourth compensation gate line G4';
the first compensation gate line G1' is used for driving a plurality of first compensation pixels P300, and the plurality of first compensation pixels P300 are located in the first row of pixels P1 and are alternately arranged with the plurality of pixels driven by the first gate line G11 of the first level gate line unit G1; the second compensation gate line G2' is used for driving a plurality of second compensation pixels P400, and the plurality of second compensation pixels P400 are located in the second row of pixels P2 and are alternately arranged with the plurality of pixels driven by the first gate line G21 of the second level gate line unit G2;
the third compensation gate line G3' is for driving a plurality of third pixels P500, and the plurality of third compensation pixels P500 are located at the N +1 th row of pixels Pn +1 and are alternately arranged with the plurality of pixels driven by the second gate line G (N-1)2 of the N-1 th level gate line unit Gn-1;
the fourth compensation gate line G4' is used to drive a plurality of fourth compensation pixels P600, and the plurality of fourth compensation pixels P600 are located at the N +2 th row of pixels Pn +2 and are alternately arranged with the plurality of pixels driven by the second gate line Gn2 of the nth-order gate line unit Gn.
In the embodiment of the present application, the gate line compensation unit shown in fig. 4 includes a first gate line compensation to a fourth gate line compensation. In other embodiments of the present application, the compensated gate line unit may further include a single gate line of the first to fourth compensated gate lines, or a plurality of gate lines of the first to fourth compensated gate lines, which is not particularly limited.
Referring to fig. 4, a driving method of the TFT array substrate according to the embodiment includes:
scanning step by step along the first to fourth compensation gate lines G1 'to G4' and transmitting data signals through the plurality of data lines (D1 to Dm), wherein the polarity of the data signals of the plurality of data lines (D1 to Dm) is negative when the first and second compensation gate lines G1 'and G2' are scanned; when the first gate line unit G1 and the second gate line unit G2 are scanned, the polarities of the data signals of the data lines (D1 to Dm) are positive, and the polarities of the data signals of the data lines (D1 to Dm) are inverted every two subsequent stages of scanning the gate line units;
and the polarity of the data signals of the plurality of data lines (D1-Dm) when the nth gate line unit and the third compensation gate line G3 'are scanned is opposite to the polarity of the data signals of the plurality of data lines (D1-Dm) when the fourth compensation gate line G4' is scanned, at this time, the number of the N-level gate line units on the TFT array substrate is odd;
and if the number of the N-level gate line units on the TFT array substrate is even, the polarity of the data signals of the plurality of data lines when the N-1 level gate line unit and the N-level gate line unit are scanned is opposite to the polarity of the data signals of the plurality of data lines when the third compensation gate line and the fourth compensation gate line are scanned.
For the driving method of the TFT array substrate including the first to fourth compensation gate lines, partial steps of the driving method may further include:
when scanning the first compensation gate line and the second compensation gate line and transmitting data signals through the plurality of data lines, adjusting the polarity of the data signals of the plurality of data lines to be positive; when the first gate line unit and the second gate line unit are scanned, the polarity of the data signals of the data lines is adjusted to be negative, and the polarity of the data signals of the data lines is reversed every time the two stages of gate line units are scanned; or,
the driving method may further include:
adjusting the polarity of the data signals of the plurality of data lines to a first polarity when scanning the first compensation gate line while scanning step by step along the first compensation gate line to the fourth compensation gate line and transmitting the data signals through the plurality of data lines; adjusting the polarity of the data signals of the plurality of data lines when scanning the second compensation gate line and the first gate line cell G1 to a second polarity opposite to the first polarity, and subsequently, every time two levels of gate line cells are scanned, the polarity of the data signals of the plurality of data lines is reversed;
and when the number of the N-level gate line units on the TFT array substrate is odd, the polarity of the data signals of the plurality of data lines when the N-1 level gate line unit and the N-level gate line unit are scanned is opposite to the polarity of the data signals of the plurality of data lines when the third compensation gate line and the fourth compensation gate line are scanned;
when the number of the N-level gate line units on the TFT array substrate is even, the polarity of the data signals of the plurality of data lines when the N-level gate line unit and the third compensation gate line are scanned is opposite to the polarity of the data signals of the plurality of data lines when the fourth compensation gate line is scanned.
It should be noted that, for the TFT array substrate including the compensation gate line unit in the present application, a suitable driving method needs to be selected according to the number of the compensation gate lines in the compensation gate line unit, so as to finally implement the dot inversion method.
Secondly, this application embodiment still provides a display panel, including TFT array substrate, TFT array substrate includes: a plurality of data lines for transmitting data signals;
the first-Nth gate line units are used for transmitting gate driving signals, each gate line unit comprises a first gate line and a second gate line, and the first gate line and the second gate line of any one gate line unit simultaneously transmit the gate driving signals;
and a pixel region including first to N +2 th rows of pixels;
the first gate line of the ith-level gate line unit is used for driving a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels of the (i +2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< i < > N, and N is an integer.
Finally, an embodiment of the present application further provides a display device, and as shown in fig. 7, the display device includes a display panel 71 and a housing 72, the display panel 71 includes a TFT array substrate, and the TFT array substrate includes: a plurality of data lines for transmitting data signals;
the first-Nth gate line units are used for transmitting gate driving signals, each gate line unit comprises a first gate line and a second gate line, and the first gate line and the second gate line of any one gate line unit simultaneously transmit the gate driving signals;
and a pixel region including first to N +2 th rows of pixels;
the first gate line of the ith-level gate line unit is used for driving a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels of the (i +2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< i < > N, and N is an integer.
In the TFT array substrate provided in all the above embodiments of the present application, the gate line units may be arranged in any manner, and reference is made to fig. 5a to 5c, which are schematic diagrams illustrating the arrangement of three gate line units provided in the embodiments of the present application.
Referring to fig. 5a, the gate line units may be arranged in an in-cell manner, wherein the first gate line G (i +1)1 of the (i +1) -th level gate line unit Gi +1 is located between the first gate line Gi1 and the second gate line Gi2 of the (i) -th level gate line unit Gi; the second gate line G (i +1)2 of the (i +1) -th level gate line unit Gi +1 is positioned between the first gate line G (i +2)1 and the second gate line G (i +2)2 of the (i +2) -th level gate line unit Gi + 2.
Referring to fig. 5b, the gate line units may be arranged in an externally embedded manner, wherein the first gate line G (i +1)1 and the second gate line G (i +1)2 of the (i +1) th stage gate line unit Gi +1 are located between the (i) th stage gate line unit Gi and the (i +2) th stage gate line unit Gi + 2.
Alternatively, referring to fig. 5c, a hybrid arrangement may be adopted between the gate line units, wherein the second gate line Gi2 of the ith gate line unit Gi is located between the first gate line G (i +1)1 and the second gate line G (i +1)2 of the (i +1) th gate line unit Gi +1, and i is an odd number.
In addition, in the TFT array substrate provided in all the above embodiments of the present application, in order to reduce the output nodes of the gate driving circuit, in any gate line unit provided in the embodiments of the present application, the first gate line is electrically connected to the second gate line, and the input end of the first gate line is connected to the input end of the second gate line. In order to increase the number of pixels and improve the display effect, in the first-stage gate line unit to the nth-stage gate line unit, the signal input terminal of the odd-numbered gate line unit and the signal input terminal of the even-numbered gate line unit are respectively disposed at two sides of the pixel region and are opposite to each other (see fig. 5a to 5 c).
In order to reduce the manufacturing cost and simplify the manufacturing process, when manufacturing the TFT array substrate, the embodiment of the present application may be manufactured by using a midle-com structure, that is, referring to fig. 6, a schematic structural diagram of the TFT array substrate provided in the embodiment of the present application sequentially includes a substrate 61, a first conductive layer 62, a first insulating layer 63, a silicon island layer 64, a second conductive layer 65, a second insulating layer 66, a third conductive layer 67, a third insulating layer 68, and a fourth conductive layer 69; wherein,
the first conductive layer 62 includes first to nth stage gate line units and a plurality of gates;
the silicon island layer 64 includes a plurality of silicon islands corresponding to the gates;
the second conductive layer 65 includes the plurality of data lines, a plurality of source/drain electrodes corresponding to the silicon islands, a plurality of gate electrodes, and a plurality of source/drain electrodes forming TFT transistors;
the third conductive layer 67 includes a common electrode;
the fourth conductive layer 69 includes a plurality of pixel electrodes.
It should be noted that the TFT array substrate provided in the embodiments of the present application may also be manufactured by using other structures, and is not limited to the midle-com structure. And, for the material of each layer structure is the same as the existing material, detailed description is not repeated in this application embodiment.
The embodiment of the application provides a TFT array substrate, a driving method, a display panel and a display device, wherein the TFT array substrate comprises: a plurality of data lines for transmitting data signals; the first-Nth gate line units are used for transmitting gate driving signals, each gate line unit comprises a first gate line and a second gate line, and the first gate line and the second gate line of any one gate line unit simultaneously transmit the gate driving signals; and a pixel region including first to N +2 th rows of pixels; the first gate line of the ith-level gate line unit is used for driving a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels of the (i +2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< i < > N, and N is an integer.
As can be seen from the above, when scanning is performed step by step along the first-stage gate line unit to the nth-stage gate line unit, the data lines transmit data signals simultaneously, wherein after the ith-stage gate line unit is scanned, the polarities of the data signals of the data lines are inverted every subsequent scanning of the two-stage gate line units, so that the pixel units of two adjacent pixels having the same voltage polarity in each row of pixels are inverted, and the dot inversion manner is implemented in which the polarities of the pixel units in the horizontal direction and the vertical direction are opposite, thereby improving the cross-talk phenomenon and improving the image display effect.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (15)
1. A TFT array substrate, comprising:
a plurality of data lines for transmitting data signals;
the first-Nth-stage gate line units are used for transmitting gate driving signals, each gate line unit comprises a first gate line and a second gate line, the first gate line and the second gate line in the gate line units are adjacent, and the first gate line and the second gate line of any gate line unit simultaneously transmit the gate driving signals;
and a pixel region including first to N +2 th rows of pixels;
the first gate line of the ith-level gate line unit is used for driving a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels of the (i +2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< ═ i < > N, and N is an integer.
2. The TFT array substrate of claim 1, wherein the second row to the N +1 th row of pixels are respectively disposed between the first gate line and the second gate line of the first to the nth gate line units;
and the first row of pixels are positioned on one side of the first-level gate line unit, which is deviated from the second-level gate line unit, and the (N +2) th row of pixels are positioned on one side of the Nth-level gate line unit, which is deviated from the (N-1) th-level gate line unit.
3. The TFT array substrate of claim 1, wherein a first gate line of the i-th gate line unit is electrically connected to the pixels of the i-th row of pixels at odd-numbered positions, and a second gate line of the i-th gate line unit is electrically connected to the pixels of the i + 2-th row of pixels at even-numbered positions; or,
the first gate line of the ith gate line unit is electrically connected to the pixels of the ith row of pixels at even positions, and the second gate line of the ith gate line unit is electrically connected to the pixels of the (i +2) th row of pixels at odd positions.
4. The TFT array substrate of claim 1, wherein a first gate line of the i-th gate line unit is electrically connected to the pixels of the i-th row of pixels at odd-numbered positions, and a second gate line of the i-th gate line unit is electrically connected to the pixels of the i + 2-th row of pixels at even-numbered positions; the first gate line of the (i +1) th level gate line unit is electrically connected to the pixels of the (i +1) th row of pixels at the even positions, the second gate line of the (i +1) th level gate line unit is electrically connected to the pixels of the (i + 3) th row of pixels at the odd positions, and i is an odd number; or,
the first gate line of the ith gate line unit is electrically connected to the pixels of the ith row of pixels at even positions, and the second gate line of the ith gate line unit is electrically connected to the pixels of the (i +2) th row of pixels at odd positions; and the first gate line of the (i +1) th level gate line unit is electrically connected to the pixels of the (i +1) th row of pixels at odd-numbered positions, the second gate line of the (i +1) th level gate line unit is electrically connected to the pixels of the (i + 3) th row of pixels at even-numbered positions, and i is an odd number.
5. The TFT array substrate of claim 1, further comprising a compensation gate line unit including at least one of a first compensation gate line, a second compensation gate line, a third compensation gate line, and a fourth compensation gate line;
the first compensation gate line is used for driving a plurality of first compensation pixels, and the plurality of first compensation pixels are positioned in the first row of pixels and are alternately arranged with the plurality of pixels driven by the first gate line of the first-stage gate line unit;
the second compensation gate line is used for driving a plurality of second compensation pixels, and the second compensation pixels are positioned in the second row of pixels and are alternately arranged with the pixels driven by the first gate line of the second-level gate line unit;
the third compensation gate line is used for driving a plurality of third compensation pixels, and the plurality of third compensation pixels are positioned in the (N +1) th row of pixels and are alternately arranged with the plurality of pixels driven by the second gate line of the (N-1) th level gate line unit;
the fourth compensation gate line is used for driving a plurality of fourth compensation pixels, and the plurality of fourth compensation pixels are located in the (N +2) th row of pixels and are alternately arranged with the plurality of pixels driven by the second gate line of the nth-level gate line unit.
6. The TFT array substrate of claim 1, wherein the first gate line of the i +1 th stage gate line unit is located between the first gate line and the second gate line of the i th stage gate line unit;
the second gate line of the (i +1) th stage gate line unit is positioned between the first gate line and the second gate line of the (i +2) th stage gate line unit.
7. The TFT array substrate of claim 1, wherein the first gate line and the second gate line of the (i +1) th stage gate line unit are positioned between the (i) th stage gate line unit and the (i +2) th stage gate line unit.
8. The TFT array substrate of claim 1, wherein in any gate line unit, the first gate line is electrically connected to the second gate line, and an input end of the first gate line is connected to an input end of the second gate line.
9. The TFT array substrate of claim 8, wherein, of the first-nth stage gate line units, the signal input terminals of the odd-numbered gate line units and the signal input terminals of the even-numbered gate line units are respectively disposed opposite to each other on both sides of the pixel region.
10. The TFT array substrate according to claim 1, comprising a substrate, a first conductive layer, a first insulating layer, a silicon island layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, and a fourth conductive layer in this order; wherein,
the first conductive layer comprises the first-Nth-level gate line units and a plurality of gates;
the silicon island layer comprises a plurality of silicon islands corresponding to the grid;
the second conductive layer comprises a plurality of data lines, a plurality of source/drain electrodes corresponding to the silicon islands, and a TFT transistor formed by the plurality of grid electrodes and the plurality of source/drain electrodes;
the third conductive layer includes a common electrode;
the fourth conductive layer includes a plurality of pixel electrodes.
11. A driving method for driving a TFT array substrate, the TFT array substrate comprising: a plurality of data lines for transmitting data signals;
the first-Nth-stage gate line units are used for transmitting gate driving signals, each gate line unit comprises a first gate line and a second gate line, the first gate line and the second gate line in the gate line units are adjacent, and the first gate line and the second gate line of any gate line unit simultaneously transmit the gate driving signals;
and a pixel region including first to N +2 th rows of pixels;
the first gate line of the ith-level gate line unit is used for driving a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels of the (i +2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< ═ i < (N), and N is an integer;
the driving method includes:
and scanning step by step along the first-stage gate line unit to the Nth-stage gate line unit, and transmitting data signals through the plurality of data lines, wherein after the ith-stage gate line unit is scanned, the polarity of the data signals of the plurality of data lines is reversed every time the ith-stage gate line unit is scanned.
12. The driving method as claimed in claim 11, wherein i is 1, and a polarity of data signals of the plurality of data lines when the first-stage gate line unit is scanned is opposite to a polarity of data signals of the plurality of data lines when the second-stage gate line unit and the third-stage gate line unit are scanned.
13. The driving method as claimed in claim 11, wherein i is 2, and a polarity of data signals of the plurality of data lines when the first-stage gate line unit and the second-stage gate line unit are scanned is opposite to a polarity of data signals of the plurality of data lines when the third-stage gate line unit and the fourth-stage gate line unit are scanned.
14. A display panel comprising a TFT array substrate, the TFT array substrate comprising: a plurality of data lines for transmitting data signals;
the first-Nth-stage gate line units are used for transmitting gate driving signals, each gate line unit comprises a first gate line and a second gate line, the first gate line and the second gate line in the gate line units are adjacent, and the first gate line and the second gate line of any gate line unit simultaneously transmit the gate driving signals;
and a pixel region including first to N +2 th rows of pixels;
the first gate line of the ith-level gate line unit is used for driving a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels of the (i +2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< ═ i < > N, and N is an integer.
15. A display device comprising a display panel including a TFT array substrate, the TFT array substrate comprising: a plurality of data lines for transmitting data signals;
the first-Nth-stage gate line units are used for transmitting gate driving signals, each gate line unit comprises a first gate line and a second gate line, the first gate line and the second gate line in the gate line units are adjacent, and the first gate line and the second gate line of any gate line unit simultaneously transmit the gate driving signals;
and a pixel region including first to N +2 th rows of pixels;
the first gate line of the ith-level gate line unit is used for driving a plurality of pixels of the ith row of pixels, the second gate line of the ith-level gate line unit is used for driving a plurality of pixels of the (i +2) th row of pixels, the plurality of pixels driven by the first gate line of the ith-level gate line unit and the plurality of pixels driven by the second gate line of the ith-level gate line unit are alternately arranged in spatial position, 1< ═ i < > N, and N is an integer.
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| CN201711103879.2A CN107818771B (en) | 2014-08-20 | 2014-08-20 | Tft array substrate and its driving method, display panel and display device |
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| CN201410410400.XA CN104155821B (en) | 2014-08-20 | 2014-08-20 | TFT array substrate and its driving method, display panel and display device |
| CN201711103879.2A CN107818771B (en) | 2014-08-20 | 2014-08-20 | Tft array substrate and its driving method, display panel and display device |
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| US10269839B2 (en) * | 2015-03-26 | 2019-04-23 | Carestream Health, Inc. | Apparatus and method using a dual gate TFT structure |
| CN107272282B (en) * | 2017-08-08 | 2020-05-19 | 深圳市华星光电技术有限公司 | Display panel and display with same |
| CN110082978B (en) * | 2019-05-22 | 2022-11-08 | 京东方科技集团股份有限公司 | Array substrate, driving method thereof and display device |
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| JP4401090B2 (en) * | 2003-03-14 | 2010-01-20 | パナソニック株式会社 | Display device and driving method thereof |
| KR101006450B1 (en) * | 2004-08-03 | 2011-01-06 | 삼성전자주식회사 | Liquid crystal display |
| KR20070041988A (en) * | 2005-10-17 | 2007-04-20 | 삼성전자주식회사 | Thin film transistor array panel and liquid crystal display |
| KR101286516B1 (en) * | 2006-11-27 | 2013-07-16 | 엘지디스플레이 주식회사 | Liquid Crystal Display and Driving Apparatus thereof |
| KR101264710B1 (en) * | 2006-11-30 | 2013-05-16 | 엘지디스플레이 주식회사 | A liquid crystal display device and a metal for driving the same |
| TW201237842A (en) * | 2011-03-15 | 2012-09-16 | Hannstar Display Corp | Liquid crystal display and controller and driving method of panel thereof |
| CN102750916B (en) * | 2011-04-18 | 2015-01-21 | 晨星软件研发(深圳)有限公司 | Thin film transistor array capable of completely inversing dots and liquid crystal display panel thereof |
| CN103514846A (en) * | 2012-06-29 | 2014-01-15 | 北京京东方光电科技有限公司 | Liquid crystal display and driving method thereof |
| CN202886797U (en) * | 2012-11-21 | 2013-04-17 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
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