CN103888807B - High-definition decoding middleware system of intelligent television and decoding method - Google Patents
High-definition decoding middleware system of intelligent television and decoding method Download PDFInfo
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Abstract
The invention discloses a high-definition decoding middleware system of an intelligent television. The high-definition decoding middleware system comprises a software application layer, a hardware layer and high-definition decoding middleware. The high-definition decoding middleware is arranged between the software application layer and the hardware layer. The high-definition decoding middleware provides a service interface for the software application layer and manages and visits the hardware layer. The high-definition decoding middleware comprises a decoding drive module and an SDK interface module, wherein the decoding drive module is used for hardware-controlled programs; and the SDK interface module provides external program interfaces. The invention also provides a decoding method. The decoding method comprises the following steps: step 1: system initialization; step 2: data transmission; step3: after data judging, transmitting the data to a video card through a DMA; and step4: carrying out decompression processing on the data and then playing the data. According to the high-definition decoding middleware system of the intelligent television and the decoding method, a video decoding drive program is packaged and the development SDK interface is provided, so that modules are easier to transplant, and the application layer is provided with simple, fast and flexible development interface, operational process is standardized, and user customizing programs are provided with convenience.
Description
Technical field
The present invention relates to a kind of middleware system of intelligent television, particularly relate to a kind of high definition decoding middleware system and coding/decoding method of intelligent television.
Background technology
Current, HDTV (High-Definition Television) is more and more welcome, and the very important feature of existing intelligent television, except variation and intelligent on software, video is the broadcasting supporting HD video.TV is in the past different, and intelligent television will embody the opening of its platform more.High definition processing module being carried out middleware module is the good selection allowing program more easily transplant.
HDTV (High-Definition Television) (being also HDTV) is different from the conventional television system of current employing analog signal transmission, and high definition have employed digital data transmission.Because HDTV is from the collection of TV programme, the transmission being fabricated into TV programme, and all realize digitlization to the reception of user terminal, therefore HDTV brings high definition to us, and resolution reaches as high as 1920 × 1080, and frame per second is up to 60fps.Realize high definition to play, the very important link of the process of HD video data is decoded exactly.In fact, in intelligent television, decoding seems very important.Existing have a lot of ripe decoding standard, also has very many most advanced encoding and decoding techniques carrying out improving on standard.
Present decoding generally designs and is closely related with hardware, provides decoding and drives.Manufacturer does not provide open application interface to developer on this basis, exploitation (SoftwareDevelopment Kit is not more provided, SDK, i.e. SDK), make TV applications exploitation lag far behind other such as Internet application and development.Present decoder module is the video drive be closely related with hardware, and it is one deck of adaptive hardware; But it does not provide more open and easy-to-use platform to upper strata developer, make the application and development carried out on this basis very limited, be difficult to the application and development ecosphere enlivened on intelligent television.In addition, existing decoding design modularization is not enough, and external interface is few, and coupling is too high, is not easy to transplant.
Therefore, be necessary to provide a kind of high definition of intelligent television decoding middleware system and coding/decoding method to solve existing defect.
Summary of the invention
The invention provides a kind of high definition decoding middleware system and coding/decoding method of intelligent television, traditional decoding task can not only be competent at, and provide SDK for upper layer application, be beneficial to upper layer application simple, develop fast and flexibly.
The invention provides a kind of high definition decoding middleware system of intelligent television, comprise software application layer, hardware layer and high definition decoding middleware, described high definition decoding middleware is between software application layer and hardware layer, described high definition decoding middleware provides service interface for software application layer and manages and access hardware layer, described high definition decoding middleware comprises decoding driver module and SDK interface module, described decoding driver module is used for the program of hardware controls, and described SDK interface module provides external routine interface.
Correspondingly, present invention also offers a kind of coding/decoding method of high definition decoding middleware system of intelligent television, comprise the following steps: step 1: system initialization, the control inerface of software application layer calls SDK interface, and the function call driving function of SDK carries out initialization, return state information after Initialize installation success; Step 2: transfer of data, first writes data to the buffer stopper in internal memory, then applies for DMA passage; Step 3: after data are judged, data are transferred to video card by DMA; Step 4: video card carries out decompression processing to data, then plays.
Particularly, described system initialization comprises configuration internal register, the firmware of loading required for coding mode, loads coding parameter, runs firmware program.
Particularly, described system initialization step comprises: step 101: reset, carried out the reset of chip by the reset position of the system register CTRL_REG of the structure in control FPGA; Step 102: internal clocking is set, internal clocking is used for timing or counting, and the setting of internal clocking is very necessary on the control circuitry, and it is also the key realizing upper strata cyclic program; Step 103: wait for PLL locking, if the setting in PLL register has been changed, then must have the time delay of at least 20us, to ensure that PLL relocks after changing setting; Step 104: enter non-load host mode, enters non-load host mode Boot pattern and is set to non-load host mode, and under this pattern, DSP can all internal registers of accessing video chip; Step 105: loading firmware; Step 106: enter coprocessor Boot pattern, association's tupe and non-load host mode collaborative work, complete the loading of firmware; Step 107: coding parameter and FIFO threshold value are set; Step 108: check whether firmware loads correctly, remove interrupt flag bit, enable DFTH interrupts; Step 109: judge that whether IRQ pin is effective, continue test if not, otherwise go to step 110; Step 110: second time judges that whether IRQ pin is effective, if effectively, go to step 111; Otherwise go to step 112; Step 111: last byte is read out FIFO; Step 112: read coding FIFO, empty flag bit, go to step 109.
Particularly, described transfer of data comprises the following steps: step 21: application program sends request by DeviceIOControl interface to the IO manager of operating system; Step 22:IO manager according to this request structure IRP, and will pass to corresponding Device Object; Step 23: queue up in the corresponding DMA request queue of device object according to device id and FIFO ID; After step 24:DMA IRP dequeue, process in corresponding DMA thread; Request result is returned application program by step 25:IO manager.
Particularly, the processing procedure of described step 24 comprises: application DMA passage; Prepare Scatter-GatherList; Order dma controller starts DMA transmission; DMA is transmitted, and dma controller produces and interrupts, and driver handles is interrupted, and notifies IO manager successful operation; If do not receive this interruption within a certain period of time, then driver returns overtime failure code to IO management.
Compared with prior art, the high definition decoding middleware system of intelligent television provided by the present invention and coding/decoding method, its high definition decoding middleware comprises decoding driver module and SDK interface module, traditional decoding task can not only be competent at, and carry SDK for upper layer application, be beneficial to upper layer application simple, develop fast and flexibly.By adopting the form of middleware, the video decode driver be closely related with graphic chips being encapsulated, exploitation SDK interface is provided; Make module be easier to transplant, simultaneously for upper layer application provides simple and fast and development interface flexibly, standard operation flow process, for customization program is provided convenience.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of the high definition decoding middleware system of the intelligent television of the embodiment of the present invention;
Fig. 2 is the schematic flow sheet of the coding/decoding method of the high definition decoding middleware system of the intelligent television of the embodiment of the present invention;
Fig. 3 is that the software application layer of the embodiment of the present invention is to the schematic flow sheet of the access control of hardware layer;
Fig. 4 is the schematic flow sheet of initialization step in Fig. 2;
Fig. 5 is the schematic flow sheet of data transmission step in Fig. 2;
Fig. 6 is another schematic flow sheet of data transmission step in Fig. 2;
Fig. 7 is the structural representation of SDK interface module in Fig. 1.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
With reference to figure 1, the invention provides a kind of high definition decoding middleware system of intelligent television, comprise software application layer, hardware layer and high definition decoding middleware, described high definition decoding middleware is between software application layer and hardware layer, described high definition decoding middleware provides service interface for software application layer and manages and access hardware layer, described high definition decoding middleware comprises decoding driver module and SDK interface module, described decoding driver module is used for the program of hardware controls, and described SDK interface module provides external routine interface.
With reference to figure 2, present invention also offers a kind of coding/decoding method of high definition decoding middleware system of intelligent television, comprise the following steps:
S001: system initialization, the control inerface of software application layer calls SDK interface, and the function call driving function of SDK carries out initialization, return state information after Initialize installation success;
S002: transfer of data, first writes data to the buffer stopper in internal memory, then applies for DMA passage;
S003: after data are judged, data are transferred to video card by DMA;
S004: video card carries out decompression processing to data, then plays.
With reference to figure 3, software application layer uses decoding to drive, and is also video drive, and the application program of software application layer is as follows to the operating system of hardware layer, the access of resource, control flow:
Step1: application program sends I/O request, and now application program is in user model.Program one is being divided into user model and kernel mode, and general application is in user model, and system kernel, driving supervisor are in kernel mode; The authority of the two is different;
Step2: operating system I/O manager receives the I/O operation requests of application program, identifies the resource of this application request, then searches corresponding driver, carries out IR interruption;
Step3: decoding drives takes over execution authority from interruption, to access accordingly and controls, then result returned according to the request of application to hardware resource;
This execution result is returned to application program by Step4: operating system I/O manager further, terminates.
With reference to figure 4, decoding driving will work, and must carry out initialization, the work mainly completed has: configuration internal register, the firmware of loading required for coding mode, loading coding parameter, operation firmware program.Concrete steps comprise:
Step 101: reset, carried out the reset of chip by the reset position of the system register CTRL_REG of the structure in control FPGA;
Step 102: internal clocking is set, internal clocking is used for timing or counting, and the setting of internal clocking is very necessary on the control circuitry, and it is also the key realizing upper strata cyclic program;
Step 103: wait for PLL locking, if the setting in PLL register has been changed, then must have the time delay of at least 20us, to ensure that PLL relocks after changing setting;
Step 104: enter non-load host mode, enters non-load host mode Boot pattern and is set to non-load host mode, and under this pattern, DSP can all internal registers of accessing video chip;
Step 105: loading firmware;
Step 106: enter coprocessor Boot pattern, association's tupe and non-load host mode collaborative work, complete the loading of firmware;
Step 107: coding parameter and FIFO threshold value are set;
Step 108: check whether firmware loads correctly, remove interrupt flag bit, enable DFTH interrupts;
Step 109: judge that whether IRQ pin is effective, continue test if not, otherwise go to step 110;
Step 110: second time judges that whether IRQ pin is effective, if effectively, go to step 111; Otherwise go to step 112;
Step 111: last byte is read out FIFO;
Step 112: read coding FIFO, empty flag bit, go to step 109.
Upon initialization, transmission data and order are carried out in decoding driving, for application service.Mainly comprise two kinds, one is common apparatus method; One is DMA method.The former is applicable to most hardware platform, and the latter can utilize the platform possessing DMA passage to provide the transfer of data of high speed more.
With reference to figure 5, application program asks to send request to the I/O manager of operating system by I/O; Manager is asked to device object by IR object; In device object, task is distributed, by request forward to corresponding equipment control function by task distribution function Dispatch; Equipment control function carries out equipment control to hardware resource, finally successively returns execution result again.
With reference to figure 6, particularly, described transfer of data comprises the following steps:
Step 21: application program sends request by DeviceIOControl interface to the IO manager of operating system;
Step 22:IO manager according to this request structure IRP, and will pass to corresponding DeviceObject;
Step 23: queue up in the corresponding DMA request queue of device object according to device id and FIFO ID;
After step 24:DMA IRP dequeue, process in corresponding DMA thread; Request result is returned application program by step 25:IO manager.
Particularly, the processing procedure of described step 24 mainly comprises: application DMA passage; Prepare Scatter-GatherList; Order dma controller starts DMA transmission; DMA is transmitted, and dma controller produces and interrupts, and driver handles is interrupted, and notifies IO manager successful operation; If do not receive this interruption within a certain period of time, then driver returns overtime failure code to IO management.
SDK interface module is an encapsulation to first floor system, for upper layer application provides a simple interface and flow process.Graph Control interface, is generally the control inerface of application program, has carried out the access to first floor system by video SDK; SDK comprises decoding initialization according to the flow process controlled, buffer memory, files loading, decompress(ion), process terminate to reclaim several module.With reference to figure 7, this flow process comprises the following steps:
Step1: initialization.Major function is startup board, loads and enable file, starts DMA decoding thread etc.;
Step2: cache test and distribution.Whether test buffer memory has vacant position, and returns true as having vacant position, otherwise false, and can buffer memory be distributed;
Step3: files loading, reads internal memory by file from disk;
Step4: decompress(ion).Data are carried out decompress(ion) preliminary treatment; Then by the control of video drive to video card, by video card, decompress(ion) is carried out to data;
Step5: decompress(ion) is complete, terminates process, release buffer memory, closing device.
Compared with prior art, the high definition decoding middleware system of intelligent television provided by the present invention and coding/decoding method, its high definition decoding middleware comprises decoding driver module and SDK interface module, traditional decoding task can not only be competent at, and carry SDK for upper layer application, be beneficial to upper layer application simple, develop fast and flexibly.By adopting the form of middleware, the video decode driver be closely related with graphic chips being encapsulated, exploitation SDK interface is provided; Make module be easier to transplant, simultaneously for upper layer application provides simple and fast and development interface flexibly, standard operation flow process, for customization program is provided convenience.In addition, in application communicates with the driving of middleware, common apparatus method is adopted to be easy to transplant on different hardware platforms; Adopt dma mode then greatly to accelerate the transmission speed of data, two kinds of methods respectively get advantage, not only maintain transplantability and also maintain treatment effeciency.
Above to the high definition decoding middleware system of a kind of intelligent television that the embodiment of the present invention provides, be described in detail, apply specific case herein to set forth principle of the present invention and execution mode, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (4)
1. the coding/decoding method of the high definition decoding middleware system of an intelligent television, the high definition decoding middleware system of described intelligent television comprises software application layer, hardware layer and high definition decoding middleware, described high definition decoding middleware is between software application layer and hardware layer, described high definition decoding middleware is answered layer to provide service interface for software and manages and access hardware layer, described high definition decoding middleware comprises decoding driver module and SDK interface module, described decoding driver module is used for the program of hardware controls, and described SDK interface module provides external routine interface; It is characterized in that: the method comprises the following steps:
Step 1: system initialization, the control inerface of software application layer calls SDK interface, and the function call driving function of SDK carries out initialization, return state information after Initialize installation success;
Step 2: transfer of data, first writes data to the buffer stopper in internal memory, then applies for DMA passage;
Step 3: after data are judged, data are transferred to video card by DMA;
Step 4: video card carries out decompression processing to data, then plays;
Described transfer of data comprises the following steps:
Step 21: application program sends request by DeviceIOControl interface to the IO manager of operating system;
Step 22:IO manager according to this request structure IRP, and will pass to corresponding DeviceObject;
Step 23: queue up in the corresponding DMA request queue of device object according to device id and FIFO ID;
After step 24:DMA IRP dequeue, process in corresponding DMA thread;
Request result is returned application program by step 25:IO manager.
2. the coding/decoding method of the high definition decoding middleware system of intelligent television according to claim 1, is characterized in that: described system initialization comprises configuration internal register, the firmware of loading required for coding mode, loads coding parameter, runs firmware program.
3. the coding/decoding method of the high definition decoding middleware system of intelligent television according to claim 2, is characterized in that: described system initialization step comprises:
Step 101: reset, carried out the reset of chip by the reset of the system register CTRL_REG of the structure in control FPGA;
Step 102: internal clocking is set, internal clocking is used for timing or counting, and the setting of internal clocking is very necessary on the control circuitry, and it is also the key realizing upper strata cyclic program;
Step 103: wait for PLL locking, if the setting in PLL register has been changed, then must have the time delay of at least 20us, to ensure that PLL relocks after changing setting;
Step 104: enter non-load host mode, enters non-load host mode Boot pattern and is set to non-load host mode, and under this pattern, DSP can all internal registers of accessing video chip;
Step 105: loading firmware;
Step 106: enter coprocessor Boot pattern, association's tupe and non-load host mode collaborative work, complete the loading of firmware;
Step 107: coding parameter and FIFO threshold value are set;
Step 108: check whether firmware loads correctly, remove interrupt flag bit, enable DFTH interrupts;
Step 109: judge that whether IRQ pin is effective, continue test if not, otherwise go to step 110;
Step 110: second time judges that whether IRQ pin is effective, if effectively, go to step 111; Otherwise go to step 112;
Step 111: last byte is read out FIFO;
Step 112: read coding FIFO, empty flag bit, go to step 109.
4. the coding/decoding method of the high definition decoding middleware system of intelligent television according to claim 1, is characterized in that: the processing procedure of described step 24 comprises: application DMA passage; Prepare Scatter-GatherList; Order dma controller starts DMA transmission; DMA is transmitted, and dma controller produces and interrupts, and driver handles is interrupted, and notifies IO manager successful operation; If do not receive this interruption within a certain period of time, then driver returns overtime failure code to IO manager.
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| CN110782889A (en) * | 2019-08-22 | 2020-02-11 | 腾讯科技（深圳）有限公司 | Voice operation method and related equipment |
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| CN201444684U (en) * | 2009-06-19 | 2010-04-28 | 济南中维世纪科技有限公司 | Multimedia bridge for multi-channel real-time video transmission |
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Inventor after: Liu Hailiang Inventor after: Su Hang Inventor after: Yang Ailin Inventor after: Luo Xiaonan Inventor after: Lin Zheqi Inventor after: Wang Xuansheng Inventor before: Luo Xiaonan Inventor before: Yang Ailin Inventor before: Liu Hailiang Inventor before: Su Hang Inventor before: Lin Zheqi Inventor before: Wang Xuansheng |
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