CN103887418B

CN103887418B - Luminescence chip is combined

Info

Publication number: CN103887418B
Application number: CN201210561892.3A
Authority: CN
Inventors: 赖志成
Original assignee: Scienbizip Consulting Shenzhen Co Ltd
Current assignee: Scienbizip Consulting Shenzhen Co Ltd
Priority date: 2012-12-22
Filing date: 2012-12-22
Publication date: 2017-06-30
Anticipated expiration: 2032-12-22
Also published as: CN103887418A

Abstract

A kind of luminescence chip combination, the first semiconductor layer, luminescent layer, the second semiconductor layer and the electrode for electrically connecting and stacking gradually with substrate including electrically-conductive backing plate, substrate include at least one of multiple electric current obstacles, arrangement density and size of electric current obstacle from substrate at the position of counter electrode towards reduction at substrate periphery position.Due to the stop of electric current obstacle, the electric current introduced from electrode can be dispersed in whole chip, so as to equably excite luminescent layer to light.

Description

Luminescence chip is combined

Technical field

The present invention relates to a kind of chip portfolio, a kind of luminescence chip combination is particularly related to.

Background technology

Light emitting diode has been widely used in the middle of various uses as emerging light source.Light emitting diode is usual Packaging body including pedestal, the chip being installed on pedestal and covering chip.Chip is grown on the N on substrate by substrate and successively Type semiconductor layer, luminescent layer and p type semiconductor layer composition.Chip can also respectively on its n type semiconductor layer and p type semiconductor layer P electrode and N electrode are formed, is electrically connected with pedestal.Currently, it is that its substrate is directly manufactured using conductive material to have segment chip , industry is normally referred to as vertical conducting cake core.The substrate of this kind of chip can make directly as the electrode of n type semiconductor layer With, thus this kind of chip only can form P electrode at the top of its p type semiconductor layer.During work, electric current enters chip from P electrode It is interior, and exported to pedestal via substrate.

However, the P electrode of this kind of vertical conducting cake core often only covers the mesozone at the top of p type semiconductor layer Domain, also tends to concentrate on the middle part of chip when causing electric current to be transmitted in chip, the electric current of chip two side areas is then less.By This, there is the few situation in middle many both sides, the light for causing chip central region to be excited by electric current in distribution of the electric current in chip Line will be more than the light that chip two side areas are excited by electric current, chip is equably lighted.This kind of situation is in large area Chip in the middle of become apparent, badly influence the normal of chip and use.

The content of the invention

Therefore, it is necessary to provide a kind of luminescence chip combination with uniform light output.

A kind of luminescence chip combination, including the first semiconductor that electrically-conductive backing plate is electrically connected and stacked gradually with electrically-conductive backing plate Layer, luminescent layer, the second semiconductor layer and electrode, substrate include multiple electric current obstacles, in the density and size of these electric current obstacles At least one from the position of counter electrode towards substrate periphery reduce.

Because the density or size of electric current obstacle reduce from the position of counter electrode towards the periphery of substrate, therefore from electricity The electric current that pole enters in chip can spread under the stop of electric current obstacle to chip perimeter, so as to be evenly distributed in chip.Point The uniform electric current of cloth and then excite luminescent layer to send uniform light, chip is obtained preferable light-out effect.

With reference to the accompanying drawings, the invention will be further described in conjunction with specific embodiments.

Brief description of the drawings

Fig. 1 shows the luminescence chip combination of first embodiment of the invention.

Fig. 2 shows the luminescence chip combination of second embodiment of the invention.

Fig. 3 shows the luminescence chip combination of third embodiment of the invention.

Fig. 4 shows the luminescence chip combination of fourth embodiment of the invention.

Main element symbol description

Luminescence chip is combined	10
		Substrate	20
Conducting portion	22
		Electric current obstacle	24
First conductive layer	26
		Second conductive layer	28
Insulating barrier	29
		Chip	30
Substrate	32
		Groove	320
First semiconductor layer	34
		Luminescent layer	36
Second semiconductor layer	38
		Electrode	39
Wire	40

Following specific embodiment will further illustrate the present invention with reference to above-mentioned accompanying drawing.

Specific embodiment

Fig. 1 is referred to, the luminescence chip combination 10 of first embodiment of the invention is shown.Luminescence chip combination 10 includes one Substrate 20 and the chip 30 being fixed on substrate 20.

Chip 30 includes that substrate 32, the first semiconductor layer 34 being sequentially formed on substrate 32, luminescent layer 36, the second half lead Body layer 38 and electrode 39.In the present embodiment, substrate 32 is made up of conductive material, such as silicon, carborundum or metal material. When substrate 32 is manufactured using silicon or carborundum, the first semiconductor layer 34, the semiconductor layer 38 of luminescent layer 36 and second can directly give birth to It is longer than on substrate 32.Now the first semiconductor layer 34 is n type semiconductor layer, and the second semiconductor layer 38 is p type semiconductor layer.Work as base When plate 32 is manufactured using metal material, the second semiconductor layer 38, the semiconductor layer 34 of luminescent layer 36 and first are first to be grown in successively In one temporary substrate (not shown), metal substrate 32 is then formed on the first semiconductor layer 34 again, finally move temporary substrate Remove.Now the first semiconductor layer 34 is p type semiconductor layer, and the second semiconductor layer 38 is n type semiconductor layer.First semiconductor layer 34th, the semiconductor layer 38 of luminescent layer 36 and second can be using luminescent materials such as gallium nitride, InGaN and aluminum indium gallium nitrides It is made.Area of the area of electrode 39 less than the second semiconductor layer 38.Electrode 39 only covers the top surface of the second semiconductor layer 38 Central region and make the top surface of the second semiconductor layer 38 opposite sides expose outside.

Chip 30 is fixed on the top surface of substrate 20 by way of viscose glue or eutectic bonding.Substrate 20 by such as epoxy resin, The insulating materials such as silica gel or ceramics is made, and it has been internally formed multiple conducting portions 22.Each conducting portion 22 is by metal material system Into.When substrate 20 is manufactured by epoxy resin or silica gel, these conducting portions 22 can be positioned beforehand through positioning instrument, then substrate 20 are formed on conducting portion 22 by injecting the modes such as shaping.When substrate 20 is by ceramics manufacture, these conducting portions 22 can be with pottery Porcelain thin slice is together molded by LTCC Technology.These conducting portions 22 are respectively positioned on the underface of chip 30, and each lead Logical portion 22 extends to the bottom surface of substrate 20 from the top surface of substrate 20.In the present embodiment, the size all same of each conducting portion 22, and lead The distribution density in logical portion 22 is from the position of 30 electrode of correspondence chip 39 towards being gradually reduced at the peripheral position of substrate 20.Every two is adjacent Conducting portion 22 between form an electric current obstacle 24.Due to the size of conducting portion 22 is identical and arranging density from centre to both sides by It is decrescence small, thus the arranging density of the electric current obstacle 24 defined by conducting portion 22 keeps constant, but size is (i.e. right from centre Answer at the position of 30 electrode of chip 39) it is gradually reduced to both sides (i.e. at the peripheral position of counterpart substrate 20).

Substrate 20 forms the first conductive layer 26 and the second conductive layer 28 respectively in its top surface and bottom surface.First conductive layer 26 with Chip 30 separates, and is connected with the electrode 39 at the top of chip 30 by a wire 40.Second conductive layer 28 connects all conducting portions 22 bottom surface.Thus, the electrode 39 of chip 30 is electrically connected with the first conductive layer 26, the conductive layer 28 of substrate 32 and second of chip 30 Electrical connection.Electric current can be input into chip 30 (with the first semiconductor layer 34 for N-type is partly led via the first conductive layer 26 from electrode 39 As a example by body layer), then exported from the second conductive layer 28 by conducting portion 22 again.In transmitting procedure, due to electric current obstacle 24 Size is gradually reduced from centre to both sides, thus the electric current for entering chip 30 from electrode 39 will be by the obstruction of electric current obstacle 24 Disperse to both sides from the middle part of chip 30, so as to flow evenly through chip 30.Therefore, in the case where equally distributed electric current is excited, chip 30 can send uniform light, so as to obtain preferable light-out effect.

It is to be appreciated that as shown in Fig. 2 the size of the electric current obstacle 24 of aforesaid substrate 20 can also keep identical, but arrangement Density is gradually reduced from middle (corresponding at the position of 30 electrode of chip 39) to both sides (i.e. at the peripheral position of counterpart substrate 20), together Sample can play a part of equalizing current.Certainly, the size of electric current obstacle 24 and arrangement density can also change simultaneously, i.e., from right Answer and be gradually reduced towards the periphery of the first semiconductor layer of chip 34 at the position of 30 electrode of chip 39, to play stronger equalizing current Effect.

It is also understood that, the substrate 32 of chip 30 itself can also form corresponding electric current obstacle to expand electric current Dissipate.As shown in figure 3, the lower surface of substrate 32 forms multiple grooves 320 as electric current obstacle by modes such as etchings.These grooves 320 size is identical, but distribution density from the position of counter electrode 39 towards gradually subtracting at the position on the periphery of counterpart substrate 32 It is small.This kind of arrangement mode of groove 320 can play a part of to hinder electric current, electric current is disperseed to both sides from the middle of chip 30, from And chip 30 is sent uniform light.Certainly, also can be by controlling etching condition (such as etching period, the concentration of etching solution Deng) make the size of groove 320 from the position of counter electrode 39 towards being gradually reduced at the position on the periphery of counterpart substrate 32, and Arranging density keep it is constant, or size and arranging density from the position of counter electrode 39 towards the periphery of counterpart substrate 32 Position at be gradually reduced.The substrate 20 for carrying chip 30 in such cases can be manufactured directly using conductive metal material, But insulation must be kept by 29 and first conductive layer of insulating barrier 26, occurred with the situation for preventing short circuit.

It is also understood that ground, the substrate 32 of the chip 30 itself of Fig. 3 can be combined with the substrate 20 of the carrying chip 30 of Fig. 1 to be made With so as to be collectively forming dual electric current obstacle 24 as shown in Figure 4, to play stronger current spreading effect.

Claims

1. a kind of luminescence chip combination, including first substrate and the chip being fixed on first substrate, the chip include the second base The first semiconductor layer, luminescent layer, the second semiconductor layer and electrode that plate is electrically connected and stacked gradually with second substrate, its feature It is：Second substrate includes at least one of multiple electric current obstacles, arrangement density and size of electric current obstacle from second substrate Reduce towards second substrate periphery at the position of upper counter electrode, electric current obstacle is the table for being formed at second substrate away from luminescent layer The groove in face, groove is located at the joint of second substrate and first substrate.

2. luminescence chip combination as claimed in claim 1, it is characterised in that：Second substrate directly connects with the first semiconductor layer Connect.

3. luminescence chip combination as claimed in claim 2, it is characterised in that：Second substrate is made of an electrically conducting material.

4. luminescence chip combination as claimed in claim 1, it is characterised in that：First substrate is led by second substrate with the first half Body layer connection.

5. luminescence chip combination as claimed in claim 4, it is characterised in that：First substrate is made up of insulating materials, the first base Intralamellar part forms multiple conducting portions, and electric current obstacle is formed between adjacent conducting portion.

6. luminescence chip combination as claimed in claim 5, it is characterised in that：First substrate include first surface and with the first table The relative second surface in face, conducting portion extends to second surface from first surface through first substrate.

7. luminescence chip combination as claimed in claim 6, it is characterised in that：Second substrate is engaged in first substrate first surface It is connected at the position of upper correspondence conducting portion and with conducting portion.

8. luminescence chip combination as claimed in claim 7, it is characterised in that：It is additionally included on first substrate first surface and is formed The first conductive layer and the second conductive layer for being formed on first substrate second surface, the first conductive layer separates with second substrate, Second conductive layer connects conducting portion.

9. luminescence chip combination as claimed in claim 8, it is characterised in that：Electrode is connected by wire with the first conductive layer.