CN103887418A - Luminous chip combination - Google Patents

Luminous chip combination Download PDF

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Publication number
CN103887418A
CN103887418A CN201210561892.3A CN201210561892A CN103887418A CN 103887418 A CN103887418 A CN 103887418A CN 201210561892 A CN201210561892 A CN 201210561892A CN 103887418 A CN103887418 A CN 103887418A
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CN
China
Prior art keywords
substrate
luminescence chip
semiconductor layer
chip combination
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201210561892.3A
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Chinese (zh)
Other versions
CN103887418B (en
Inventor
赖志成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Scienbizip Consulting Shenzhen Co Ltd
Original Assignee
Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hongfujin Precision Industry Shenzhen Co Ltd, Hon Hai Precision Industry Co Ltd filed Critical Hongfujin Precision Industry Shenzhen Co Ltd
Priority to CN201210561892.3A priority Critical patent/CN103887418B/en
Publication of CN103887418A publication Critical patent/CN103887418A/en
Application granted granted Critical
Publication of CN103887418B publication Critical patent/CN103887418B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting

Abstract

Disclosed is a luminous chip combination which includes a conductive substrate, and a a first semiconductor layer, a luminous layer, a second semiconductor layer and an electrode, which are electrically connected with the substrate and stacked sequentially. The substrate includes a plurality of current counterguards. At least one of the distribution density and size of the current counterguards is reduced from a position of the substrate, corresponding to the electrode, towards the peripheral position of the substrate. Because of block of the current counterguards, current introduced from the electrode can be distributed into the whole chip and thus the luminous layer is stimulated uniformly to emit light.

Description

Luminescence chip combination
Technical field
The present invention relates to a kind of chip portfolio, refer to especially a kind of luminescence chip combination.
Background technology
Light-emitting diode, as emerging light source, has been widely used in the middle of various uses.Light-emitting diode generally includes pedestal, be installed on the chip on pedestal and cover the packaging body of chip.Chip by substrate and the n type semiconductor layer, luminescent layer and the p type semiconductor layer that grow in successively on substrate form.Chip also can form respectively P electrode and N electrode on its n type semiconductor layer and p type semiconductor layer, to be electrically connected with pedestal.Current, having segment chip is directly to adopt electric conducting material to manufacture its substrate, and industry is referred to as vertical conducting cake core conventionally.The substrate of this kind of chip can directly use as the electrode of n type semiconductor layer, thereby this kind of chip only can form P electrode at the top of its p type semiconductor layer.When work, electric current enters in chip from P electrode, and exports pedestal to via substrate.
But the P electrode of this kind of vertical conducting cake core only covers the zone line at the top of p type semiconductor layer often, while causing electric current to transmit, also trend towards concentrating on the middle part of chip in chip, the electric current of chip two side areas is less.Thus, the few situation in many both sides in the middle of the distribution of electric current in chip occurs, the light that causes chip central region to be subject to light that electric current excites excited by electric current more than chip two side areas, makes the chip cannot be luminous equably.This kind of situation is more obvious in the middle of large-area chip, badly influences the normal use of chip.
Summary of the invention
Therefore, be necessary to provide a kind of luminescence chip combination with uniform light output.
A kind of luminescence chip combination, the first semiconductor layer, luminescent layer, the second semiconductor layer and the electrode that comprise electrically-conductive backing plate, be electrically connected and stack gradually with electrically-conductive backing plate, substrate comprises multiple electric current obstacles, and at least one position from counter electrode in density and the size of these electric current obstacles reduces towards the periphery of substrate.
Because density or the size of electric current obstacle reduce towards the periphery of substrate from the position of counter electrode, therefore the meeting under the stopping of electric current obstacle of the electric current in electrode enters chip is spread to chip periphery, thereby is evenly distributed in chip.The electric current being evenly distributed and then stimulated luminescence layer send uniform light, make chip obtain the desirable light effect that goes out.
With reference to the accompanying drawings, the invention will be further described in conjunction with specific embodiments.
Brief description of the drawings
Fig. 1 illustrates the luminescence chip combination of first embodiment of the invention.
Fig. 2 illustrates the luminescence chip combination of second embodiment of the invention.
Fig. 3 illustrates the luminescence chip combination of third embodiment of the invention.
Fig. 4 illustrates the luminescence chip combination of fourth embodiment of the invention.
Main element symbol description
Luminescence chip combination 10
Substrate 20
Conducting portion 22
Electric current obstacle 24
The first conductive layer 26
The second conductive layer 28
Insulating barrier 29
Chip 30
Substrate 32
Groove 320
The first semiconductor layer 34
Luminescent layer 36
The second semiconductor layer 38
Electrode 39
Wire 40
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Refer to Fig. 1, show the luminescence chip combination 10 of first embodiment of the invention.Luminescence chip combination 10 comprises a substrate 20 and is fixed on the chip 30 on substrate 20.
Chip 30 comprises substrate 32, is formed at the first semiconductor layer 34, luminescent layer 36, the second semiconductor layer 38 and the electrode 39 on substrate 32 successively.In the present embodiment, substrate 32 is to be made up of the material that conducting electricity, such as silicon, carborundum or metal material.In the time that substrate 32 adopts silicon or carborundum to manufacture, the first semiconductor layer 34, luminescent layer 36 and the second semiconductor layer 38 can be directly grown on substrate 32.Now the first semiconductor layer 34 is n type semiconductor layer, and the second semiconductor layer 38 is p type semiconductor layer.In the time that substrate 32 adopts metal material to manufacture, the second semiconductor layer 38, luminescent layer 36 and the first semiconductor layer 34 are to be first grown in successively in a temporary substrate (not shown), and then form metal substrate 32 on the first semiconductor layer 34, finally temporary substrate is removed.Now the first semiconductor layer 34 is p type semiconductor layer, and the second semiconductor layer 38 is n type semiconductor layer.The first semiconductor layer 34, luminescent layer 36 and the second semiconductor layer 38 all can adopt luminescent materials such as gallium nitride, InGaN and aluminum indium nitride gallium and make.The area of electrode 39 is less than the area of the second semiconductor layer 38.Electrode 39 only cover the central region of the second semiconductor layer 38 end faces and the relative exposed at both sides that makes the second semiconductor layer 38 end faces outside.
The mode that chip 30 engages by viscose glue or eutectic is fixed on substrate 20 end faces.Substrate 20 is made up of the insulating material such as such as epoxy resin, silica gel or pottery, and its inside is formed with multiple conducting portions 22.Each conducting portion 22 is made by metal material.In the time that substrate 20 is manufactured by epoxy resin or silica gel, these conducting portions 22 can be located by orientation tool in advance, and then substrate 20 is formed on conducting portion 22 by injecting the modes such as moulding.In the time that substrate 20 is manufactured by pottery, these conducting portions 22 can be with ceramic sheet by together moulding of LTCC Technology.These conducting portions 22 be all positioned at chip 30 under, and each conducting portion 22 all extends to substrate 20 bottom surfaces from substrate 20 end faces.In the present embodiment, the size of each conducting portion 22 is all identical, and the distribution density of conducting portion 22 reduces towards substrate 20 peripheral positions gradually from corresponding chip 30 electrode 39 positions.Between every two adjacent conducting portions 22, form an electric current obstacle 24.Because the measure-alike and arranging density of conducting portion 22 reduces to both sides gradually from centre, thereby the arranging density of the electric current obstacle 24 being defined by conducting portion 22 remains unchanged, but size is from middle (being corresponding chip 30 electrode 39 positions), to both sides, (being counterpart substrate 20 peripheral positions) reduces gradually.
Substrate 20 forms respectively the first conductive layer 26 and the second conductive layer 28 at its end face and bottom surface.The first conductive layer 26 separates with chip 30, and is connected with the electrode 39 at chip 30 tops by a wire 40.The second conductive layer 28 connects the bottom surface of all conducting portions 22.Thus, the electrode 39 of chip 30 is electrically connected with the first conductive layer 26, and the substrate 32 of chip 30 is electrically connected with the second conductive layer 28.Electric current can be inputted into chip 30 interior (taking the first semiconductor layer 34 as n type semiconductor layer is as example) from electrode 39 via the first conductive layer 26, and then exports from the second conductive layer 28 by conducting portion 22.In transmitting procedure, because the size of electric current obstacle 24 reduces gradually from centre to both sides, thereby the electric current that enters chip 30 from electrode 39 will be subject to the obstruction of electric current obstacle 24 and disperse to both sides from chip 30 middle parts, thereby flows through equably chip 30.Therefore, under equally distributed electric current excites, chip 30 can send uniform light, thereby obtains the desirable light effect that goes out.
Understandably, as shown in Figure 2, it is identical that the size of the electric current obstacle 24 of aforesaid substrate 20 also can keep, but the density of arranging is from middle (being corresponding chip 30 electrode 39 positions), to both sides, (being counterpart substrate 20 peripheral positions) reduces gradually, can play equally the effect of equalizing current.Certainly, the size of electric current obstacle 24 and the density of arranging also can change simultaneously, all reduce gradually towards chip the first semiconductor layer 34 peripheries from corresponding chip 30 electrode 39 positions, to play the effect of stronger equalizing current.
It is also understood that ground, the substrate 32 of chip 30 self also can form corresponding electric current obstacle electric current is spread.As shown in Figure 3, substrate 32 lower surfaces form multiple grooves 320 as electric current obstacle by modes such as etchings.These grooves 320 measure-alike, but distribution density reduces towards the position of counterpart substrate 32 peripheries gradually from the position of counter electrode 39.This kind of arrangement mode of groove 320 can play the effect that hinders electric current, electric current disperseed to both sides in the middle of chip 30, thereby make chip 30 send uniform light.Certainly, also can the size of groove 320 be reduced gradually towards the position of counterpart substrate 32 peripheries from the position of counter electrode 39 by controlling etching condition (as concentration of etching period, etching solution etc.), and arranging density remains unchanged, or size and arranging density all reduce towards the position of counterpart substrate 32 peripheries gradually from the position of counter electrode 39.The substrate 20 of carries chips 30 just can directly adopt the metal material manufacture of conduction in such cases, but must keep insulation by insulating barrier 29 and the first conductive layer 26, occurs with the situation that prevents short circuit.
It is also understood that ground, the substrate 32 of the chip 30 of Fig. 3 self can be combined with the substrate of the carries chips of Fig. 1 30 20, thus the common dual electric current obstacle 24 forming as shown in Figure 4, to play stronger current spread effect.

Claims (10)

1. a luminescence chip combination, the first semiconductor layer, luminescent layer, the second semiconductor layer and the electrode that comprise electrically-conductive backing plate, be electrically connected and stack gradually with substrate, it is characterized in that: substrate comprises multiple electric current obstacles, electric current obstacle arrange in density and size at least one from substrate, reduce towards substrate periphery the position of counter electrode.
2. luminescence chip combination as claimed in claim 1, is characterized in that: substrate is directly connected with the first semiconductor layer.
3. luminescence chip combination as claimed in claim 2, is characterized in that: substrate is made up of electric conducting material, and electric current obstacle is to be formed at the surperficial groove of substrate away from luminescent layer.
4. luminescence chip combination as claimed in claim 3, is characterized in that: also comprise another substrate of bearing substrate, groove is positioned at the joint of substrate and another substrate.
5. luminescence chip combination as claimed in claim 1, is characterized in that: substrate is connected with the first semiconductor layer by another substrate.
6. luminescence chip combination as claimed in claim 5, is characterized in that: substrate is made up of insulating material, and the multiple conducting portions of the inner formation of substrate, form electric current obstacle between adjacent conducting portion.
7. luminescence chip combination as claimed in claim 6, is characterized in that: substrate comprises first surface and the second surface relative with first surface, and conducting portion runs through substrate from first surface and extends to second surface.
8. luminescence chip combination as claimed in claim 7, is characterized in that: another substrate is engaged in the position of corresponding conducting portion on substrate first surface and is connected with conducting portion.
9. luminescence chip combination as claimed in claim 8, it is characterized in that: be also included in the first conductive layer forming on substrate first surface and the second conductive layer forming on substrate second surface, the first conductive layer and another substrate separate, and the second conductive layer connects conducting portion.
10. luminescence chip combination as claimed in claim 9, is characterized in that: electrode is connected with the first conductive layer by wire.
CN201210561892.3A 2012-12-22 2012-12-22 Luminescence chip is combined Expired - Fee Related CN103887418B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210561892.3A CN103887418B (en) 2012-12-22 2012-12-22 Luminescence chip is combined

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210561892.3A CN103887418B (en) 2012-12-22 2012-12-22 Luminescence chip is combined

Publications (2)

Publication Number Publication Date
CN103887418A true CN103887418A (en) 2014-06-25
CN103887418B CN103887418B (en) 2017-06-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106159073A (en) * 2015-04-23 2016-11-23 晶元光电股份有限公司 Light-emitting component and manufacture method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008066554A (en) * 2006-09-08 2008-03-21 Sanken Electric Co Ltd Semiconductor light emitting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106159073A (en) * 2015-04-23 2016-11-23 晶元光电股份有限公司 Light-emitting component and manufacture method thereof

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Effective date of registration: 20170526

Address after: Guangdong province Shenzhen city Longhua District Dragon Road No. 83 wing group building 11 floor

Applicant after: SCIENBIZIP CONSULTING (SHEN ZHEN) CO., LTD.

Address before: 518109 Guangdong city of Shenzhen province Baoan District Longhua Town Industrial Zone tabulaeformis tenth East Ring Road No. 2 two

Applicant before: Hongfujin Precise Industry (Shenzhen) Co., Ltd.

Applicant before: Hon Hai Precision Industry Co., Ltd.

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CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20170630

Termination date: 20171222