CN103887338B - A kind of knot terminal and preparation method thereof suitable for deep trouth superjunction devices - Google Patents
A kind of knot terminal and preparation method thereof suitable for deep trouth superjunction devices Download PDFInfo
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- CN103887338B CN103887338B CN201210563935.1A CN201210563935A CN103887338B CN 103887338 B CN103887338 B CN 103887338B CN 201210563935 A CN201210563935 A CN 201210563935A CN 103887338 B CN103887338 B CN 103887338B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 24
- 239000011810 insulating material Substances 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 33
- 239000010410 layer Substances 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000000407 epitaxy Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000007772 electrode material Substances 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000002356 single layer Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 239000000243 solution Substances 0.000 description 8
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910001316 Ag alloy Inorganic materials 0.000 description 2
- KMWBBMXGHHLDKL-UHFFFAOYSA-N [AlH3].[Si] Chemical compound [AlH3].[Si] KMWBBMXGHHLDKL-UHFFFAOYSA-N 0.000 description 2
- -1 aluminium silicon Copper Chemical compound 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The knot terminal and preparation method thereof that present invention discloses a kind of suitable for deep trouth superjunction devices, the knot terminal include semiconductor base, first electrode, semiconductor regions, second electrode.First electrode is formed in the lower end surface of semiconductor base；Semiconductor regions are formed in the upper surface of semiconductor base, have the first conduction type, semiconductor regions include active region, first terminal region, second terminal region.Active region is equipped with multiple first grooves, and filling has the semiconductor material of the second conduction type in first groove；First terminal region is equipped with multiple third grooves, and filling has the semiconductor material of the second conduction type in third groove；Second terminal region is equipped at least one second groove, is the insulating materials with high dielectric constant in second groove.Second electrode connects the first groove of active region, is covered on active region, first terminal region, on second terminal region.Knot terminal of the present invention can improve knot terminal device high pressure resistant property.
Description
Technical field
The invention belongs to semiconductor power device technology fields, are related to a kind of knot terminal more particularly to one of superjunction devices
Kind is suitable for the knot terminal of deep trouth superjunction devices；Meanwhile the invention further relates to a kind of knot terminals suitable for deep trouth superjunction devices
Preparation method.
Background technique
Requirement of the modern power electronics technology to power device performance substantially has following several: 1) high pressure resistant, 2) when conducting
Current density is big；3) pressure drop is low on device when being connected, 4) switching speed is high, 5) driving power is small, and above-mentioned the 3rd point and the 4th point
Especially it is worth noting.The VDMOS occurred in 1980, since its is high pressure resistant, switching speed is fast, and driving power is small, is in use to always
Nowadays.But traditional VDMOS conducting resistance is by " the silicon limit " relationship Ron=0.83 × 10-8×VB2.5(Ω.cm2) pact
Beam, value increase sharply with pressure resistance raising, and this mechanism limits the development of high pressure VDMOS.
University of Electronic Science and Technology (UESTC) Chen Xingbi academician proposes in the alternately arranged PN of vertical MOS Guan Zhongyong within 1993
The new construction that structure substitutes conventional Drift layer is theoretical, i.e., obtains the superjunction (Super- generally accepted in the world in the future
Junction) pressure-resistance structure, the theory have broken traditional silicon limit restraint, have while obtaining high-breakdown-voltage lower
Conducting resistance Ron, be known as be power semiconductor field revolution.
Superjunction devices is developed so far, and knot terminal is broadly divided into extended and Truncated two major classes.The former be P column with
The structure that N column alternates, the latter are the structure of filling high dielectric constant material in groove.Individually mutually handed over using P column with N column
The structure replaced, technological difficulty is low, and yield is high, but this knot terminal wastes area very much.Individually using filling in groove
The structure of high dielectric constant material, although can significantly reduce the area of knot terminal, the width of its groove is with device
The raising of resistance to pressure request and increase, as groove width increases, etching and the filling time also greatly increase, reduce production effect
Rate；Simultaneously because groove structure bears the overwhelming majority pressure resistance of device, the requirement to trench fill quality is high, i.e., to filling
The control of the defects of gap, impurity requires extremely harshness, technological difficulty significantly to increase.
The terminal of most superjunction devices uses the structure that P column and N column alternate, institute as above currently on the market
It states, the shortcomings that this junction termination structures is that termination environment wastes very big area, to increase manufacturing cost.
Summary of the invention
The technical problems to be solved by the present invention are: providing a kind of knot terminal suitable for deep trouth superjunction devices, can improve
Knot terminal device high pressure resistant property.
In addition, knot obtained is eventually the present invention also provides a kind of preparation method of knot terminal suitable for deep trouth superjunction devices
End can improve knot terminal device high pressure resistant property.
In order to solve the above technical problems, the present invention adopts the following technical scheme:
A kind of knot terminal suitable for deep trouth superjunction devices, the knot terminal include:
Semiconductor base；
First electrode is formed in the lower end surface of the semiconductor base；
Semiconductor regions are formed in the upper surface of the semiconductor base, have the first conduction type, the semiconductor
Region includes:
Active region is equipped with multiple first grooves, and filling has the semiconductor material of the second conduction type in first groove
Material；
First terminal region is equipped with multiple third grooves, and filling has the semiconductor of the second conduction type in third groove
Material；
Second terminal region is equipped at least one second groove, is the insulation material with high dielectric constant in second groove
Material；
Second electrode connects the first groove of active region, is covered on the active region, first terminal region, the
On two terminal areas.
As a preferred solution of the present invention, the active region, first terminal region are that P column and N column are mutually handed over
The structure replaced；First terminal region is electric field elongated area, and second terminal region is electric field cut-off region.
As a preferred solution of the present invention, between the groove width and groove of the first groove that the active region is equipped with
Away from equal or different；The groove width and trench spacing for the third groove that the first terminal region is equipped with are equal or different；
Spacing between the second groove and the spacing and each first groove/third groove of immediate third groove
It is equal or unequal；
The depth of the second groove and the deep equality of first groove/third groove, or be greater than each first groove/
The depth of third groove.
As a preferred solution of the present invention, the quantity of third groove is advised by device pressure resistance in the first terminal region
The doping concentration of lattice and the semiconductor regions with the first conduction type determines.
As a preferred solution of the present invention, the first groove and the structure of third groove are identical, second ditch
The width of slot is greater than the width of first groove and third groove.
As a preferred solution of the present invention, the filler in the second groove in the second terminal region is that single is high
Dielectric constant material, or be a variety of high dielectric constant materials.
As a preferred solution of the present invention, the end of the second electrode is on first terminal region, Huo Zhe
On second terminal region.
A kind of preparation method of above-mentioned knot terminal, the preparation method include the following steps:
Step S1: semiconductor regions are grown on the semiconductor base of dense doping；Is then etched on semiconductor regions
The depth and width size of the second groove of two terminal areas, second groove is determined by device pressure resistance and substrate doping；So
The filling for completing second terminal region trenches by the method for deposit silica afterwards, is then gone by chemically-mechanicapolish polishing CMP
Except excess silicon dioxide；
Step S2: carrying out the etching of the first groove of active region and the third groove in first terminal region, grows deep trouth
Etching barrier layer or chemically mechanical polishing CMP grind barrier layer；Then first groove/third groove etch areas is defined, into
Row deep etching removes partly or entirely hard exposure mask after etching；Then it carries out epitaxial growth and fills groove；It is carried out after extension filling
Cmp planarization is chemically-mechanicapolish polished, hard exposure mask is completely removed after planarization；
Step S3: continue the front MOS technique, field oxide growth, etching, gate oxide growth, polysilicon gate deposit, etching, P
Trap injection is annealed, dielectric deposition under aluminium, hole etching, is then deposited second electrode material and is patterned etching；Last double
Conductor substrate carries out back thinning and is formed first electrode, and this completes the production of deep trouth superjunction MOS a kind of.
As a preferred solution of the present invention, it in the step S1, is grown outside N-type on the semiconductor base of dense doping
Prolong layer, N-type epitaxy layer is as the semiconductor regions.
As a preferred solution of the present invention, in the step S2, the barrier layer is single-layer or multi-layer, barrier layer packet
The first oxide skin(coating) and the second oxide skin(coating) are included, or including oxide skin(coating) and nitride layer.
The beneficial effects of the present invention are: the knot terminal and its preparation side proposed by the present invention suitable for deep trouth superjunction devices
Method, since terminal area extends the reasonable disposition with electric field cut-off structure using electric field, breakdown characteristics are significantly improved.And this
The terminal structure production of invention is simple, high-efficient with device common process good compatibility.
The structure that the present invention is combined using P column, N column with trench fill, the knot relatively individually alternateed using P column, N column
Structure, area greatly reduce；Simultaneously as groove structure only assumes responsibility for a part of pressure resistance of the total pressure resistance of device, reduced width, etching
Reduce therewith with the filling time, and since the pressure resistance undertaken becomes smaller, the capacity of trench fill quality is also increased, is more advantageous to good
The raising of rate.
Even if terminal structure of the invention has substantially reduced the width of groove, production efficiency is greatly improved,
But in order to further increase, the present invention also illustrates a kind of manufacturing method of terminal suitable for deep trouth superjunction devices.With more
The groove of a narrower width replaces original single wide deep trouth, and groove opening size and its spacing select to close according to oxidation technology
The design value of reason, then by the silicon between the method complete oxidation groove of high growth temperature silica, while the oxidation grown
Layer fills up groove, finally terminal area is made to become oxide layer completely.
Detailed description of the invention
Fig. 1 is the schematic cross-section of junction termination structures of the invention.
Fig. 2 is that the schematic cross-section after deep trouth is dug in the second terminal region of first embodiment of the invention.
Fig. 3 is the second terminal area filling SiO of first embodiment of the invention and second embodiment2Section signal afterwards
Figure.
Fig. 4 is that the schematic cross-section after deep trouth is dug in the terminal area two of second embodiment of the invention.
Specific embodiment
The preferred embodiment that the invention will now be described in detail with reference to the accompanying drawings.
Embodiment one
Referring to Fig. 1, present invention discloses a kind of knot terminal suitable for deep trouth superjunction devices, the knot terminal includes:
Semiconductor base 1, first electrode 11, semiconductor regions 2, second electrode.
Semiconductor base 1 is the semiconductor material with the first doping type, the doping of about 0.002-0.008ohm.cm
Resistivity, typically As or Sb doped N-type silicon base.
First electrode 11 is formed in the lower end surface (back side) of the semiconductor base 1；Semiconductor regions 2 are formed in described half
The upper surface of conductor substrate 1, has the first conduction type (i.e. the first doping type), and the typical material of semiconductor regions 2 is
Resistivity is 1-10ohm.cm Ph doped N-type silicon epitaxial material.
The semiconductor regions include: active region 100, first terminal region 200, second terminal region 300.Wherein,
Active region 100 is equipped with multiple first grooves 3, and filling has the second conduction type (i.e. the second doping type) in first groove 3
Semiconductor material, the growing epitaxial silicon etc. of specific material such as Boron doping.First terminal region 200 is equipped with multiple first ditches
Slot 3 (in the present embodiment, the groove of first terminal region setting is identical as the groove structure that active region is arranged, wherein fill
Semiconductor material is also identical, therefore is referred to as first groove here), the interior filling of first groove 3 has the half of the second conduction type
Conductor material, as shown in Figure 1, the arrangement mode of first groove 3 is similar with active region.Second terminal region 300 is equipped at least
One second groove 4, interior second groove 4 is the insulating materials with high dielectric constant.The second of the second terminal region 300
Filler in groove is single high dielectric constant material, or is a variety of high dielectric constant materials；Specific material such as SiO2 or
Person's polyimides etc..It avoids etching and filling very wide deep trouth, the then method that multiple 4th grooves 6 aoxidize that etches also can be used
(as shown in Figure 4) finally makes SiO2 fill up the region.
The groove width for the first groove 3 that the active region 100 is equipped with can be equal or different with trench spacing；It is described
The groove width and trench spacing for the first groove 3 that first terminal region 200 is equipped with are equal or different；The second groove 4 with
Spacing between the spacing of immediate first groove and each first groove can be equal or unequal；The second groove
Depth and first groove deep equality, or the depth greater than each first groove.Preferably, the width of the second groove
Degree is greater than the width of first groove.
The first groove of second electrode connection active region is covered on the active region, first terminal region, the
On two terminal areas.The end of the second electrode is on first terminal region, or on second terminal region.
In the present embodiment, the active region, first terminal region are the structure that P column and N column alternate；First eventually
End regions are electric field elongated area, and second terminal region is electric field cut-off region.
In the first terminal region quantity of third groove by device pressure resistance specification and with the first conduction type half
The doping concentration of conductive region determines.
The structure of knot terminal of the present invention is described above also to disclose in one kind while the present invention discloses junction termination structures
The preparation method of knot terminal is stated, the preparation method includes the following steps:
[step S1] in the silicon base (semiconductor base 1) of dense doping as shown in Figure 1, grow N-type epitaxy layer (semiconductor
Region 2), mix Ph such as with a thickness of the low-doped epitaxial layer of 48um.The second ditch of terminal area two is then etched in N-type epitaxy layer
Depending on slot 4 (such as Fig. 2), trench depth and width dimensions are by device pressure resistance and substrate doping.Then pass through deposit dioxy
The method of SiClx completes two trench fill of terminal area, then removes excess silicon dioxide (such as Fig. 3) by CMP.
The first groove 3 that [step S2] carries out active region and terminal area one etches, grow deep etching barrier layer or
CMP grinds barrier layer, such as oxide, nitride or nitrogen oxides.The barrier layer can be with single layer, can also be with multilayer, such as first
The+the second oxide of oxide or oxide+nitride etc..Then the etch areas of first groove 3 is defined, deep etching is carried out,
Photoresist (if there is) and part or all of hard exposure mask are removed after etching.Then it carries out epitaxial growth and fills groove.Extension filling
Cmp planarization is carried out afterwards, and hard exposure mask is completely removed after planarization.
[step S3] continues the traditional front MOS technique, field oxide growth, etching, gate oxide growth, polysilicon gate shallow lake
Product, etching, p-well injection are annealed, and medium 5 deposits under aluminium, and hole etching then deposits second electrode material 12 (such as aluminium silicon or aluminium silicon
Copper) and it is patterned etching.Finally semiconductor base 1 is carried out back thinning and is formed first electrode 11 (such as silver alloy),
This completes the production of deep trouth superjunction MOS a kind of.
Embodiment two
The difference between this embodiment and the first embodiment lies in the preparation method of knot terminal of the present invention includes such as in the present embodiment
Lower step:
[step S1] as shown in connection with fig. 1, grows N-type epitaxy layer in the silicon base (semiconductor base 1) of dense doping and (partly leads
Body region 2), such as mix the low-doped epitaxial layer with a thickness of 48um of Ph.Terminal area two is then etched in N-type epitaxy layer
Depending on 4th groove 6 (such as Fig. 4), trench depth and width dimensions are by device pressure resistance and substrate doping, and groove is opened
Mouth size and its spacing are then complete by the method for high growth temperature silica according to the reasonable design value of oxidation technology selection
The silicon in terminal area two between the 4th groove 6 is aoxidized, while the oxide layer grown fills up groove, finally makes terminal area complete
Become oxide layer (such as Fig. 3) entirely；
The first groove 3 that [step S2] carries out active region and terminal area one etches, grow deep etching barrier layer or
CMP grinds barrier layer, such as oxide, nitride or nitrogen oxides.The barrier layer can be with single layer, can also be with multilayer, such as first
The+the second oxide of oxide or oxide+nitride etc..Then the etch areas of first groove 3 is defined, deep etching is carried out,
Photoresist (if there is) and part or all of hard exposure mask are removed after etching.Then it carries out epitaxial growth and fills groove.Extension filling
Cmp planarization is carried out afterwards, and hard exposure mask is completely removed after planarization.
[step S3] continues the traditional front MOS technique, field oxide growth, etching, gate oxide growth, polysilicon gate shallow lake
Product, etching, p-well injection are annealed, and medium 5 deposits under aluminium, and hole etching then deposits second electrode material 12 (such as aluminium silicon or aluminium silicon
Copper) and it is patterned etching.Finally semiconductor base 1 is carried out back thinning and is formed first electrode 11 (such as silver alloy),
This completes the production of deep trouth superjunction MOS a kind of.
In conclusion the knot terminal and preparation method thereof proposed by the present invention suitable for deep trouth superjunction devices, due to terminal
Region is extended using electric field and the reasonable disposition of electric field cut-off structure, breakdown characteristics significantly improve.And terminal of the invention
Structure fabrication is simple, high-efficient with device common process good compatibility.
Description and application of the invention herein are illustrative, is not wishing to limit the scope of the invention to above-described embodiment
In.The deformation and change of embodiments disclosed herein are possible, the realities for those skilled in the art
The replacement and equivalent various parts for applying example are well known.It should be appreciated by the person skilled in the art that not departing from the present invention
Spirit or essential characteristics in the case where, the present invention can in other forms, structure, arrangement, ratio, and with other components,
Material and component are realized.Without departing from the scope and spirit of the present invention, can to embodiments disclosed herein into
The other deformations of row and change.
Claims (3)
1. a kind of preparation method of knot terminal, it is characterised in that:
The knot terminal is suitable for the knot terminal of deep trouth superjunction devices, and the knot terminal includes:
Semiconductor base；
First electrode is formed in the lower end surface of the semiconductor base；
Semiconductor regions are formed in the upper surface of the semiconductor base, have the first conduction type, the semiconductor regions
Include:
Active region is equipped with multiple first grooves, and filling has the semiconductor material of the second conduction type in first groove；
First terminal region is equipped with multiple third grooves, and filling has the semiconductor material of the second conduction type in third groove
Material；
Second terminal region is equipped at least one second groove, is the insulating materials with high dielectric constant in second groove；
The active region, first terminal region, second terminal region are arranged successively；
Second electrode connects the first groove of active region, is covered on the active region, first terminal region, second eventually
On end regions；
The preparation method includes the following steps:
Step S1: semiconductor regions are grown on the semiconductor base of dense doping；Then etching second is whole on semiconductor regions
The depth and width size of the second groove of end regions, second groove is determined by device pressure resistance and substrate doping；Then lead to
The method for crossing deposit silica completes the filling of second terminal region trenches, is then removed by chemically mechanical polishing CMP more
Remaining silica；
Step S2: carrying out the etching of the first groove of active region and the third groove in first terminal region, grows deep etching
Barrier layer or chemically mechanical polishing CMP grind barrier layer；Then first groove/third groove etch areas is defined, is carried out deep
It is groove etched, partly or entirely hard exposure mask is removed after etching；Then it carries out epitaxial growth and fills groove；Chemistry is carried out after extension filling
Cmp planarization is mechanically polished, hard exposure mask is completely removed after planarization；
Step S3: continue the front MOS technique, field oxide growth, etching, gate oxide growth, polysilicon gate deposit, etching, p-well note
Enter, anneal, dielectric deposition under aluminium, hole etching then deposits second electrode material and is patterned etching；Finally to semiconductor
Substrate carries out back thinning and is formed first electrode, and this completes the production of deep trouth superjunction MOS a kind of.
2. preparation method according to claim 1, it is characterised in that:
In the step S1, N-type epitaxy layer is grown on the semiconductor base of dense doping, N-type epitaxy layer is as the semiconductor
Region.
3. preparation method according to claim 1, it is characterised in that:
In the step S2, the barrier layer is single-layer or multi-layer, and barrier layer includes the first oxide skin(coating) and the second oxide skin(coating),
Or including oxide skin(coating) and nitride layer.
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| DE102015106693A1 (en) * | 2015-04-29 | 2016-11-03 | Infineon Technologies Austria Ag | A superjunction semiconductor device with junction termination extension structure and method of fabrication |
| CN105336765B (en) * | 2015-10-20 | 2018-12-25 | 西南交通大学 | A kind of power semiconductor |
| CN107359118B (en) * | 2017-07-31 | 2019-11-29 | 电子科技大学 | A kind of production method of super junction power device Withstand voltage layer |
| CN109360823B (en) * | 2018-10-08 | 2020-08-28 | 南京溧水高新创业投资管理有限公司 | Groove type transient voltage suppressor and manufacturing method thereof |
| CN111341832B (en) * | 2018-12-19 | 2023-10-27 | 无锡华润华晶微电子有限公司 | Junction terminal structure and preparation method thereof |
| CN117410347A (en) * | 2023-12-15 | 2024-01-16 | 无锡美偌科微电子有限公司 | Super junction power device with low terminal area and preparation method |
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