CN103875068B - 穿晶片通路设备以及其制造方法 - Google Patents

穿晶片通路设备以及其制造方法 Download PDF

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Publication number
CN103875068B
CN103875068B CN201280050826.8A CN201280050826A CN103875068B CN 103875068 B CN103875068 B CN 103875068B CN 201280050826 A CN201280050826 A CN 201280050826A CN 103875068 B CN103875068 B CN 103875068B
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CN
China
Prior art keywords
wafer
groove
wafer surface
conductive layer
equipment
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CN201280050826.8A
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English (en)
Chinese (zh)
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CN103875068A (zh
Inventor
R·德克尔
B·马赛利斯
M·米尔德
R·毛奇斯措克
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/0292—Electrostatic transducers, e.g. electret-type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4451—Semiconductor materials, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Micromachines (AREA)
  • Transducers For Ultrasonic Waves (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Combinations Of Printed Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
CN201280050826.8A 2011-10-17 2012-10-12 穿晶片通路设备以及其制造方法 Active CN103875068B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201161547942P 2011-10-17 2011-10-17
US61/547,942 2011-10-17
PCT/IB2012/055547 WO2013057642A1 (en) 2011-10-17 2012-10-12 Through-wafer via device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
CN103875068A CN103875068A (zh) 2014-06-18
CN103875068B true CN103875068B (zh) 2018-07-10

Family

ID=47428773

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280050826.8A Active CN103875068B (zh) 2011-10-17 2012-10-12 穿晶片通路设备以及其制造方法

Country Status (6)

Country Link
US (1) US9230908B2 (https=)
EP (1) EP2745315A1 (https=)
CN (1) CN103875068B (https=)
IN (1) IN2014CN02550A (https=)
RU (1) RU2603435C2 (https=)
WO (1) WO2013057642A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IN2014CN04975A (https=) 2011-12-20 2015-09-18 Koninkl Philips Nv
US10586753B2 (en) 2014-03-31 2020-03-10 Koninklijke Philips N.V. IC die, ultrasound probe, ultrasonic diagnostic system and method
JP6304445B2 (ja) * 2015-03-16 2018-04-04 富士電機株式会社 半導体装置の製造方法
US11097942B2 (en) * 2016-10-26 2021-08-24 Analog Devices, Inc. Through silicon via (TSV) formation in integrated circuits
TW201947717A (zh) * 2018-05-03 2019-12-16 美商蝴蝶網路公司 用於超音波晶片的垂直封裝及相關方法

Citations (3)

* Cited by examiner, † Cited by third party
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US6430109B1 (en) * 1999-09-30 2002-08-06 The Board Of Trustees Of The Leland Stanford Junior University Array of capacitive micromachined ultrasonic transducer elements with through wafer via connections
WO2005088699A1 (en) * 2004-03-10 2005-09-22 Koninklijke Philips Electronics N.V. Method of manufacturing an electronic device and a resulting device
US20100264548A1 (en) * 2009-04-16 2010-10-21 Freescale Semiconductor, Inc. Through substrate vias

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US5381385A (en) 1993-08-04 1995-01-10 Hewlett-Packard Company Electrical interconnect for multilayer transducer elements of a two-dimensional transducer array
US5619476A (en) * 1994-10-21 1997-04-08 The Board Of Trustees Of The Leland Stanford Jr. Univ. Electrostatic ultrasonic transducer
US6716737B2 (en) * 2002-07-29 2004-04-06 Hewlett-Packard Development Company, L.P. Method of forming a through-substrate interconnect
US20040104454A1 (en) 2002-10-10 2004-06-03 Rohm Co., Ltd. Semiconductor device and method of producing the same
US6836020B2 (en) 2003-01-22 2004-12-28 The Board Of Trustees Of The Leland Stanford Junior University Electrical through wafer interconnects
US7257051B2 (en) * 2003-03-06 2007-08-14 General Electric Company Integrated interface electronics for reconfigurable sensor array
JP2005032769A (ja) * 2003-07-07 2005-02-03 Seiko Epson Corp 多層配線の形成方法、配線基板の製造方法、デバイスの製造方法
WO2005120355A1 (ja) 2004-06-07 2005-12-22 Olympus Corporation 静電容量型超音波トランスデューサ
EP1883956A4 (en) 2005-05-18 2011-03-23 Kolo Technologies Inc BY-THE-WAFER CONNECTION
US7622848B2 (en) 2006-01-06 2009-11-24 General Electric Company Transducer assembly with z-axis interconnect
WO2008001282A2 (en) 2006-06-26 2008-01-03 Koninklijke Philips Electronics, N.V. Flip-chip interconnection with a small passivation layer opening
JP5175853B2 (ja) 2006-09-25 2013-04-03 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ フリップチップ相互接続貫通チップビア
KR20130014618A (ko) * 2006-11-03 2013-02-07 리써치 트라이앵글 인스티튜트 굴곡 모드 압전 트랜스듀서를 사용하는 보강된 초음파 촬영 프로브
US8110899B2 (en) * 2006-12-20 2012-02-07 Intel Corporation Method for incorporating existing silicon die into 3D integrated stack
US7843022B2 (en) 2007-10-18 2010-11-30 The Board Of Trustees Of The Leland Stanford Junior University High-temperature electrostatic transducers and fabrication method
US7781238B2 (en) 2007-12-06 2010-08-24 Robert Gideon Wodnicki Methods of making and using integrated and testable sensor array

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US6430109B1 (en) * 1999-09-30 2002-08-06 The Board Of Trustees Of The Leland Stanford Junior University Array of capacitive micromachined ultrasonic transducer elements with through wafer via connections
WO2005088699A1 (en) * 2004-03-10 2005-09-22 Koninklijke Philips Electronics N.V. Method of manufacturing an electronic device and a resulting device
US20100264548A1 (en) * 2009-04-16 2010-10-21 Freescale Semiconductor, Inc. Through substrate vias

Also Published As

Publication number Publication date
WO2013057642A1 (en) 2013-04-25
US9230908B2 (en) 2016-01-05
EP2745315A1 (en) 2014-06-25
CN103875068A (zh) 2014-06-18
IN2014CN02550A (https=) 2015-08-07
RU2603435C2 (ru) 2016-11-27
US20140293751A1 (en) 2014-10-02
RU2014119923A (ru) 2015-11-27

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