CN103873073B - A kind of based on Turbo code high-speed coding implementation method parallel with adding window structure - Google Patents
A kind of based on Turbo code high-speed coding implementation method parallel with adding window structure Download PDFInfo
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Abstract
The present invention relates to a kind of based on Turbo code high-speed coding implementation method parallel with adding window structure，Realized by Turbo code high speed decoder，Including first、Second input buffer module、First、Two external information memory modules、Interleaving/deinterleaving module、N number of SISO decoding units、Hard decision module and output buffer module，First、Two input buffer modules continuously receive the Frame of outside input in ping-pong operation mode，N number of SISO decoding units complete the first component decoding of first time iteration and second component is decoded，The like，The the first component decoding for completing the M time iteration is decoded with second component，Iteration ends，Process is deinterleaved in hard decision module to log-likelihood ratio information LLR that the second component decoding of the M time iteration is obtained，And hard decision is carried out by result is deinterleaved，Hard decision result is stored in output buffer module finally；The decoding of the method integrating parallel and the advantage of sliding window decoding, greatly improved the decoding speed of service, with preferable decoding performance.
Description
Technical field
The present invention relates to a kind of based on Turbo code high-speed coding implementation method parallel with adding window structure, belong to satellite shifting
Dynamic art communication systems field.
Background technology
In satellite mobile communication system, the signal that receiver is received is subjected to the impact such as fading channel and interference noise.
In this regard, satellite mobile communication system is frequently with the error control code Turbo or LDPC with high channel coding gain（Low-density is strange
Even parity check code）The bit error rate is reduced and approaches shannon limit improving the reliability of information transfer by code.The advantage of Turbo code exists
In its short code code word has more preferable error performance under Low SNR, is more suitable for burst transfer or real-time Communication for Power application
In.At present, Turbo code is by as DVB-RCS（DVB-satellite backhaul channel）、CCSDS（Aerospace Data Systems
Information committee）One of recommendation channel coding schemes Deng satellite mobile communication system and deep space communication system.Meanwhile, Turbo
Code is also in land mobile communication system such as 3GPP（3rd generation partner program）The LTE of normal structure（Long Term Evolution）System and
It is used widely in the systems such as WiMax.
The Turbo code that relatively this several system is adopted, it can be found that code word defined in 3GPP TS212 standards is employed
Maximum uncontested interleaver, it is provided that more flexible parallel exponent number is selected, and is more suitable for wide-band communication system high speed volume
Decoding application.So, here so that female code code efficiency is 1/3 Turbo code as an example, generator polynomial is expressed as
g0(D)=1+D2+D3,g1(D)=1+D+D3.
Also referred to as octal system（15,13）, the constraint length of the encoder is v=4, and its structure includes 28 state subgroups
Encoder, 1 Turbo code interleaver.Information c of the input length for Kk, code word of the coding output length for N=3K, comprising letter
Breath position ukAnd check bitTwo parts.The code word after information bit coding is added tail and returns to initial shape than special envoy encoder
State 0, through the Turbo code word that different punctured schemes are obtained more more high coding efficiencies.
Relative to encoder, decoder realizes that structure is more complex, and the design of wideband satellite communication receiver
Difficult point.Using iterative decoding thought be Turbo code an important feature, in order to realize translating in component in iterative decoding process
Soft Inform ation is exchanged between code device, and the component decoding of Turbo code must adopt SISO（Soft-output coding）Algorithm.Wherein, MAP
（Maximum a posteriori probability）Class algorithm compares SOVA（Soft output Viterbi）Class of algorithms performance will be got well, and reduce the MAP of complexity
Class algorithm is relatively easy to hardware realization, is widely used.Wherein, the implementation complexity of Max-Log-MAP algorithms is minimum.Often
MAP decoder architectures are as shown below, wherein,Represent information bit u of the component coder in the output at k momentk, ys、
y1p、y2pInformation bit and the respective check bit information of 2 component decoders after representing receiver demodulation, before decoding, and remember
Y={ys、y1p、y2p}.It is illustrated in figure 1 conventional MAP decoder architecture figures.
In an iterative process, the output L of component decoder 11(uk| Y) it is represented by system information, prior information and outside
Information：L1a(uk)、L1e(uk)
To component decoder 2, external information L2e(uk) be expressed as exporting L2(uk| Y) deduct system informationPriori
Information L2a(uk)：
In formula, π represents interleaving treatment：
L2a(uk)=L1e(uπ(k))、L1a(uπ(k))=L2e(uk)
Note current state is s, and previous state is s', then the log-likelihood information of Log-MAP decoding algorithms is
Wherein, define
1）Forward state metric,
2）Backward state measurement,
3）Branch metric, γk(s',s)=p(uk)p(yk|s',s)
Defining operationAccording to approximateMax-Log-MAP decoding algorithm is then obtained
1）
2）
3）
Obtain log-likelihood information
To state measurement value after needing to calculate during decoding due to MAP classes algorithm, complete sequence is therefore only received
Could start to decode after row.So, in the case where data sequence is long, the decoding delay of MAP class algorithms, must just than larger
Decoding delay must be reduced by changing algorithm.
Content of the invention
It is an object of the invention to overcoming the above-mentioned deficiency of prior art, there is provided a kind of based on parallel with adding window structure
Turbo code high-speed coding implementation method, the decoding of the method integrating parallel and the advantage of sliding window decoding, greatly improved decoding fortune
Scanning frequency degree, with preferable decoding performance, measured performance is less than 0.15dB than theoretical performance difference；Simultaneously using calculating in real time
Mode, has saved storage resource.
The above-mentioned purpose of the present invention is mainly achieved by following technical solution：
A kind of based on Turbo code high-speed coding implementation method parallel with adding window structure, by Turbo code high speed decoder
Realize, the Turbo code high speed decoder includes that the first input buffer module, the second input buffer module, the first external information are deposited
Storage module RAM3, the second external information memory module RAM4, interleaving/deinterleaving module, SISO decoding modules, hard decision module and defeated
Go out cache module RAM5, wherein the first input buffer module includes information bit memory element RAM1 and check bit memory element
RAM2, the second input buffer module include information bit memory element RAM1 ' and check bit memory element RAM2 ', SISO decodes mould
Block includes N number of SISO decoding units, implements process as follows：
Step（One）, the first input buffer module and the second input buffer module outside is continuously received in ping-pong operation mode
The Frame of input, the Frame are data to decode yk, by data to decode ykIn information bit ysIt is divided into isometric N sections
Information bit memory element RAM1 or RAM1 ' is stored in, by the first check bit y1p, the second check bit y2pIsometric N section is divided into respectively
It is stored in check bit memory element RAM2 or RAM2 '；
Step（Two）, interleaving/deinterleaving module produce sequence address and interleaving address, N number of SISO decoding units are according to institute
State sequence address and read information bit memory element RAM1 or information bit y for being divided into N sections in RAM1 ' respectivelysStore with check bit
The first check bit y for being divided into N sections in unit R AM2 or RAM2 '1p, the first component decoding of first time iteration is carried out, it is right to obtain
Number likelihood ratio information LLR and external information L for being divided into isometric N sections1e, by external information L1eIt is stored according to the sequence address
Second external information memory module RAM4；N number of SISO decoding units store mould from the second external information respectively according to the interleaving address
Block RAM 4 reads external information L for being divided into isometric N sections1e, while reading information bit memory element RAM1 according to the interleaving address
Or information bit y for being divided into N sections in RAM1 's, read in check bit memory element RAM2 or RAM2 ' according to the sequence address
The second check bit y for being divided into N sections2p, carry out first time iteration second component decoding, obtain log-likelihood ratio information LLR and
It is divided into external information L of isometric N sections2e, by external information L2eFirst external information memory module is stored according to the interleaving address
RAM3；
Step（Three）, N number of SISO decoding units according to the sequence address read respectively information bit memory element RAM1 or
Information bit y for being divided into N sections in RAM1 'sWith the first check bit for being divided into N sections in check bit memory element RAM2 or RAM2 '
y1p, while reading external information L in the first external information memory module RAM32e, the first component decoding of second iteration is carried out,
Obtain log-likelihood ratio information LLR and be divided into external information L' of isometric N sections1e, by external information L'1eAccording to the sequence address
It is stored in the second external information memory module RAM4；N number of SISO decoding units store mould according to the interleaving address from the second external information
Block RAM 4 reads external information L' for being divided into isometric N sections1e, according to the interleaving address read information bit memory element RAM1 or
Information bit y for being divided into N sections in RAM1 's, read in check bit memory element RAM2 or RAM2 ' according to the sequence address
It is divided into the second check bit y of N sections2p, the second component decoding of second iteration is carried out, log-likelihood ratio information LLR is obtained and is divided
External information L' for isometric N sections2e, by external information L'2eThe first external information memory module is stored according to the interleaving address
RAM3；
Step（Four）, the like, repeat step（Three）, complete first point of the M time iteration of N number of SISO decoding units
Amount decoding is decoded with second component, iteration ends, and the M is the iterationses for setting；
Step（Five）, log-likelihood ratio information LLR that the decoding of the second component of the M time iteration obtained is in hard decision module
In be deinterleaved process, and carry out hard decision by result is deinterleaved, hard decision result be stored in output caching mould finally
In block RAM 5；
Wherein N, M are positive integer, and N >=4, M >=6.
Above-mentioned based on Turbo code high-speed coding implementation method parallel with adding window structure in, step（One）Middle information bit
ysIt is divided into isometric N sections, the first check bit y1p, the second check bit y2pIsometric N sections are divided into, are embodied as：K is defined for letter
Breath bit length, represents with bit number, m=K/N is per section of length, and r is the overlap bit number that every section of head or tail is added, a frame number
According to N sections are uniformly divided into, the 1st segment length for sending into N number of SISO decoding units is m+r；Middle segment length is m+2r；Final stage
Length m+r+tail_bit, tail_bit represent information bit ys, the first check bit y1p, the second check bit y2pTail bit.
Above-mentioned based on Turbo code high-speed coding implementation method parallel with adding window structure in, step（One）In be divided into
Information bit y of long N sectionssIt is expressed as follows：
Bs[1,…,N]={{y0,y1,...,yK/N-1},...,{y(N-1)K/N,y(N-1)K/N+1,...,yK-1}}；
It is divided into the first check bit y of isometric N sections1p, the second check bit y2pIt is expressed as follows respectively：
B1p[1,…,N]={{yK,yK+1,...,y(N+1)K/N-1},...,{y(2N-1)K/N,y(2N-1)K/N+1,...,y2K-1}}；
B2p[1,...,N]={{y2K,y2K+1,...,y(2N+1)K/N-1},...,{y(3N-1)K/N,y(3N-1)K/N+1,...,
y3K-1}}；
By the data { B for reconfigurings[1](k),Bs[2](k),....,Bs[N] (k) }, k ∈ [0, K/N-1] are deposited in order
Enter information bit memory element RAM1 or RAM1 '；By the data { B for reconfiguring1p[1](k),B1p[2](k),….,B1p[N]
(k) }, k ∈ [0, K/N-1] be stored in check bit memory element RAM2 or RAM2 ' in order in top half；By reconfigured
Data { B2p[1](k),B2p[2](k),....,B2p[N] (k) }, k ∈ [0, K/N-1] are stored in check bit memory element in order
The latter half in RAM2, wherein, K is information bit length.
Above-mentioned based on Turbo code high-speed coding implementation method parallel with adding window structure in, in N number of SISO decoding units
Portion decodes flow process using sliding window, and what the decoding of the first component and second component for carrying out each iteration was decoded realizes process such as
Under, wherein each SISO decoding unit includes LIFO memory RAMs 6 and RAM7：
Step（One）, within the 1st sliding window time, calculate current data section last sliding window forward state metric
α, used as the initial value of first sliding window forward state metric α of next data segment；Calculate current data first sliding window of section
Backward state measurement β, as after initial value from upper last sliding window of a data segment to state measurement β；
Step（Two）, within the 2nd sliding window time, information bit y in the first sliding windows, check bit yp, priori letter
Breath LaIt is stored in the LIFO memory RAMs 6 that depth is 1 sliding window length SW；Calculate the forward-facing state of the 1st interior data of sliding
Tolerance α, stores to the LIFO memory RAMs 7 that depth is 1 sliding window length SW；Calculate the backward state degree of the 2nd sliding window
Amount β, as after effective original state from the 1st sliding window to state measurement β value；
Step（Three）, within the 3rd sliding window time, calculate the effective β value of backward state measurement of first sliding window, with
When read information bit y of caching from LIFO memory RAMs 6s, check bit yp, prior information La, from LIFO memory RAMs 7
Forward state metric α is read, log-likelihood ratio LLR and external information L is calculated togethere；
Step（Four）, the like, repeat step（Two）、（Three）, until completing last cunning in SISO decoding units
Dynamic window decoding.
Above-mentioned based on Turbo code high-speed coding implementation method parallel with adding window structure in, in N number of SISO decoding units
Portion can carry out the calculating of forward state metric α and backward state measurement β value simultaneously, further reduce decoding delay.
Above-mentioned based on Turbo code high-speed coding implementation method parallel with adding window structure in, also include logic control mould
Block, for being controlled to all modules of Turbo code high speed decoder, including to be decoded in first, second input buffer module
The Read-write Catrol of the fragmented storage of data, the piece selected control system of ping-pong operation；First, second external information memory module data enable,
Address controls；The startup of sliding window decoding, termination in SISO decoding units, whole decoding iteration control；Interleaving/deinterleaving module
Middle sequence address, the selection control of interleaving address；The enable control of hard decision module；In output buffer module, decoding result deposits
Storage and segmentation output control.
The present invention is had the advantages that compared with prior art：
（1）, innovative design of the present invention a kind of based on Turbo code high-speed coding implementation method parallel with adding window structure,
The decoding of decoding architecture integrating parallel and the advantage of sliding window decoding designed by the method, greatly improved the decoding speed of service,
In decoding clock 110MHz, effective information is more than 36Mbps；
（2）, system information position, check bit, external information storing process in Turbo code high-speed coding implementation method of the present invention
In, according to storage mode is merged, RAM numbers are reduced, is easy to encoded control；
（3）, memory element adopts dual port RAM form, SISO decoding units in Turbo code high-speed coding system of the present invention
The calculating that forward state metric α and backward state measurement train β value can be carried out simultaneously, decoding delay is further reduced；
（4）, the parallel adding window decoder designed by the present invention employ the Max-Log-MAP algorithms of optimization, with preferable
Decoding performance, measured performance than theoretical performance difference be less than 0.15dB；
（5）, present invention emulation found optimal data bit width, frame data are uniformly divided into N sections, and to per section
Length is optimized design, is realizing there is preferably compromise between resource consumption and decoding performance.
Description of the drawings
Fig. 1 is conventional MAP decoder architecture figures；
The decoder architecture block diagram that Fig. 2 is adopted by Turbo code high speed decoding method of the present invention；
Fig. 3 is SISO decoding units structural representation of the present invention；
Fig. 4 is SISO decoding units work decoding flow chart of the present invention；
Fig. 5 is Turbo code of the present invention theory and measured performance curve, r=0.4333,0.4888,0.5444.
Specific embodiment
The present invention is described in further detail with specific embodiment below in conjunction with the accompanying drawings：
The present invention combines the advantage of block parallel decoding and sliding window decoding, and design is a kind of to be based on N number of SISO decoding units
Parallel Turbo code decoder, and the sliding window decoding flow process inside the SISO using regular length, further to reduce decoding
Time delay simultaneously saves storage.
The decoder architecture block diagram adopted by Turbo code high speed decoding method of the present invention is illustrated in figure 2, the present invention
Turbo code high speed decoder includes the first input buffer module, the second input buffer module, the first external information memory module
RAM3, the second external information memory module RAM4, interleaving/deinterleaving module, Logic control module, SISO decoding modules, hard decision
Module and output buffer module RAM5, wherein the first input buffer module include information bit memory element RAM1 and check bit storage
Unit R AM2, the second input buffer module include information bit memory element RAM1 ' and check bit memory element RAM2 ', SISO is translated
Code module includes N number of SISO decoding units.The function of each module is as follows：
（1）First input buffer module/the second input buffer module：Store whole data to decode yk, by information bit ysDeposit
Enter information bit memory element RAM1/RAM1 ', by the first check bit y1p, the second check bit y2pIt is stored in check bit memory element
RAM2/RAM2’.Meanwhile, in order to realize interframe data continuous processing, two pieces of identical memory spaces are needed to continuous Frame
Carry out ping-pong operation.
（2）First and second external information memory module：External information L that storage SISO decoding modules are obtainedeArrive memory element RAM3
Or in RAM4, used as the prior information of the decodings of SISO next time, RAM3, RAM4 provide the decoding of the 1st component, the 2nd component respectively and translate
Prior information needed for code；
（3）SISO decoding modules：As the nucleus module of Turbo decoders, the realization of decoding algorithm is mainly completed, including
Forward state metric α, the calculating of backward state measurement β, decoder are output as log-likelihood ratio information LLR and external information Le.
SISO decoding units designed by the present invention have N number of：SISO_1、SISO_2、…、SISO_N；
（4）Interleaving/deinterleaving module：Read/write system position, the address signal of check bit sum external information is provided, address includes
Sequence address and interleaving address, provide sequence address when the 1st component is decoded, provide interleaving address when the 2nd component is decoded, wherein,
Need to be shifted accordingly according to the information that interleaving address reads；
（5）Output buffer module：Output buffer module RAM5 is used for storing decoding result and exporting.
（6）Logic control module：The control signal of whole decoder is produced, for being controlled to above-mentioned all modules,
Piece selected control system including the Read-write Catrol of the fragmented storage of data to decode, ping-pong operation in first, second input buffer module；
First, second external information memory module data are enabled, address control；The startup of sliding window decoding, termination in SISO decoding units,
Whole decoding iteration control；The selection control of sequence address, interleaving address in interleaving/deinterleaving module；Hard decision module makes
Can control；Storage and the segmentation output control of result is decoded in output buffer module.
If a signed fixed-point number is n according to the bit number of typecPosition, the 1st expression sign bit, low p positions are used for representing
Fractional part, high nc- p-1 positions are denoted as (n for representing integer partc, p) fixed point quantization.The bit wide of data select to performance and
Resource consumption has a great impact, and the present invention finds optimal data bit width, the data in the present invention by analyzing and emulating
Bit wide adopts following form：
1）Through channel information bit and check bit fixed point format for (6,2),
2）The fixed point format of prior information for (8,2),
3）The fixed point format of α and β for (11,2),
4）The fixed point format of log-likelihood ratio for (12,2).
In Turbo code decoder, the order in time that calculates of two components decoding is completed, component decoder 1 and point
The external information of other side is each needed as prior information between amount decoder 2, so the 1st component decoder and the decoding of the 2nd component
Device is multiplexed same component SISO decoding modules.
The present invention specifically includes following steps based on the Turbo code high-speed coding implementation method parallel with adding window structure：
Step（One）, the first input buffer module and the second input buffer module outside is continuously received in ping-pong operation mode
The Frame of input, the Frame are data to decode yk, by data to decode ykIn information bit ysIt is divided into isometric N sections
Information bit memory element RAM1 or RAM1 ' is stored in, by the first check bit y1p, the second check bit y2pIsometric N section is divided into respectively
It is stored in check bit memory element RAM2 or RAM2 '.
Wherein information bit ysIt is divided into isometric N sections, the first check bit y1p, the second check bit y2pIsometric N sections are divided into, are had
Body surface is shown as：Definition K is information bit length（Bit number）, being represented with bit number, m=K/N is per section of length, and r is every paragraph header
（Or tail）The overlap bit number of interpolation.General, the overlap bit number added between per section and per section is rsc encoder constraint length
5～8 times of degree can obtain preferable performance, be to simplify operation, choose fixed r=32bit, the beginning of first paragraph and most
One section need not finally be added overlap bit afterwards.One frame data are uniformly divided into N sections, send into the 1st of N number of SISO decoding units the
Segment length is m+r；Middle segment length is m+2r；Final stage length m+r+tail_bit, tail_bit represent information bit ys,
One check bit y1p, the second check bit y2pTail bit.
First input buffer module has received a frame data yk, k ∈ [0,3K-1], by system position information ysBelieve with check bit
Breath y1p、y2pIt is respectively divided, is wherein divided into information bit y of isometric N sectionssIt is expressed as follows：
Bs[1,…,N]={{y0,y1,...,yK/N-1},...,{y(N-1)K/N,y(N-1)K/N+1,...,yK-1}}；
It is divided into the first check bit y of isometric N sections1p, the second check bit y2pIt is expressed as follows respectively：
B1p[1,…,N]={{yK,yK+1,...,y(N+1)K/N-1},...,{y(2N-1)K/N,y(2N-1)K/N+1,...,y2K-1}}；
B2p[1,...,N]={{y2K,y2K+1,...,y(2N+1)K/N-1},...,{y(3N-1)K/N,y(3N-1)K/N+1,...,
y3K-1}}；
By the data { B for reconfigurings[1](k),Bs[2](k),….,Bs[N] (k) }, k ∈ [0, K/N-1] are deposited in order
Enter information bit memory element RAM1；By the data { B for reconfiguring1p[1](k),B1p[2](k),....,B1p[N](k)},k∈
[0, K/N-1] is stored in the top half in check bit memory element RAM2 in order；By the data { B for reconfiguring2p[1](k),
B2p[2](k),....,B2p[N] (k) }, k ∈ [0, K/N-1] are stored in the lower half in check bit memory element RAM2 in order
Point, and initialization extrinsic information memory element RAM3 is 0.SISO decoding units proceed by the decoding of frame data, while second
Input buffer module receives next frame data and stores buffering to which, and K is information bit length.
Step（Two）, interleaving/deinterleaving module produce sequence address and interleaving address, N number of SISO decoding units are according to institute
State sequence address and read information bit y for being divided into N sections in information bit memory element RAM1 respectivelysWith check bit memory element RAM2
In the first check bit y for being divided into N sections1p, the first component decoding of first time iteration is carried out, log-likelihood ratio information LLR is obtained
With external information L for being divided into isometric N sections1e, by external information L1eThe second external information storage mould is stored according to the sequence address
Block RAM 4.
It is illustrated in figure 3 SISO decoding units structural representation of the present invention；It is illustrated in figure 4 SISO decoding units of the present invention
Work decoding flow chart, decodes flow process, each SISO decoding unit using sliding window inside N number of SISO decoding units of the invention
Including LIFO memory RAMs 6 and RAM7, the concrete grammar of the first component decoding of first time iteration is as follows：
（1）, within the 1st sliding window time, calculate current data section last sliding window forward state metric α, make
Initial value for first sliding window forward state metric α of next data segment；Calculate current data first sliding window of section backward
State measurement β, as after initial value from upper last sliding window of a data segment to state measurement β；
（2）, within the 2nd sliding window time, information bit y in the first sliding windows, check bit yp, prior information LaDeposit
Enter in the LIFO memory RAMs 6 that depth is 1 sliding window length SW；Forward state metric α of the 1st interior data of sliding is calculated,
Store the LIFO memory RAMs 7 that depth is 1 sliding window length SW；The backward state measurement β 2 of the 2nd sliding window is calculated,
As the effective original state being worth to state measurement β 1 after the 1st sliding window；
（3）, within the 3rd sliding window time, the effective β 1 of backward state measurement for calculating first sliding window is worth, at the same from
Information bit y of caching is read in LIFO memory RAMs 6s, check bit yp, prior information L1a（Iteration is 0 first）, deposit from LIFO
Forward state metric α is read in reservoir RAM7, calculates log-likelihood ratio LLR and external information L together1e；
（4）, the like, repeat step（2）、（3）, translate until completing last sliding window in SISO decoding units
Code.
Memory element adopt dual port RAM form, so SISO decoding units can carry out simultaneously forward state metric α and
Backward state measurement trains the calculating of β value, further reduces decoding delay.
In SISO decoding unit workflow diagrams as shown in Figure 4, Cl steps include backward state measurement training β 2 and are worth
Calculating；C2 steps include the calculating of forward state metric α value；C3 steps include the effective β 1 of backward state measurement be worth, logarithm
Likelihood ratio LLR and external information value LeCalculate.
The last marginal value that backward state measurement training β 2 is calculated is worth the effective original state for calculating as β 1, and the values of β 1 are calculated
It is used at once calculating log-likelihood ratio LLR after out, so without the need for storage.
N number of SISO decoding units read from the second external information memory module RAM4 according to the interleaving address respectively and divide afterwards
External information L for isometric N sections1e, while read according to the interleaving address being divided into N sections in information bit memory element RAM1
Information bit ys, the second check bit y for being divided into N sections in check bit memory element RAM2 is read according to the sequence address2p, carry out
The second component decoding of first time iteration, obtains log-likelihood ratio information LLR and is divided into external information L of isometric N sections2e, will be outer
Information L2eFirst external information memory module RAM3 is stored according to the interleaving address.The second component interpretation method of first time iteration
With the first component interpretation method.
For obtaining preferably decoding performance, calculated external information can be optimized by being multiplied by a weighter factor ω
Max-Log-MAP decoding algorithms.The present invention takes ω=0.75, and is realized by shifting additive operation, to avoid using multiplier
Resource.
Step（Three）, N number of SISO decoding units are read in information bit memory element RAM1 respectively according to the sequence address
Information bit y for being divided into N sectionssWith the first check bit y for being divided into N sections in check bit memory element RAM21p, while reading first
External information L in external information memory module RAM32e, the first component decoding of second iteration is carried out, log-likelihood ratio letter is obtained
Breath LLR and external information L' for being divided into isometric N sections1e, by external information L'1eThe second external information is stored according to the sequence address to deposit
Storage module RAM4；N number of SISO decoding units read from the second external information memory module RAM4 according to the interleaving address and are divided into
External information L' of long N sections1e, the information bit for being divided into N sections in information bit memory element RAM1 is read according to the interleaving address
ys, the second check bit y for being divided into N sections in check bit memory element RAM2 is read according to the sequence address2p, carry out second
The second component decoding of iteration, obtains log-likelihood ratio information LLR and is divided into external information L' of isometric N sections2e, by external information
L'2eThe first external information memory module RAM3 is stored according to the interleaving address.The same step of the interpretation method of second iteration（Two）.
Step（Four）, the like, repeat step（Three）, complete first point of the M time iteration of N number of SISO decoding units
Amount decoding is decoded with second component, iteration ends, and the M is the iterationses for setting；
Step（Five）, log-likelihood ratio information LLR that the decoding of the second component of the M time iteration obtained is in hard decision module
In be deinterleaved process, and carry out hard decision by result is deinterleaved, hard decision result be stored in output caching mould finally
In block RAM 5；SISO decoding units are waited or proceed by the decoding of next frame.
Embodiment
The present invention be directed to one group of K={ 1248,1408,1568 } defined in 3GPP TS212 standards, the code word of L=2880,
Design is a kind of to be based on N（N=8）The parallel Turbo code decoder of individual SISO decoding units.
Input-buffer unit has received a frame data yk, k ∈ [0,3K-1], by system position information ysWith check bit information
y1p、y2pIt is respectively divided into 8 isometric sections：Bs[1 ..., 8], B1p[1 ..., 8], B2p[1 ..., 8], by the data for reconfiguring
{Bs[1](k),Bs[2](k),….,Bs}, [8] (k) k ∈ [0, K/8-1] are stored in information bit memory element RAM1 in order；Will weight
Data { the B of Combination nova1p[1](k),B1p[2](k),....,B1p}, [8] (k) k ∈ [0, K/8-1] are stored in check bit in order and deposit
Top half in storage unit RAM2；By the data { B for reconfiguring2p[1](k),B2p[2](k),....,B2p[8](k)},k∈
[0, K/8-1] is stored in the latter half in check bit memory element RAM2 in order.And initialization extrinsic information memory element RAM3
For 0, decoding unit proceeds by the decoding of frame data, while receiving next frame data stores buffering to which.
Init state metric parameter.To all subsegments, except the 1st subsegment indictment state and last subsegment shape of tail state known to
Outward, the state of other subsegment head and the tail is all unknown.For known subsegment α（Or β）8 state s ∈ { 0,1,2 ..., 7 } just
Initial value, it is 0 to make known state, and unknown state is -256；To unknown subsegment α（Or β）The initial value of 8 states, using overlap ratio
The mode of special recursion is obtained, and overlaps bit alpha（Or β）It is that equiprobability occurs that the initial value of state is set to the state of 0, i.e., 8.
Then, start concurrently to carry out all subsegments the 1st iterative decoding.
1st component decoder is decoded.Information bit y is read from RAM1, RAM2, RAM3 in order respectivelys, the 1st verification
Position y1p, prior information L1a（That is external information L2e, iteration is 0 first）Send into SISO decoding units and do the decoding of the 1st component, after decoding
External information L for obtaining1eIt is stored in external information memory element RAM4 in order, as the prior information of the 2nd component decoder.
2nd component decoder is decoded.First, state measurement parameter is initialized.Then, from RAM1, RAM4
Information bit y is read respectively by interleaved orders, prior information L2a（That is external information L1e）, and with RAM2 in the 2nd check bit y2pOne
Play feeding SISO decoding units and do the decoding of the 2nd component, external information L obtained after decoding2eExternal information is stored in by deinterleaving order to deposit
Storage unit RAM3, used as the prior information of the 1st component decoder.
Iterate maximum iteration time M set in advance is reached until iterationses.Wherein memory element is using double
Mouth RAM forms, so SISO decoding modules can carry out the meter that forward state metric α and backward state measurement train β value simultaneously
Calculate.
Iteration ends, output caching.After predetermined iterationses M is completed, to obtaining after the decoding of the 2nd component
Log-likelihood ratio through deinterleaving carries out hard decision, and hard decision result is stored in output caching RAM5, decoding unit etc.
Treat or proceed by the decoding of next frame.
Designed software program is realized using Xilinx XC6VLX240T chips, designed decoder work
, up to 110MHz, effective information speed is up to 36Mbps for clock；It is 6024 that resource is consumed for taking slice numbers, is this chip
The 16% of 37680 slice, takes 8 36k RAM, is the 2% of this resources of chip.
Give the Turbo code decoder performance curve that FPGA of the present invention is realized as shown in Figure 5, and provide theoretical curve and do
Relatively, signal is modulated using BPSK, and information is that length is respectively K={ 1248,1408,1568 }, through rate-matched mould after coding
The a length of L=2880 of block Turbo code.All simulation results are with signal to noise ratio (Eb/N0) and the bit error rate（BER）Relation curve form give
Go out.From simulation curve as can be seen that the Turbo code decoder and theoretical curve of FPGA realizations are in 8 iteration, performance loss is not
More than 0.15dB.
The above, optimal specific embodiment only of the invention, but protection scope of the present invention is not limited thereto,
Any those familiar with the art the invention discloses technical scope in, the change or replacement that can readily occur in,
Should all be included within the scope of the present invention.
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.
Claims (5)
1. a kind of based on Turbo code high-speed coding implementation method parallel with adding window structure, it is characterised in that：By Turbo code
High speed decoder realizes, the Turbo code high speed decoder include the first input buffer module, the second input buffer module, the
One external information memory module RAM3, the second external information memory module RAM4, interleaving/deinterleaving module, SISO decoding modules, sentence firmly
Certainly module and output buffer module RAM5, wherein the first input buffer module include that information bit memory element RAM1 and check bit are deposited
Storage unit RAM2, the second input buffer module include information bit memory element RAM1 ' and check bit memory element RAM2 ', SISO
Decoding module includes N number of SISO decoding units, implements process as follows：
Step (one), the first input buffer module and the second input buffer module continuously receive outside input in ping-pong operation mode
Frame, the Frame be data to decode yk, by data to decode ykIn information bit ysIt is divided into isometric N sections to be stored in
Information bit memory element RAM1 or RAM1 ', by the first check bit y1p, the second check bit y2pIt is divided into isometric N sections respectively to be stored in
Check bit memory element RAM2 or RAM2 '；
Step (two), interleaving/deinterleaving module produce sequence address and interleaving address, and N number of SISO decoding units are according to described suitable
Sequence address reads information bit memory element RAM1 or information bit y for being divided into N sections in RAM1 ' respectivelysWith check bit memory element
The first check bit y for being divided into N sections in RAM2 or RAM2 '1p, the first component decoding of first time iteration is carried out, logarithm is obtained seemingly
So than information LLR and external information L for being divided into isometric N sections1e, by external information L1eSecond is stored according to the sequence address
External information memory module RAM4；N number of SISO decoding units are according to the interleaving address respectively from the second external information memory module
RAM4 reads external information L for being divided into isometric N sections1e, while according to the interleaving address read information bit memory element RAM1 or
Information bit y for being divided into N sections in RAM1 's, read in check bit memory element RAM2 or RAM2 ' according to the sequence address
It is divided into the second check bit y of N sections2p, the second component decoding of first time iteration is carried out, log-likelihood ratio information LLR is obtained and is divided
External information L for isometric N sections2e, by external information L2eFirst external information memory module RAM3 is stored according to the interleaving address；
Step (three), N number of SISO decoding units read information bit memory element RAM1 or RAM1 ' respectively according to the sequence address
In information bit y for being divided into N sectionssWith the first check bit y for being divided into N sections in check bit memory element RAM2 or RAM2 '1p, with
When read external information L in the first external information memory module RAM32e, the first component decoding of second iteration is carried out, it is right to obtain
Number likelihood ratio information LLR and external information L' for being divided into isometric N sections1e, by external information L'1eIs stored according to the sequence address
Two external information memory modules RAM4；N number of SISO decoding units are according to the interleaving address from the second external information memory module RAM4
Read external information L' for being divided into isometric N sections1e, read in information bit memory element RAM1 or RAM1 ' according to the interleaving address
Information bit y for being divided into N sectionss, read according to the sequence address and be divided into N sections in check bit memory element RAM2 or RAM2 '
The second check bit y2p, the second component decoding of second iteration is carried out, log-likelihood ratio information LLR is obtained and is divided into isometric
External information L' of N sections2e, by external information L'2eThe first external information memory module RAM3 is stored according to the interleaving address；
Step (four), the like, repeat step (three), the first component for completing the M time iteration of N number of SISO decoding units are translated
Code is decoded with second component, iteration ends, and the M is the iterationses for setting；
Step (five), log-likelihood ratio information LLR that the decoding of the second component of the M time iteration is obtained is entered in hard decision module
Row deinterleaving is processed, and carries out hard decision by result is deinterleaved, and hard decision result is stored in output buffer module finally
In RAM5；
Wherein N, M are positive integer, and N >=4, M >=6.
2. according to claim 1 a kind of based on Turbo code high-speed coding implementation method parallel with adding window structure, which is special
Levy and be：Information bit y in step (one)sIt is divided into isometric N sections, the first check bit y1p, the second check bit y2pIt is divided into
Long N sections, are embodied as：Definition K is information bit length, is represented with bit number, and m=K/N is per section of length, and r is per section
The overlap bit number that head or tail is added, frame data are uniformly divided into N sections, and the 1st segment length for sending into N number of SISO decoding units is
m+r；Middle segment length is m+2r；Final stage length m+r+tail_bit, tail_bit represent information bit ys, the first check bit
y1p, the second check bit y2pTail bit number.
3. according to claim 1 a kind of based on Turbo code high-speed coding implementation method parallel with adding window structure, which is special
Levy and be：Flow process is decoded using sliding window inside N number of SISO decoding units, the first component decoding of each iteration is carried out
With second component decoding realize that process is as follows, wherein each SISO decoding unit includes LIFO memory RAMs 6 and RAM7：
Step (one), within the first sliding window time, calculate current data section last sliding window forward state metric α,
Initial value as first sliding window forward state metric α of next data segment；After calculating current data first sliding window of section
To state measurement β, as after initial value from upper last sliding window of a data segment to state measurement β；
Step (two), within the second sliding window time, information bit y in the first sliding windows, check bit yp, prior information La
It is stored in the LIFO memory RAMs 6 that depth is sliding window length SW；Calculate the forward-facing state of data in first sliding window
Tolerance α, stores to the LIFO memory RAMs 7 that depth is sliding window length SW；Calculate the backward state of second sliding window
Tolerance β, as after effective original state from first sliding window to state measurement β value；
Step (three), the effective β value of backward state measurement within the 3rd sliding window time, calculating first sliding window, while
Information bit y of caching is read from LIFO memory RAMs 6s, check bit yp, prior information La, read from LIFO memory RAMs 7
Forward state metric α is taken, log-likelihood ratio LLR and external information L is calculated togethere；
Step (four), the like, repeat step (two), (three), until completing last sliding window in SISO decoding units
Decoding.
4. according to claim 1 a kind of based on Turbo code high-speed coding implementation method parallel with adding window structure, which is special
Levy and be：The meter of forward state metric α and backward state measurement β value is carried out inside N number of SISO decoding units simultaneously can
Calculate, further reduce decoding delay.
5. according to claim 1 a kind of based on Turbo code high-speed coding implementation method parallel with adding window structure, which is special
Levy and be：Also include Logic control module, for being controlled to all modules of Turbo code high speed decoder, including first,
The piece selected control system of the Read-write Catrol of the fragmented storage of data to decode, ping-pong operation in two input buffer modules；Outside first, second
Information storage module data are enabled, address control；The startup of sliding window decoding, termination in SISO decoding units, whole decoding change
Generation control；The selection control of sequence address, interleaving address in interleaving/deinterleaving module；The enable control of hard decision module；Output
Storage and the segmentation output control of result is decoded in cache module.
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| CN105337685B (en) * | 2014-07-28 | 2018-12-07 | 华为技术有限公司 | A kind of figure group detection method and its device |
| CN104702294B (en) * | 2015-03-26 | 2018-04-27 | 北京思朗科技有限责任公司 | A kind of asymmetric imitate of bit wide of Turbo decoders deposits interface |
| CN106712778B (en) * | 2015-08-05 | 2020-05-26 | 展讯通信（上海）有限公司 | Turbo decoding device and method |
| WO2017127973A1 (en) * | 2016-01-25 | 2017-08-03 | Qualcomm Incorporated | Generation of polar codes with a variable block length utilizing puncturing |
| CN107302371B (en) * | 2016-04-14 | 2020-10-27 | 联芯科技有限公司 | Turbo code decoding system and decoding method |
| CN107370555B (en) * | 2016-05-12 | 2020-03-17 | 博通集成电路（上海）股份有限公司 | Error decision method and device |
| CN107453761B (en) * | 2016-05-31 | 2021-04-06 | 展讯通信（上海）有限公司 | Turbo code decoding method and Turbo code decoder |
| CN108270452B (en) * | 2016-12-30 | 2021-07-20 | 芯原微电子（成都）有限公司 | Turbo decoder and decoding method |
| CN108736900B (en) * | 2017-04-21 | 2021-08-24 | 展讯通信（上海）有限公司 | Turbo code decoding control method and device, computer readable medium and terminal |
| CN107565983B (en) * | 2017-09-08 | 2020-08-11 | 广东工业大学 | Turbo code decoding method and device |
| CN111147084B (en) * | 2018-11-06 | 2023-12-19 | 北京忆芯科技有限公司 | Multichannel parallel decoder and decoding method thereof |
| CN111525980B (en) * | 2019-02-01 | 2021-09-17 | 华为技术有限公司 | Decoding method and device |
| CN110601792B (en) * | 2019-07-31 | 2022-02-01 | 苏州门海微电子科技有限公司 | Front-end coding and decoding system and method for broadband power carrier communication |
| CN112332868A (en) * | 2020-10-20 | 2021-02-05 | 陕西航天技术应用研究院有限公司 | Turbo parallel decoding method based on DVB-RCS2 |
| CN112398487A (en) * | 2020-12-14 | 2021-02-23 | 中科院计算技术研究所南京移动通信与计算创新研究院 | Implementation method and system for reducing complexity of Turbo parallel decoding |
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| JP3898574B2 (en) * | 2002-06-05 | 2007-03-28 | 富士通株式会社 | Turbo decoding method and turbo decoding apparatus |
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