CN115514377A - Turbo decoding circuit and decoding method - Google Patents

Turbo decoding circuit and decoding method Download PDF

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CN115514377A
CN115514377A CN202210976461.7A CN202210976461A CN115514377A CN 115514377 A CN115514377 A CN 115514377A CN 202210976461 A CN202210976461 A CN 202210976461A CN 115514377 A CN115514377 A CN 115514377A
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information
decoder
input
sequence
detection value
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胡建国
张充
宋政
马志华
夏邦
林芸晓
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Sun Yat Sen University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2771—Internal interleaver for turbo codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations

Abstract

The invention discloses a Turbo decoding circuit and a decoding method.A first decoder inputs a detection value s (k), a detection value p (k) and prior information of an information bit sequence
Figure DDA0003798616520000011
Outputting posterior information
Figure DDA0003798616520000012
Posterior information
Figure DDA0003798616520000013
The first interleaver is input to a second decoder; the detection value s (k) is input to a second decoder after passing through a second interleaver; the second interleaver receives the detected value p' (k) of the second check sequence and performs decodingCode calculation, outputting a posteriori information of bits of an information sequence
Figure DDA0003798616520000014
Posterior information
Figure DDA0003798616520000015
After being processed by a deinterleaver, the data is input to a second decoder as a next iteration process; a priori information of a first decoder
Figure DDA0003798616520000016
The invention converts the input and output calculation process of the decoder into a logarithm form, converts multiplication operation into addition operation, avoids complex exponential operation, greatly simplifies the calculation process, reduces decoding delay and can be widely applied to the field of integrated circuits.

Description

Turbo decoding circuit and decoding method
Technical Field
The invention relates to the field of integrated circuits, in particular to a Turbo decoding circuit and a Turbo decoding method.
Background
In NB-IoT digital baseband processing, turbo codes are a near shannon limit error correction coding scheme commonly used for wireless data transmission, and attract great attention. In the NB-IoT application scenario, the requirements on power consumption are extremely strict. In the whole design process, the component decoder is the key point of the design, the Turbo codes in different standards have different structures, and generally, two algorithms are used for the execution of the Turbo codes: one is a soft output viterbi decoding algorithm (SOVA algorithm) based on an improvement of the viterbi decoding algorithm; the other is the maximum a posteriori probability decoding algorithm (MAP algorithm) and its improvement.
The SOVA algorithm has the advantages of low decoding complexity and convenient implementation, but the decoding performance of the SOVA algorithm is worst and lacks stability. The decoding performance of the MAP algorithm is superior to that of the SOVA algorithm, and the MAP algorithm has the defects of high operation complexity, large required storage space and difficulty in realization in practice.
Disclosure of Invention
In order to solve at least one of the technical problems in the prior art to a certain extent, the present invention provides a Turbo decoding circuit and a decoding method.
The technical scheme adopted by the invention is as follows:
a Turbo decoding circuit comprises a first decoder, a second decoder, a first interleaver, a second interleaver and a de-interleaver;
the decoding process of the Turbo decoding circuit is an iterative process, the input is the prior information of the system information bit, and the output is the posterior information of the system information bit after decoding;
one iteration process is as follows:
the input information of the first decoder comprises a detection value s (k) of the information sequence, a detection value p (k) of the first check sequence and a priori information of the information bit sequence
Figure BDA0003798616500000011
The first decoder outputs a posteriori information of the bits of the information sequence
Figure BDA0003798616500000012
Posterior information
Figure BDA0003798616500000013
The first interleaver is input to a second decoder; the detection value s (k) of the information sequence is input to a second decoder after passing through a second interleaver;
the second interleaver receives the detection value p' (k) of the second check sequence, performs decoding calculation, and outputs a posteriori information of each bit of the information sequence
Figure BDA0003798616500000014
Posterior information
Figure BDA0003798616500000015
After de-interleaver, as prior information of the first decoder in the next iteration process
Figure BDA0003798616500000016
The input and output calculation process of the decoder is converted into a logarithm form, and multiplication operation is converted into addition operation so as to avoid complex exponential operation.
Furthermore, the first decoder and the second decoder have the same structure and are both soft input and output decoders;
information is continuously exchanged and iterated between the two decoders to meet the requirement of the decoding performance of the Turbo code.
Further, forward recursion, backward recursion and branch measurement are subjected to logarithmic value taking and then calculation is carried out.
Furthermore, the decoder comprises a branch metric calculation module, a forward recursion module, a backward recursion module, a likelihood information calculation module and an external information calculation module;
the input information of the branch metric calculation module is a detection value s (k), a detection value p (k) and prior information
Figure BDA0003798616500000021
Branch metric M outputting four different values k (e) Are each M k (0,0),M k (0,1),M k (1,0),M k (1,1)；
The forward recursion module and the backward recursion module measure M according to four branches k (e) Calculating to obtain a recursion value of the current moment;
the likelihood information calculation module calculates according to the recursion value to obtain a result of a likelihood ratio;
and the extrinsic information calculation module is used for calculating extrinsic information generated by the current decoder according to the result of the likelihood ratio.
Further, the branch metric calculation module is composed of an adder and an inverter.
Furthermore, the forward recursion module and the backward recursion module are both composed of an adder and a comparator.
Furthermore, the Turbo decoding circuit adopts a parallel decoding mode to decode.
The other technical scheme adopted by the invention is as follows:
a decoding method applied to the Turbo decoding circuit includes the following steps:
the detection value s (k) of the information sequence, the detection value p (k) of the first check sequence and the prior information of the information bit sequence
Figure BDA0003798616500000022
Inputting the first decoder, outputting the posterior information
Figure BDA0003798616500000023
For posterior information
Figure BDA0003798616500000024
After one interleaving, inputting the interleaved data into a second decoder;
the detection value s (k) is input into a second decoder after being interleaved for one time;
after the second interleaver receives the detection value p' (k) of the second check sequence, decoding calculation is performed to output a posteriori information of each bit of the information sequence
Figure BDA0003798616500000025
For posterior information
Figure BDA0003798616500000026
After one time of de-interleaving, the de-interleaved data is used as prior information of the first decoder in the next iteration process
Figure BDA0003798616500000027
Information is continuously exchanged and iterated between the two decoders until the requirement of the decoding performance of the Turbo code is met.
The invention has the beneficial effects that: the invention converts the input and output calculation process of the decoder into a logarithm form, converts the multiplication operation into the addition operation, avoids complex exponential operation, greatly simplifies the calculation process, reduces the decoding delay and can obtain the effect of low power consumption.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description is made on the drawings of the embodiments of the present invention or the related technical solutions in the prior art, and it should be understood that the drawings in the following description are only for convenience and clarity of describing some embodiments in the technical solutions of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a block diagram of a Turbo decoder circuit in an embodiment of the present invention;
FIG. 2 is an overall circuit diagram of a low power consumption Turbo code decoding circuit according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating the concept of grid graph edges in an embodiment of the present invention;
FIG. 4 is a circuit diagram of a branch metric calculation module in an embodiment of the present invention;
FIG. 5 is a circuit diagram of forward state metric and backward state metric calculation modules in an embodiment of the present invention;
fig. 6 is a circuit diagram of the likelihood ratio calculation module and the extrinsic information calculation module according to the embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. The step numbers in the following embodiments are provided only for convenience of illustration, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless otherwise specifically limited, terms such as set, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention by combining the specific contents of the technical solutions.
Because the MAP algorithm is provided earlier, after decades of correction and improvement, the decoding performance approaches to the aroma limit, and the decoding computation amount and complexity are also greatly reduced, so that the MAP algorithm improved algorithm is more widely popularized in practical application. Compared with the Log-MAP algorithm, the Max-Log-MAP algorithm of the invention uses the Max () function to simulate the Max () function, removes the flow of searching the data table, further simplifies the operation process, reduces the decoding time delay, and reduces the complexity and the required storage space. The result of this simplification process is that about 0.3dB of decoding performance is lost, but for the application field with large overall system gain margin, the hardware cost and real-time performance are really considerable due to these performance losses. The Turbo code decoding circuit of the present invention is explained in detail below.
As shown in fig. 1, fig. 1 is a structural diagram of a Turbo decoder circuit, a Turbo code decoding process is an iterative process, and the Turbo code decoding circuit includes two decoders (i.e., a decoder 1 and a decoder 2) with the same structure, and in this embodiment, both the decoders are soft input output decoders (SISO). The decoder inputs the prior information of the system information bits, and outputs the posterior information of the system information bits after decoding.
The parameters in fig. 1 are defined as follows:
p (k) -check information, check value of the sequence.
s (k) -system information, the detected value of the information sequence.
La(u k ) -a priori information, from initial a priori information or the result of the last iteration.
Le(u k ) A posteriori information, the output of the information bits calculated by the decoding algorithm.
L(u k ) Likelihood information, input symbol information u k The log likelihood ratio of (c).
In an iterative process, the decoder 1 inputs the detected value s (k) of the received information sequence, the detected value p (k) of the received check sequence generated by the first sub-encoder, and the a priori information of the information bit sequence
Figure BDA0003798616500000041
After decoding operation, outputting posterior information of each bit of information sequence
Figure BDA0003798616500000042
The a posteriori information is interleaved once and then input to the decoder 2 as a priori information thereof. At the same time, the received information sequence s (k) is also interleaved once and input to the decoder 2, and the check sequence p' (k) corresponding to the second sub-encoder is received. The decoder 2 outputs a posteriori information of the bits of the (interleaved) information sequence after a decoding calculation
Figure BDA0003798616500000043
The a posteriori information sequence is input to the decoder 2 after one time de-interleaving, and is used as a priori information of the decoder 1 in the next iteration process. Therefore, the soft information is continuously exchanged and iterated between the two sub-decoders, and the requirement of the Turbo code decoding performance is met.
Before analyzing the decision function, edge concepts in the trellis, also called branches (corresponding branch metrics), are defined, as shown in fig. 3. Wherein the starting state and the ending state of the edge are respectively
Figure BDA0003798616500000044
And
Figure BDA0003798616500000045
the input information symbol is u k (e) Code word symbol is c k (e) The time index is k. It can be seen that at time k, the input information bits and the start state uniquely determine the output codeword, the end state and the edges in the trellis diagram. Here, the
Figure BDA0003798616500000046
The definition of each character in fig. 3 is as follows:
u k -the information bits input at time k.
c k -the encoded output codeword at time k.
X k -the transmitted symbol at time k.
Y k -received symbols at time k.
Figure BDA0003798616500000051
-transmitting a signal X of the code sequence from instant i i Signal X to time j j The corresponding sequence.
Figure BDA0003798616500000052
-receiving the signal Y of the code sequence from the instant i i Signal Y to time j j The corresponding sequence.
Decoder output symbol information u for MAP algorithm k The posterior probability log-likelihood ratio is as shown in equation 1:
Figure BDA0003798616500000053
when the received information bit u has two symbol states u =0 or 1, the posterior probability of the decoding output information bit probability at the time k is shown in formula 2:
Figure BDA0003798616500000054
after the forward recursion and the backward recursion are deduced, the remained gamma k (s) is the branch transition probability, also called branch metric, which can be derived as formula 3 using bayesian formula:
Figure BDA0003798616500000055
in summary, after the forward recursion, the backward recursion and the branch metric are derived, the MAP algorithm uses a log-likelihood ratio (LLR) as a decision function, as shown in equation 4:
Figure BDA0003798616500000056
as can be seen from the above, the MAP decoding algorithm includes a large number of exponential operations and multiplication operations, which results in higher decoding complexity and greater hardware implementation difficulty. Therefore, in the embodiment, the input and output calculation process of the decoder is converted into a logarithmic form, and the multiplication operation is converted into the addition operation, so that the complex exponential operation is avoided. Carrying out logarithmic value calculation on key forward recursion, backward recursion and branch measurement, and introducing a Jacobian equation according to the calculation in the map algorithm, wherein the formula is shown as a formula 5:
ln(e x +e y )＝max(x,y)+ln(1+e -|x-y| )＝max*(x,y) (5)
the Max-Log-MAP algorithm is a further simplification of the MAP algorithm, and compared with the Log-MAP algorithm, the Max () function is used to be quasi-equal to the Max () function, and the result of simplifying the decision function of the Log-MAP algorithm is shown in formula 6. Finally, max-Log-Decoding result calculated by MAP algorithm
Figure BDA0003798616500000061
Is according to L M-log (u k ) The value of (c) is decided as shown in equation 7.
Figure BDA0003798616500000062
Figure BDA0003798616500000063
As shown in fig. 2, the overall circuit diagram of Turbo code decoding is shown as 2. As can be seen from fig. 2, the decoder includes a branch metric calculation M k Forward recursion module, backward recursion module, likelihood information calculation LLR and extrinsic information calculation L e And fourthly, the method comprises the following steps.
Referring to fig. 4, fig. 4 is a circuit diagram of a branch metric calculation module. The transmission channel model of the system is the channel ratio E s /N o Additive white Gaussian noise channel (AWGN), wherein the coded information is BPSK modulated in the channel, and the transmitted check information symbol
Figure BDA0003798616500000064
Is the result of a bipolar transformation of the symbols, i.e.
Figure BDA0003798616500000065
According to the state transition diagram of the Turbo code, only two edges of any state at a certain moment are transferred to a certain state at the next moment, only 4 edges in the grid diagram can be subjected to state transition at adjacent moments, and when the check bit is +/-1, the extrinsic information Le is summed with the parity bit
Figure BDA0003798616500000066
Are combined such that the branch metric M k (e) Taking four different values, M respectively k (0,0),M k (0,1),M k (1,0),M k (1,1)。
Referring to fig. 5, fig. 5 is a circuit diagram of a multiplexer in a circuit for Turbo code encoding, a circuit diagram of forward state metric and backward state metric calculation modules. And the state measurement module adopts a feedback iteration structure for calculation, and feeds a new state measurement value obtained by calculation back to the input end so as to participate in next recursion calculation. FIG. 5 is a diagram of a four-state forward recursion hardware implementation, with backward recursion for the same reason. The forward and backward recursion values are two important intermediate variables in the Turbo decoding iterative process, and as can be seen from the circuit structure in the figure, the calculation of the recursion values is to add and compare the corresponding branch metric value and the recursion value at the previous moment, so as to calculate the recursion value at the current moment.
Referring to fig. 6, a circuit diagram of the likelihood ratio calculation module and extrinsic information calculation module is shown. In the likelihood ratio calculation module, the input data u can be calculated by dividing the input data into four parts, namely a first part and a second part k And taking the path of 0 or 1, and comparing the corresponding branch metric and the state metric by the third part and the fourth part to finally obtain a result of the likelihood ratio. And the extrinsic information calculation module circuit module is used for calculating extrinsic information generated by the current sub-decoder, and the extrinsic information is fed back to the other sub-decoder to be used as prior information.
As clearly shown in fig. 4-6, all operations in the decoder are simple addition or comparison operations, which greatly simplifies the operation process, reduces the decoding delay, and reduces the complexity and required storage space. Referring to fig. 2, in addition, the Turbo code decoding circuit adopts a parallel decoding mode, calculates a forward recursion value and a backward recursion value at the same time, improves a decoding structure, and can effectively reduce power consumption.
In summary, compared with the prior art, the present embodiment has the following advantages and beneficial effects: the Turbo code decoding circuit of the embodiment is not only simple in operation, but also low in power consumption, and is realized through a Verilog hardware description language, simulation and synthesis are performed by taking an Altera cycle IV EP4CE75F23C8 as a target device, and the power consumption of the encoding circuit is lower than 30mW under the frequency of 125MHz, so that the requirement of low power consumption in an NB-IoT application scene can be met.
In the foregoing description of the specification, reference to the description of "one embodiment/example," "another embodiment/example," or "certain embodiments/examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1. The Turbo decoding circuit is characterized by comprising a first decoder, a second decoder, a first interleaver, a second interleaver and a de-interleaver;
the decoding process of the Turbo decoding circuit is an iterative process, the input is the prior information of the system information bit, and the output is the posterior information of the system information bit after decoding;
one of the iteration processes is as follows:
the input information of the first decoder comprises a detection value s (k) of the information sequence, a detection value p (k) of the first check sequence and a priori information of the information bit sequence
Figure FDA0003798616490000011
The first decoder outputs a posteriori information of the bits of the information sequence
Figure FDA0003798616490000012
Posterior information
Figure FDA0003798616490000013
The first interleaver is input to a second decoder; the detection value s (k) of the information sequence is input to a second decoder after passing through a second interleaver;
the second interleaver receives the detection value p' (k) of the second check sequence, performs decoding calculation, and outputs a posteriori information of each bit of the information sequence
Figure FDA0003798616490000014
Posterior information
Figure FDA0003798616490000015
After de-interleaver, as prior information of the first decoder in the next iteration process
Figure FDA0003798616490000016
The input and output calculation process of the decoder is converted into a logarithm form, and multiplication operation is converted into addition operation so as to avoid complex exponential operation.
2. The Turbo decoding circuit of claim 1, wherein the first decoder and the second decoder have the same structure and are both soft input-output decoders;
information is continuously exchanged and iterated between the two decoders to meet the requirement of the decoding performance of the Turbo code.
3. The Turbo decoding circuit of claim 1, wherein the forward recursion, the backward recursion, and the branch metric are logarithmically evaluated and then calculated in the decoder.
4. The Turbo decoding circuit of claim 3, wherein the decoder comprises a branch metric calculation module, a forward recursion module, a backward recursion module, a likelihood information calculation module, and an extrinsic information calculation module;
the input information of the branch metric calculation module is a detection value s (k), a detection value p (k) and prior information
Figure FDA0003798616490000017
Branch metric M outputting four different values k (e) Are each M k (0，0)，M k (0，1)，M k (1，0)，M k (1，1)；
The forward recursion module and the backward recursion module measure M according to four branches k (e) Calculating to obtain a recursion value of the current moment;
the likelihood information calculation module calculates according to the recursion value to obtain a result of a likelihood ratio;
and the extrinsic information calculation module is used for calculating extrinsic information generated by the current decoder according to the result of the likelihood ratio.
5. The Turbo decoding circuit of claim 4, wherein the branch metric computation module comprises an adder and an inverter.
6. The Turbo decoding circuit of claim 4, wherein said forward recursion module and said backward recursion module each comprise an adder and a comparator.
7. The Turbo decoding circuit of claim 1, wherein the Turbo decoding circuit performs decoding in a parallel decoding manner.
8. A decoding method applied to the Turbo decoding circuit according to any one of claims 1 to 7, comprising the steps of:
the detection value s (k) of the information sequence, the detection value p (k) of the first check sequence and the prior information of the information bit sequence
Figure FDA0003798616490000021
Inputting the first decoder, outputting the posterior information
Figure FDA0003798616490000022
For posterior information
Figure FDA0003798616490000023
After one interleaving, inputting the interleaved data into a second decoder;
the detection value s (k) is input into a second decoder after being interleaved for one time;
after the second interleaver receives the detection value p' (k) of the second check sequence, decoding calculation is performed to output a posteriori information of each bit of the information sequence
Figure FDA0003798616490000024
For posterior information
Figure FDA0003798616490000025
After one time of de-interleaving, the de-interleaved data is used as prior information of the first decoder in the next iteration process
Figure FDA0003798616490000026
Information is continuously exchanged and iterated between the two decoders until the requirement of the decoding performance of the Turbo code is met.
CN202210976461.7A 2022-08-15 2022-08-15 Turbo decoding circuit and decoding method Pending CN115514377A (en)

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