CN103871918A - Method for defect locating in wafer - Google Patents
Method for defect locating in wafer Download PDFInfo
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- CN103871918A CN103871918A CN201210528649.1A CN201210528649A CN103871918A CN 103871918 A CN103871918 A CN 103871918A CN 201210528649 A CN201210528649 A CN 201210528649A CN 103871918 A CN103871918 A CN 103871918A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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Abstract
The invention provides a method for defect locating in a wafer. By means of a first mark which is formed on the wafer and is visible on a sample manufacturing machine bench, a defect in a wafer is located directly or indirectly to obtain the detailed location and / or a location range of the defect. The method solves the problem that when the defect is too small, defect locating is difficult due to lack of a useful reference. The method facilitates manufacturing a sample with a defect.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to the method for defect location in a kind of wafer.
Background technology
Defect analysis in wafer is the effective means that improves product yield and improve manufacture craft.General defect analysis all needs to make the wafer sample of defect position, by TEM(Transmission Electron Microscope, transmission electron microscope) with high pressure accelerate electron beam irradiation sample, sample topography is amplified, projected on screen, take a picture, then analyze, therefore, it is important how making the sample that comprises defect accurately.
While making defect sample in prior art, general using Defect Scanning board, carries out Defect Scanning to wafer, obtains wafer defect scan image, and wafer defect scan image can illustrate the defect of crystal column surface existence and the pattern of crystal column surface; Again wafer is written into sample making board, is shown the wafer feature image of overall crystal column surface by sample making board; In conjunction with the crystal column surface feature image of existing wafer defect scan image and the demonstration of sample making board, in crystal column surface feature image, find position the record of defect, to realize the location of defect, by focused ion beam cutting crystal wafer, make the sample that comprises this defect according to the defective locations of record.Concrete, in prior art, conventionally utilize electronics contrast (Passive voltage contrast, PVC) board obtains wafer defect scan image, and carry out sample making by focusing on beam-plasma board, wherein, electronics contrast board can form contrast by crystal column surface current potential difference, utilize the signal to crystal column surface potential state sensitivity, as secondary electron, as the modulation signal of picture tube, thereby obtain wafer defect scan image; In the time carrying out defect location, if flaw size is larger, can be shown by wafer feature image, be written into after sample making board at wafer, according to the wafer shape characteristic showing in wafer feature image, wafer is set up to coordinate system, by coupling wafer defect scan image, can connect the position of directly locating this defect in crystal column surface feature image by coordinate again.
Along with the development of semiconductor technology, the characteristic line breadth of semiconductor device is more and more less, on wafer of the same area, integrated level is more and more higher, the size of defect is also dwindled thereupon, generally be less than the resolution of the Defect Scanning boards such as electronics contrast board due to the resolution of the sample making boards such as focused ion beam board, in the crystal column surface shape appearance figure that the defect that therefore, can show in Defect Scanning figure shows at focused ion beam board, be difficult to show; And, high integration means that in crystal column surface unit are, number of devices increases, the wafer shape characteristic being shown by wafer feature image also becomes complicated, if the wafer shape characteristic that passes through to show in wafer feature image still adopting with prior art is set up coordinate system to wafer, can be subject to complicated wafer shape characteristic and disturb, directly cause sample to prepare.
Summary of the invention
In view of this, the invention provides the method for defect location in a kind of wafer, when undersized with fix the defect, cause location defect position difficulty owing to lacking effective object of reference, and then affect the problem of the making that comprises defect sample.
The technological means that the present invention adopts is as follows: a kind of method of defect location in wafer, comprising:
Steps A: on described wafer, form the first mark, and obtain wafer defect scan image by Defect Scanning board scanning wafer, wherein, described first be marked at wafer defect scan image and the wafer feature image that shown from sample making board in;
Step B: according to described the first mark, the defect in wafer is positioned in described sample making board.
Further, described first be labeled as the temporary marker of disappearing in predetermined time section.
Further, in described steps A, by using electron beam the precalculated position of described wafer to be carried out to the scanning of first scheduled time, to form the first mark on described wafer.
Further, the number of described the first mark is at least one.
Further, the electron beam energy of described formation the first mark is 500ev to 2kev, and electric current is 40nA to 200nA, and described first scheduled time is more than or equal to 120 seconds.
Further, described the first mark comprises the figure for embodying positional information and/or directional information, and in step B, utilize the positional information and/or the directional information that in the figure of described the first mark, embody to realize location, and obtain the particular location of defect and/or the position range at defect place by location.
Preferably, in described step B, be further included in described sample making board and form permanent the second mark according to described the first mark, according to the second mark, the defect in wafer is positioned.
Further, described sample making board is focused ion beam board, utilizes ion beam to carry out etching to form described the second mark to wafer by described focused ion beam board.
Further, described the second mark comprises the figure for embodying positional information and/or directional information, and in step B, utilize the positional information and/or the directional information that in the figure of described the second mark, embody to realize location, and obtain the particular location of defect and/or the position range at defect place by location.
Further, the ion beam energy of described formation the second mark is 30kv, and electric current is 10pA to 30pA.
Adopt the method for defect location in wafer provided by the present invention, directly or indirectly the defect in wafer is positioned by be formed on visible the first mark on sample making board on wafer, to obtain the particular location of defect and/or the position range at defect place, solve in the time that flaw size is too small, owing to lacking effective object of reference and cause the problem of location defect position difficulty, be convenient to make the sample that comprises defect.
Accompanying drawing explanation
Fig. 1 is the method flow diagram of defect location in a kind of wafer of the present invention;
Fig. 2 is the flow chart of a kind of embodiment of defect positioning method in a kind of wafer of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
Technical scheme of the present invention realizes based on following design:
The problem that causes prior art be mainly due to flaw size is too small so that make the defect of wafer on sample making board can not direct visible situation under, position and lack effective object of reference with existing localization method.Therefore, on wafer, form the mark that can clearly show at sample making board and can obtain effective object of reference, in conjunction with the flow process of existing Defect Scanning and defect location, propose following technical scheme:
As shown in Figure 1, the invention provides the method for defect location in a kind of wafer, comprising:
Steps A: on described wafer, form the first mark, and obtain wafer defect scan image by Defect Scanning board scanning wafer, wherein, described first be marked at wafer defect scan image and the wafer feature image that shown from sample making board in;
Step B: according to described the first mark, the defect in wafer is positioned in described sample making board.
Below in conjunction with specific embodiment, technical scheme of the present invention is described in detail.
Embodiment mono-,
First, on wafer, form the first mark, this first be marked at wafer defect scan image and the wafer feature image that shown from sample making board in, and obtain wafer defect scan image by Defect Scanning board; What now, in wafer defect scan image, can clearly show comprises this first mark and wafer defect;
Then, in sample making board, according to the first mark, the defect in wafer is positioned; In the time that wafer is written into sample making board, in the wafer feature image being shown by sample making board, can clearly show this first mark, therefore, can mate wafer defect scintigram, in wafer feature image, carry out the location of defect by the position relationship of the first mark in wafer defect scintigram and this defect.Due to the sample that the comprises defect part wafer that is certain area coverage, therefore, by can determine the particular location of defect or the position range at defect place as the first mark of effective object of reference; Determining after the particular location of defect, use sample making board cutting crystal wafer to form sample, the scope of sample comprises the particular location of this defect; When determining that after the position range at defect place, the scope of sample comprises the position range at this defect place.
The first mark can be that permanent mark can be also the temporary marker of disappearing in predetermined time section, because permanent the first mark has destroyed the structure of crystal column surface semiconductor device, for fear of permanent the first mark, defect is exerted an influence, the present embodiment is preferred, and this first is labeled as the temporary marker of disappearing in predetermined time section; Further, because the electron beam that uses certain energy can produce carbon distribution effect to wafer-scanning, and the vestige that this carbon distribution effect produces can clearly be shown by sample making board, and do not affect the structure of the semiconductor device forming on crystal column surface, therefore, can use electron beam to scan to form the first mark to wafer; Moreover, because existing Defect Scanning board generally adopts electron beam to scan to obtain wafer defect scintigram to wafer for the consideration of resolution and reliability, therefore, for the ease of operation, can be in the time that wafer be written into Defect Scanning board (as electronics contrast board), with the electron beam of certain energy, the precalculated position of wafer is carried out the scanning of first scheduled time, to form the first mark on wafer, as preferred parameter, the energy of this electron beam is 500ev to 2kev, electric current is 40nA to 200nA, and first scheduled time was more than or equal to 120 seconds.
It should be noted that, in preferred scheme, the first mark forming due to the carbon distribution effect that uses electron beam to produce can not affect the structure of crystal column surface device, and carbon distribution effect disappears at certain hour Duan Houhui, and therefore the precalculated position of the first mark can be selected arbitrarily; In the time carrying out defect location according to the first mark, to guarantee that the first mark that this carbon distribution effect forms not yet disappears, still can be visible in sample making board, each parameter when the time that the first mark forming due to carbon distribution effect exists is depended on electron beam scanning, therefore, in this preferred version, do not limit, those skilled in the art can select concrete defect location opportunity as the case may be; Further, in the time analyzing, be subject to the carbon distribution effects of the first mark for fear of sample, can first familiar lacunas scanning machine carry out Defect Scanning and obtain preliminary wafer defect scan image, then change the energy of electron beam, form the first mark in the position scanning that is differing from defect.
In order to facilitate the location of defective locations in step B, on above-mentioned basis, the number of the first mark at least one, the first mark can also comprise the figure for embodying positional information and/or directional information, as an example, the first mark can be a point-like mark, the position range of defect is being labeled as the center of circle with this point-like, in the circular scope that between defective locations and this point-like the first mark, distance is radius, the first mark can be also two directive line segments, defective locations is positioned at the intersection point at two line segment extended line places, also can use and on same straight line, not obtain three the first marks by setting up coordinate system location defect position coordinates etc., those skilled in the art can be according to known scheme, as geometrical relationship or functional relation are set up the corresponding relation between the first mark and defect particular location or defective locations scope, do not enumerate at this.Further, can be according to above-mentioned corresponding relation in step B, utilize the positional information and/or the directional information that in the figure of the first mark, embody to realize location, and obtain the particular location of defect and/or the position range at defect place by location.
Embodiment bis-,
Due to provisional mark, as being marked in predetermined time section, the carbon distribution after electron beam scanning can disappear, and may make sample exceeding after the predetermined regression time section of provisional mark for various restrictions in actual mechanical process, therefore, while comprising defect sample for fear of making, provisional mark disappears, affect the location of defect, propose the present embodiment.
As shown in Figure 2, first, on wafer, form the first provisional mark, this provisional first be marked at wafer defect scan image and the wafer feature image that shown from sample making board in, and obtain wafer defect scan image by Defect Scanning board; What now, in wafer defect scan image, can clearly show comprises the first mark and the wafer defect that this is provisional;
Then, in sample making board, form permanent the second mark according to the first provisional mark, according to the second mark, the defect in wafer is positioned.
Preferred as the present embodiment, sample making board is selected focused ion beam board, utilize ion beam, according to the first provisional mark, wafer is carried out to etching to form the second mark by focused ion beam board, as preferred parameter, the ion beam energy that forms the second mark is 30kv, and electric current is 10pA to 30pA.
It should be noted that, due in the preferred version of the present embodiment, the second mark forms by ion beam etching, and because etching can be destroyed crystal column surface device configuration, therefore, the position of the second mark need to differ from the position of defect; The second mark is at least one, the second mark can comprise the figure for embodying positional information and/or directional information equally, in the time carrying out defect location, utilize the positional information and/or the directional information that in the figure of the second mark, embody to realize location, and obtain the particular location of defect and/or the position range at defect place by location, its position fixing process is identical by the first provisional mark location defect position with specific embodiment, does not repeat them here.
In sum, adopt the method for defect location in wafer provided by the present invention, directly or indirectly the defect in wafer is positioned by be formed on visible the first mark on sample making board on wafer, to obtain the particular location of defect and/or the position range at defect place, solve in the time that flaw size is too small, owing to lacking effective object of reference and cause the problem of location defect position difficulty, be convenient to make the sample that comprises defect.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (10)
1. a method for defect location in wafer, comprising:
Steps A: on described wafer, form the first mark, and obtain wafer defect scan image by Defect Scanning board scanning wafer, wherein, described first be marked at wafer defect scan image and the wafer feature image that shown from sample making board in;
Step B: according to described the first mark, the defect in wafer is positioned in described sample making board.
2. method according to claim 1, is characterized in that, described first is labeled as the temporary marker of disappearing in predetermined time section.
3. method according to claim 2, is characterized in that, in described steps A, by using electron beam the precalculated position of described wafer to be carried out to the scanning of first scheduled time, to form the first mark on described wafer.
4. method according to claim 3, is characterized in that, the number of described the first mark is at least one.
5. according to the method described in claim 3 or 4, it is characterized in that, the electron beam energy of described formation the first mark is 500ev to 2kev, and electric current is 40nA to 200nA, and described first scheduled time is more than or equal to 120 seconds.
6. method according to claim 5, it is characterized in that, described the first mark comprises the figure for embodying positional information and/or directional information, and in step B, utilize the positional information and/or the directional information that in the figure of described the first mark, embody to realize location, and obtain the particular location of defect and/or the position range at defect place by location.
7. method according to claim 6, is characterized in that, is further included in described sample making board and forms permanent the second mark according to described the first mark in described step B, according to the second mark, the defect in wafer is positioned.
8. method according to claim 7, is characterized in that, described sample making board is focused ion beam board, utilizes ion beam to carry out etching to form described the second mark to wafer by described focused ion beam board.
9. method according to claim 8, it is characterized in that, described the second mark comprises the figure for embodying positional information and/or directional information, and in step B, utilize the positional information and/or the directional information that in the figure of described the second mark, embody to realize location, and obtain the particular location of defect and/or the position range at defect place by location.
10. method according to claim 9, is characterized in that, the ion beam energy of described formation the second mark is 30kv, and electric current is 10pA to 30pA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210528649.1A CN103871918A (en) | 2012-12-10 | 2012-12-10 | Method for defect locating in wafer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210528649.1A CN103871918A (en) | 2012-12-10 | 2012-12-10 | Method for defect locating in wafer |
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| CN103871918A true CN103871918A (en) | 2014-06-18 |
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Cited By (9)
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| CN104198247A (en) * | 2014-09-02 | 2014-12-10 | 上海华力微电子有限公司 | Focused ion beam sample preparation method for precisely positioning front-layer defects |
| CN105136545A (en) * | 2015-10-19 | 2015-12-09 | 上海华力微电子有限公司 | Marking method for TEM chip sample |
| CN105352768A (en) * | 2015-09-27 | 2016-02-24 | 上海华力微电子有限公司 | TEM sample positioning method |
| CN104319244B (en) * | 2014-08-13 | 2017-02-01 | 武汉新芯集成电路制造有限公司 | Positioning method of failure center point of chip |
| CN108346592A (en) * | 2018-01-17 | 2018-07-31 | 武汉新芯集成电路制造有限公司 | A kind of method and device of simulation wafer rear defect |
| CN108461371A (en) * | 2018-05-08 | 2018-08-28 | 德淮半导体有限公司 | Electron beam scanning device, defect detecting system and method |
| CN109256342A (en) * | 2018-11-16 | 2019-01-22 | 上海华力微电子有限公司 | A kind of crystal grain defect monitoring method |
| CN109659248A (en) * | 2018-12-19 | 2019-04-19 | 上海华力集成电路制造有限公司 | Method of the defect to graph layer setting accuracy on raising mating plate |
| CN111816582A (en) * | 2020-07-23 | 2020-10-23 | 上海华力微电子有限公司 | Wafer bonding defect position positioning method and manufacturing method of semiconductor device sample |
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| CN109659248A (en) * | 2018-12-19 | 2019-04-19 | 上海华力集成电路制造有限公司 | Method of the defect to graph layer setting accuracy on raising mating plate |
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| CN111816582A (en) * | 2020-07-23 | 2020-10-23 | 上海华力微电子有限公司 | Wafer bonding defect position positioning method and manufacturing method of semiconductor device sample |
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Application publication date: 20140618 |