CN104425297A - Chip failure analysis method and chip failure analysis marker - Google Patents
Chip failure analysis method and chip failure analysis marker Download PDFInfo
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- CN104425297A CN104425297A CN201310365572.5A CN201310365572A CN104425297A CN 104425297 A CN104425297 A CN 104425297A CN 201310365572 A CN201310365572 A CN 201310365572A CN 104425297 A CN104425297 A CN 104425297A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/302—Contactless testing
- G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
- G01R31/311—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation of integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a chip failure analysis method and a chip failure analysis marker. The chip failure analysis method comprises the following steps: providing a chip to be tested and making a first marker in a detect position of the chip under an SEM (Scanning Electron Microscope); and putting the chip in an FIB (Focused Ion Beam), and irradiating the first marker with an electron beam to form an oxide film so as to form a chip failure analysis marker which can be identified under an ion beam. The situation in which a feature point may not be found before hole digging with the use of an FIB is avoided. The operation time is saved, and the reliability is high. Moreover, the accuracy of 30nm can be achieved in the SEM, and the practical demand can be met.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of method for analyzing chip failure and chip failure evaluation of markers.
Background technology
In the manufacture process of integrated circuit, the inefficacy caused due to defect is of all kinds, and in order to understand these defects, and prevented, need to be analyzed these failure modes.
At present, in failure analysis laboratory, mainly comprise and use focused ion beam (Focused Ion Beam, FIB), fixed point mark and cutting analysis are carried out to defective locations.Usually, for the chip that defective locations is known, basic operation process, for put in FIB equipment by chip to be measured, then according to known position, finds characteristic point, carries out mark of digging a hole, afterwards cutting analysis in addition.
But; in actual analysis process; often can run into defective locations do not know or characteristic point be difficult to find situation; at this moment just need first by sweep electron microscope (Scanning ElectronMicroscope; SEM) scanned and taken pictures; record Position Approximate, then puts into FIB by chip to be measured, finds characteristic point according to photo.But but often run into the multiple situation of this process need, and and when using FIB, need to carry out preheating, and the process such as the focusing of electron beam and ion beam at every turn, therefore can time of at substantial.And due to FIB cost high, therefore its limited amount in general factory, nervous when therefore using machine, so above-mentioned situation can be given in practical operation undoubtedly bring very burden.
For this situation, a kind of new method of necessary searching does precise marking to defect, FIB can only be used to carry out marking brought inconvenience to break through.
Summary of the invention
The object of the invention is to, a kind of method for analyzing chip failure and chip failure evaluation of markers are provided, FIB ion beam can be broken through and to dig pit the restriction made marks, thus raise the efficiency.
For solving the problems of the technologies described above, a kind of method for analyzing chip failure, comprising:
Chip to be measured is provided, in the secure execution mode (sem the defective locations of described chip is done the first mark;
Described chip to be measured is positioned in FIB, utilizes the first mark described in electron beam irradiation to form an oxide-film, thus discernible chip failure evaluation of markers under being formed in ion beam.
Optionally, for described method for analyzing chip failure, the method in the secure execution mode (sem defective locations of described chip being done the first mark comprises:
Utilize the electron-beam sustainer of SEM to irradiate and be more than or equal to 20s to form carbon distribution.
Optionally, for described method for analyzing chip failure, adjusting voltage during described electron beam irradiation is 1kV-3kV.
Optionally, for described method for analyzing chip failure, the electron beam mark precision of described SEM is 30nm-100nm.
Optionally, for described method for analyzing chip failure, when described in described electron beam irradiation, the first mark is to form an oxide-film, the voltage of FIB is 1-3kV, and electron beam current is 1-2nA, and irradiation time is for being greater than 90s.
Optionally, for described method for analyzing chip failure, described in chip to be measured is provided, also comprise before in the secure execution mode (sem the defective locations of described chip being done the first mark:
Described chip to be measured is placed in SEM, utilizes electron beam random scan until find defective locations.
Optionally, for described method for analyzing chip failure, described in be formed in ion beam under after discernible chip failure evaluation of markers, also comprise:
FIB is utilized to carry out cutting analysis.
The invention provides a kind of chip failure evaluation of markers, the fault location of described chip failure evaluation of markers on chip, wherein, described chip failure evaluation of markers is an oxide-film, and described oxide-film is identifiable design under ion beam.
Optionally, for described chip failure evaluation of markers, the width of described oxide-film is 30nm-100nm.
Compared with prior art, method for analyzing chip failure provided by the invention and chip failure evaluation of markers, SEM is adopted to form the first mark at defective locations, the electron beam of FIB is utilized to make the first mark become an oxide-film afterwards, this oxide-film by the ion beam identification of SEM, thus just can become chip failure evaluation of markers.Which avoid utilize FIB ion beam dig a hole before the searching that may occur less than the situation of characteristic point, save the operating time, reliability is high, and can reach the precision of 30nm in SEM, can practical requirement.
Accompanying drawing explanation
Fig. 1 is the flow chart of one embodiment of the invention chips failure analysis method;
Fig. 2-Fig. 4 is the schematic diagram of the chip structure in one embodiment of the invention chips failure analysis method;
Fig. 5 is the display photo of chip failure evaluation of markers under FIB ion beam that the method for analyzing chip failure of the embodiment of the present invention is formed.
Embodiment
Below in conjunction with schematic diagram, method for analyzing chip failure of the present invention and chip failure evaluation of markers are described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, provides a kind of method for analyzing chip failure, comprising:
Step S101, provides chip to be measured, in the secure execution mode (sem the defective locations of described chip is done the first mark;
Step S102, is positioned in FIB by described chip to be measured, utilizes the first mark described in electron beam irradiation to form an oxide-film, thus discernible chip failure evaluation of markers under being formed in ion beam.
Based on above-mentioned thought, the present invention can obtain a kind of chip failure evaluation of markers, the fault location of described chip failure evaluation of markers on chip, and wherein, described chip failure evaluation of markers is an oxide-film, and described oxide-film is identifiable design under ion beam.
The present invention forms the first mark by adopting SEM at defective locations, and utilize the electron beam of FIB to make the first mark become an oxide-film afterwards, this oxide-film by the ion beam identification of SEM, thus just can become chip failure evaluation of markers.Which avoid utilize FIB ion beam dig a hole before the searching that may occur less than the situation of characteristic point, save the operating time, reliability is high, and can reach the precision of 30nm in SEM, can practical requirement.
Below enumerate the preferred embodiment of described method for analyzing chip failure and chip failure evaluation of markers, to clearly demonstrate content of the present invention, will be clear that, content of the present invention is not restricted to following examples, and other improvement by the routine techniques means of those of ordinary skill in the art are also within thought range of the present invention.
Incorporated by reference to Fig. 1 and Fig. 2-Fig. 4, illustrate method for analyzing chip failure of the present invention.Wherein, Fig. 1 is the flow chart of one embodiment of the invention chips failure analysis method, and Fig. 2-Fig. 4 is the process schematic in one embodiment of the invention chips failure analysis method.
First, as shown in Figure 1, carry out step S101, chip to be measured is provided, in the secure execution mode (sem the defective locations of described chip is done the first mark.Before this step of execution, also need to find defective locations in the secure execution mode (sem, preferably, adopt SEM random scan to search out defect position as far as possible fast.Certainly, according to different situations, for the chip to be measured of known defect position, directly this step can be carried out.
Concrete, after searching out defective locations, utilize SEM to do the first mark, consider when electron beam scanning overlong time, carbon distribution can be formed on sample, thus and non-scanning area formation color contrasts.Therefore, described in do the first mark and be and make electron beam irradiation target location, continues for some time, be preferably more than 20s, thus the carbon distribution formed is described first mark.As shown in Figure 2, region 10 is the region comprising the defectiveness position searched out, and adopts electron beam irradiation in target location, forms carbon distribution, i.e. the first mark 11.Preferably, in order to make the formation of carbon distribution easier, also make the carbon distribution formed be convenient to identify, make electron beam be in big current, the pattern of low-voltage, such as, the voltage adopted in the present embodiment is 1kV-3kV.
The operational requirements of SEM is lower, and selects rapidly, and compare to adopt FIB or first utilize SEM to find and take pictures, the rear operation utilizing FIB to mark, improves in time with in accuracy greatly.
In the present embodiment, in order to reach preferably resolving effect, making the electron beam of described SEM mark precision is 30nm-100nm, and namely the width of the first mark 11 is 30nm-100nm, is 30nm in the present embodiment.Be understandable that, during the restriction of the present invention to this precision, consider that the first mark using SEM to do can mate in prior art the mark utilizing FIB to do, thus make to save the time and also can reach preferably effect, meet actual needs.Certainly, according to actual needs, and the levels of precision of SEM, described electron beam mark precision can be less than 30nm, and suitably in conjunction with different enlargement ratios and scan box, this is also within thought of the present invention.
Then, carry out step S102, described chip to be measured is positioned in FIB, utilize the reflector 20 in FIB to form the first mark 11 described in electron beam irradiation to form an oxide-film 12, thus discernible chip failure evaluation of markers under being formed in ion beam, as shown in Figure 3.This considers that the carbon distribution adopting SEM to be formed is thinner, if under being directly positioned over the ion beam of FIB, ion beam is difficult to identify, therefore adopts the electron beam treatment of FIB first to mark 11.Fig. 3 is depicted as and utilizes the electron beam of FIB to carry out the process of irradiating, in the process, preferably, the voltage of described FIB is 1-3kV, and electron beam current is 1-2nA, irradiation time is for being greater than 90s, in the present embodiment, the voltage adopting FIB is 2kV, and electron beam current is 1.4nA, time is two minutes, thus makes the first mark 11 gradually become oxide-film 12.As shown in Figure 4, after the electron beam irradiation of FIB, define the chip failure evaluation of markers 13 that material is oxide-film.
Through said process, chip failure evaluation of markers of the present invention can be obtained, the fault location of described chip failure evaluation of markers on chip, concrete, described chip failure evaluation of markers is an oxide-film, and described oxide-film is identifiable design under ion beam, preferably, the width of described oxide-film is 30nm-100nm, to adapt to practical operation needs.
Afterwards, adopt FIB to carry out cutting analysis, method of the prior art can be taked to carry out, and the present invention is not described further this.
Please refer to Fig. 5, its the display photo of chip failure evaluation of markers under FIB ion beam formed for adopting the method for analyzing chip failure of the embodiment of the present invention, can significantly find out, there is a white bright list structure in Fig. 5 central authorities, this is chip failure evaluation of markers, the Be very effective of this mark, can reach and utilize FIB ion beam to dig a hole the identical effect of formed mark.
Method for analyzing chip failure provided by the invention and chip failure evaluation of markers, SEM is adopted to form the first mark at defective locations, the electron beam of FIB is utilized to make the first mark become an oxide-film afterwards, this oxide-film by the ion beam identification of SEM, thus just can become chip failure evaluation of markers.Which avoid utilize FIB ion beam dig a hole before the searching that may occur less than the situation of characteristic point, save the operating time, reliability is high, and can reach the precision of 30nm in SEM, can practical requirement.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (9)
1. a method for analyzing chip failure, comprising:
Chip to be measured is provided, in the secure execution mode (sem the defective locations of described chip is done the first mark;
Described chip to be measured is positioned in FIB, utilizes the first mark described in electron beam irradiation to form an oxide-film, thus discernible chip failure evaluation of markers under being formed in ion beam.
2. method for analyzing chip failure as claimed in claim 1, it is characterized in that, the method in the secure execution mode (sem defective locations of described chip being done the first mark comprises:
Utilize the electron-beam sustainer of SEM to irradiate and be more than or equal to 20s to form carbon distribution.
3. method for analyzing chip failure as claimed in claim 2, is characterized in that, adjusting voltage during described electron beam irradiation is 1kV-3kV.
4. method for analyzing chip failure as claimed in claim 2, is characterized in that, the electron beam mark precision of described SEM is 30nm-100nm.
5. method for analyzing chip failure as claimed in claim 1, is characterized in that, when described in described electron beam irradiation, the first mark is to form an oxide-film, the voltage of FIB is 1-3kV, and electron beam current is 1-2nA, and irradiation time is for being greater than 90s.
6. method for analyzing chip failure as claimed in claim 1, is characterized in that, described in chip to be measured is provided, also comprise before in the secure execution mode (sem the defective locations of described chip being done the first mark:
Described chip to be measured is placed in SEM, utilizes electron beam random scan until find defective locations.
7. method for analyzing chip failure as claimed in claim 1, is characterized in that, described in be formed in ion beam under after discernible chip failure evaluation of markers, also comprise:
FIB is utilized to carry out cutting analysis.
8. a chip failure evaluation of markers, the fault location of described chip failure evaluation of markers on chip, is characterized in that, described chip failure evaluation of markers is an oxide-film, and described oxide-film is identifiable design under ion beam.
9. chip failure evaluation of markers as claimed in claim 8, it is characterized in that, the width of described oxide-film is 30nm-100nm.
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| CN201310365572.5A CN104425297B (en) | 2013-08-20 | 2013-08-20 | Method for analyzing chip failure and chip failure evaluation of markers |
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| CN201310365572.5A CN104425297B (en) | 2013-08-20 | 2013-08-20 | Method for analyzing chip failure and chip failure evaluation of markers |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105136545A (en) * | 2015-10-19 | 2015-12-09 | 上海华力微电子有限公司 | Marking method for TEM chip sample |
| JP2018100953A (en) * | 2016-12-16 | 2018-06-28 | 住友金属鉱山株式会社 | Method for marking and method for preparing analyzing sample |
| CN110767561A (en) * | 2019-09-09 | 2020-02-07 | 长江存储科技有限责任公司 | Failure analysis method and structure of stacked packaging structure |
| CN115274489A (en) * | 2022-09-29 | 2022-11-01 | 合肥晶合集成电路股份有限公司 | Failure analysis method and system for chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030098416A1 (en) * | 2001-11-26 | 2003-05-29 | Dror Shemesh | System and method for directing a miller |
| US20050194536A1 (en) * | 2002-11-06 | 2005-09-08 | Masanari Furiki | Charged particle beam apparatus |
| CN102680742A (en) * | 2012-05-28 | 2012-09-19 | 上海华力微电子有限公司 | Method for labeling atomic force nano-probe sample and method for manufacturing integrated circuit |
-
2013
- 2013-08-20 CN CN201310365572.5A patent/CN104425297B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030098416A1 (en) * | 2001-11-26 | 2003-05-29 | Dror Shemesh | System and method for directing a miller |
| US20050194536A1 (en) * | 2002-11-06 | 2005-09-08 | Masanari Furiki | Charged particle beam apparatus |
| CN102680742A (en) * | 2012-05-28 | 2012-09-19 | 上海华力微电子有限公司 | Method for labeling atomic force nano-probe sample and method for manufacturing integrated circuit |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105136545A (en) * | 2015-10-19 | 2015-12-09 | 上海华力微电子有限公司 | Marking method for TEM chip sample |
| CN105136545B (en) * | 2015-10-19 | 2019-01-04 | 上海华力微电子有限公司 | A kind of labeling method of TEM chip sample |
| JP2018100953A (en) * | 2016-12-16 | 2018-06-28 | 住友金属鉱山株式会社 | Method for marking and method for preparing analyzing sample |
| CN110767561A (en) * | 2019-09-09 | 2020-02-07 | 长江存储科技有限责任公司 | Failure analysis method and structure of stacked packaging structure |
| CN110767561B (en) * | 2019-09-09 | 2021-09-17 | 长江存储科技有限责任公司 | Failure analysis method and structure of stacked packaging structure |
| CN115274489A (en) * | 2022-09-29 | 2022-11-01 | 合肥晶合集成电路股份有限公司 | Failure analysis method and system for chip |
| CN115274489B (en) * | 2022-09-29 | 2022-12-09 | 合肥晶合集成电路股份有限公司 | Failure analysis method and system for chip |
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