CN103308840A - Wafer acceptance test method - Google Patents
Wafer acceptance test method Download PDFInfo
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- CN103308840A CN103308840A CN2013101963168A CN201310196316A CN103308840A CN 103308840 A CN103308840 A CN 103308840A CN 2013101963168 A CN2013101963168 A CN 2013101963168A CN 201310196316 A CN201310196316 A CN 201310196316A CN 103308840 A CN103308840 A CN 103308840A
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Abstract
The invention provides a wafer acceptance test method. The method comprises the following steps of before performing a WAT (Wafer Acceptance Test) on a wafer by a testing machine, first, selecting a test voltage scanning section; and then, testing the wafer by using the testing machine which can record all electric parameter values in the test voltage scanning section, therefore, an electric parameter curve can be drawn by all electric parameter values in the section so as to further obtain a special electric parameter numerical value by the electric parameter curve. After test by the testing machine, when feedback electric parameters are inaccurate or the electric parameters cannot be fed back, a second test is not performed manually, so that the time and labor force are saved, and the detection efficiency is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, but relate in particular to a kind of wafer acceptance test method.
Background technology
Usually wafer is after creating, before entering follow-up cutting encapsulation, need to choose test to it, by the unit of selection test with minimum, be crystal granules sorted, with defectiveness or do not possess the upper mark of crystal grain mark of normal operation ability, and when cutting crystal wafer, these crystal grain filtered out and abandon, avoid bad crystal grain to enter encapsulation and successive process, cause for no reason waste of cost.But the selection test generally includes wafer acceptance test (WAT, Wafer Acceptance Test) and circuit is surveyed (CP, Circuit Probe).
The WAT detecting step is finished after wafer produces in earlier stage, and before wafer cutting and encapsulation, in case the mistake in being used for guaranteeing occurring in earlier stage being produced by wafer and situation that crystal grain can't be worked can detect it by WAT, in advance to save cost.Because in the project that WAT tests; many destroyed tests have been comprised; if directly apply on the crystal grain; must cause the destruction to crystal grain; the yield when thereby impact is dispatched from the factory; therefore usually can be when making crystal grain, in the space of each crystal grain and intergranule, namely Cutting Road (scribe line) is upward made test structure (test key).The WAT test is exactly by the detection to these test structures, thereby whether the serviceability of inferring element near its crystal grain is intact.Usually said WAT test parameter refers to, these elements is carried out electrical property measure resulting electrical parameter data, such as connectivity test, threshold voltage, drain saturation current etc.
Concrete, during On-Wafer Measurement WAT, some test structures of by tester table crystal column surface being chosen first apply test voltage, thereby are drawn the electrical parameter value of this test structure by tester table, and feed back the electrical parameter value by tester table.Yet, when wafer is carrying out WAT when detecting, often (such as the tester table warning etc.) can cause some of them electrical parameter value to drift about because external cause, i.e. inaccurate the or electrical parameter value that can't feedback test arrives of the electrical parameter value fed back after test of tester table.When problems occured, prior art detected by manually wafer being carried out secondary WAT usually, draw accurately electrical parameter value, and so very consuming time and consumption power is unfavorable for improving detection efficiency.
Summary of the invention
But the object of the present invention is to provide a kind of wafer acceptance test method to draw electrical parameter through one-shot measurement, avoided secondary detection, improve detection efficiency.
To achieve these goals, but the present invention proposes a kind of wafer acceptance test method, comprising:
Select a plurality of measuring points to be checked at crystal column surface;
In tester table, set the test voltage sweep interval of each measuring point to be checked;
The use test board is tested some test voltages in each measuring point input test voltage scanning to be checked interval;
The use test board is collected the electrical parameter of corresponding described measuring point to be checked under each test voltage, and is depicted as the electrical parameter curve;
Draw the numerical value of the electrical parameter to be detected of each measuring point to be checked according to described electrical parameter curve.
Further, described wafer is provided with a plurality of Cutting Roads.
Further, described measuring point to be checked is arranged on the described Cutting Road.
Further, described measuring point to be checked is 5.
Further, described measuring point to be checked is evenly distributed on the surface of described wafer.
Further, described electrical parameter comprises voltage, resistance and electric current.
Further, described voltage comprises cut-in voltage, saturation voltage and voltage breakdown.
Further, described electric current comprises saturation current, substrate leakage current and close current.
Further, described test voltage sweep interval is 0V to 5V.
Compared with prior art, beneficial effect major embodiment of the present invention in: when tester table is tested wafer, because tester table has recorded all electrical parameter values in the test voltage sweep interval, therefore can draw out the electrical parameter curve by electrical parameter values all in this interval, and then can draw specific electrical parameter numerical value by the electrical parameter curve, the electrical parameter that is feeding back after test when tester table is inaccurate or can't feed back electrical parameter the time, need not manually to carry out the second test, thereby saved time and labour, improved detection efficiency.
Description of drawings
But Fig. 1 is the process flow diagram of wafer acceptance test method in one embodiment of the invention;
Fig. 2 is the curve map of cut-in voltage and drain terminal electric current in the embodiment of the invention one;
Fig. 3 is the curve map of the voltage breakdown between source-drain electrode and drain terminal electric current in the embodiment of the invention one.
Embodiment
Below in conjunction with the drawings and specific embodiments but the wafer acceptance test method that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-accurately ratio, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Embodiment one
Please refer to Fig. 1, but in the wafer acceptance test method that the present embodiment proposes, comprising:
Step S100: select a plurality of measuring points to be checked at crystal column surface; Wherein, described wafer is provided with a plurality of Cutting Roads, and described measuring point to be checked all is arranged on the described Cutting Road; Described measuring point to be checked is 5, is evenly distributed on the surface of described wafer;
Step S200: the test voltage sweep interval of in tester table, setting each measuring point to be checked; Described test voltage sweep interval is 0V to 5V, because the operating voltage of device is less than 5V usually, therefore selecting the test voltage sweep interval is the electrical parameter values such as inefficacy voltage that 0V to 5V is convenient to obtain device; Described test voltage is that test WAT is added into the voltage on the test structure (test key);
Step S300: the use test board is tested some test voltages in each measuring point input test voltage scanning to be checked interval;
Step S400: the use test board is collected the electrical parameter of corresponding described measuring point to be checked under each test voltage, and is depicted as the electrical parameter curve; Described electrical parameter comprises voltage, resistance and electric current; Wherein, described voltage comprises cut-in voltage, saturation voltage and voltage breakdown; Described electric current comprises saturation current, substrate leakage current and close current;
Step S500: the numerical value that draws the electrical parameter to be detected of each measuring point to be checked according to described electrical parameter curve.
Before the use test board is tested the curve of collecting electrical parameter to wafer, first according to the difference that will test electrical parameter, the form of different test conditions according to instruction inputed in the described tester table, thereby draw the curve that to test electrical parameter; In the present embodiment, the use test board tests and collects the curve of cut-in voltage Vtlin to wafer, and the test voltage sweep interval of selection is 0 to 1.4V, please refer to Fig. 2;
Can observe the situation of change that test voltage is all drain terminal electric current I in 0 to 1.4V the sweep interval by the curve of cut-in voltage Vtlin, and curve returns out and reaches target drain terminal electric current I thus
TargetThe time the magnitude of voltage of cut-in voltage Vtlin, that is to say, in the present embodiment, electrical parameter to be detected is that electric current is at target drain terminal I
TargetWhen lower, the magnitude of voltage of cut-in voltage Vtlin; When tester table in test target drain terminal electric current I
TargetIn the time of can't returning cut-in voltage Vtlin or tester table in test the time warning has occured, then can draw by the curve of cut-in voltage Vtlin the magnitude of voltage of cut-in voltage Vtlin, by shown in Figure 2, when target drain terminal electric current I
TargetDuring for 1.00E-6A, the magnitude of voltage of described cut-in voltage Vtlin is 0.8V.
Embodiment two
But identical in wafer acceptance test method and the step among the embodiment one that the present embodiment proposes, the implementation step please refer to embodiment one, again repeats no more.
In the present embodiment, the use test board tests and collects the curve of the voltage breakdown Bvds between source-drain electrode to wafer, please refer to Fig. 3;
Can be observed the situation of change of voltage breakdown Bvds by the curve of the voltage breakdown Bvds between source-drain electrode, and curve returns out the magnitude of voltage of the voltage breakdown Bvds when reaching target drain terminal electric current I ds thus, that is to say, in the present embodiment, described electrical parameter to be detected is the magnitude of voltage of the voltage breakdown Bvds of target current when being Ids; When tester table when test target drain terminal electric current I ds can't return voltage breakdown Bvds or tester table in test the time warning has occured, then can draw by the curve of the voltage breakdown Bvds between source-drain electrode the magnitude of voltage of voltage breakdown Bvds.
To sum up, but in the wafer acceptance test method that the embodiment of the invention provides, when tester table is tested wafer, because tester table has recorded all electrical parameter values in the test voltage sweep interval, therefore can draw out the electrical parameter curve by electrical parameter values all in this interval, and then can draw specific electrical parameter numerical value by the electrical parameter curve, the electrical parameter that is feeding back after test when tester table is inaccurate or can't feed back electrical parameter the time, need not manually to carry out the second test, thereby saved time and labour, improved detection efficiency.
Above-mentioned only is the preferred embodiments of the present invention, the present invention is not played any restriction.Any person of ordinary skill in the field; in the scope that does not break away from technical scheme of the present invention; technical scheme and technology contents that the present invention discloses are made any type of changes such as replacement or modification that are equal to; all belong to the content that does not break away from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (9)
1. but wafer acceptance test method comprises:
Select a plurality of measuring points to be checked at crystal column surface;
In tester table, set the test voltage sweep interval of each measuring point to be checked;
The use test board is tested some test voltages in each measuring point input test voltage scanning to be checked interval;
The use test board is collected the electrical parameter of corresponding described measuring point to be checked under each test voltage, and is depicted as the electrical parameter curve;
Draw the numerical value of the electrical parameter to be detected of each measuring point to be checked according to described electrical parameter curve.
2. but wafer acceptance test method as claimed in claim 1 is characterized in that, described wafer is provided with a plurality of Cutting Roads.
3. but wafer acceptance test method as claimed in claim 2 is characterized in that, described measuring point to be checked is arranged on the described Cutting Road.
4. but wafer acceptance test method as claimed in claim 3 is characterized in that, described measuring point to be checked is 5.
5. but wafer acceptance test method as claimed in claim 4 is characterized in that, described measuring point to be checked is evenly distributed on the surface of described wafer.
6. but wafer acceptance test method as claimed in claim 1 is characterized in that, described electrical parameter comprises voltage, resistance and electric current.
7. but wafer acceptance test method as claimed in claim 6 is characterized in that, described voltage comprises cut-in voltage, saturation voltage and voltage breakdown.
8. but wafer acceptance test method as claimed in claim 6 is characterized in that, described electric current comprises saturation current, substrate leakage current and close current.
9. but wafer acceptance test method as claimed in claim 1 is characterized in that, described test voltage sweep interval is 0V to 5V.
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| CN201310196316.8A CN103308840B (en) | 2013-05-23 | 2013-05-23 | Wafer acceptance test method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104049197A (en) * | 2014-06-24 | 2014-09-17 | 上海集成电路研发中心有限公司 | Wafer acceptance test system and method |
| CN104900556A (en) * | 2015-04-30 | 2015-09-09 | 上海华力微电子有限公司 | Method for online monitoring of integrity of gate oxide |
| CN107480904A (en) * | 2017-08-24 | 2017-12-15 | 成都海威华芯科技有限公司 | A kind of compound semiconductor critical defect analysis system and analysis method |
| CN111312608A (en) * | 2020-02-25 | 2020-06-19 | 上海华虹宏力半导体制造有限公司 | Wafer parameter trimming method |
| CN113690153A (en) * | 2021-08-10 | 2021-11-23 | 深圳市华星光电半导体显示技术有限公司 | Method for preventing ESD from damaging TFT, preparation method of TFT and display panel |
| TWI822210B (en) * | 2022-07-28 | 2023-11-11 | 力晶積成電子製造股份有限公司 | Method for identifying abnormal distribution and electronic apparatus |
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| CN104900556A (en) * | 2015-04-30 | 2015-09-09 | 上海华力微电子有限公司 | Method for online monitoring of integrity of gate oxide |
| CN107480904A (en) * | 2017-08-24 | 2017-12-15 | 成都海威华芯科技有限公司 | A kind of compound semiconductor critical defect analysis system and analysis method |
| CN107480904B (en) * | 2017-08-24 | 2020-11-24 | 成都海威华芯科技有限公司 | Compound semiconductor fatal defect analysis system and analysis method |
| CN111312608A (en) * | 2020-02-25 | 2020-06-19 | 上海华虹宏力半导体制造有限公司 | Wafer parameter trimming method |
| CN111312608B (en) * | 2020-02-25 | 2022-09-02 | 上海华虹宏力半导体制造有限公司 | Method for trimming wafer parameters |
| CN113690153A (en) * | 2021-08-10 | 2021-11-23 | 深圳市华星光电半导体显示技术有限公司 | Method for preventing ESD from damaging TFT, preparation method of TFT and display panel |
| CN113690153B (en) * | 2021-08-10 | 2023-10-31 | 深圳市华星光电半导体显示技术有限公司 | Method for preventing ESD from damaging TFT and preparation method of TFT |
| TWI822210B (en) * | 2022-07-28 | 2023-11-11 | 力晶積成電子製造股份有限公司 | Method for identifying abnormal distribution and electronic apparatus |
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