CN103871861A - Method for improving uniformity of large-size silicon wafer device performance - Google Patents
Method for improving uniformity of large-size silicon wafer device performance Download PDFInfo
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- CN103871861A CN103871861A CN201410110077.4A CN201410110077A CN103871861A CN 103871861 A CN103871861 A CN 103871861A CN 201410110077 A CN201410110077 A CN 201410110077A CN 103871861 A CN103871861 A CN 103871861A
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- gate dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
Abstract
The invention provides a method for improving the uniformity of large-size silicon wafer device performance. After a first side wall is formed, due to the reasons mentioned in the prior art, the thicknesses of gate dielectric layers are different in different areas, chemical acid liquor is adopted to completely remove the gate dielectric layers on the two sides of a gate electrode, and then an in-situ moisture growth technology is used for forming a gate dielectric layer with the consistent thickness again on the surface of a semiconductor substrate. Due to the fact that the gate dielectric layer formed through the in-situ moisture growth technology is consistent in thickness in different density areas, the influence of the gate dielectric layers of different thicknesses on the follow-up light doping drain technology injection can be avoided, and then the electric property uniformity of the formed device can be ensured.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of inhomogeneity method of large-sized silicon wafers device performance that improves.
Background technology
In current semi-conductor industry, 12 inches of silicon chip manufacturing process have become main flow, and 18 inches of silicon chip manufactures are simultaneously also in positive development.In large-sized silicon wafers is manufactured, the uniformity of zones of different device performance is one and considers silicon chip and be worth important index.Due to the density difference of zones of different device, for example the device density in SRAM region is much larger than the device density of WAT test zone, and different components density just causes uniformity to be difficult to control.
In fabrication of semiconductor device, be subject to the restriction of the uniformity of processing performance own, there is notable difference in the cmos device electric property of the same design of large-sized silicon wafers zones of different.This species diversity will cause the electrical health degree of full wafer silicon chip entirety to decline, and also can exert an influence to the yield of silicon chip central area and fringe region simultaneously, has directly reduced the economic worth of finished product silicon chip.Semiconductor manufacture at present, improving the electrical uniformity of silicon chip is mainly to rely on the manufacture uniformity that promotes a certain technique so as to improving the electrical uniformity of silicon chip.
After 0.18 μ m technique, lightly doped drain (Lightly Doped Drain) injection technology is widely used.The introducing of lightly doped drain injection technology, can improve hot carrier's effect greatly, also directly has influence on the electric property of cmos device simultaneously.Lightly doped drain injection technology is the carrying out after first side wall.
Please refer to Fig. 1, Fig. 1 forms the structural representation after first side wall in prior art, described structure comprises Semiconductor substrate 10, in Semiconductor substrate, form gate oxide 20, on described gate oxide 20, form grid 30, for the ease of distinguishing, the oxide layer that is positioned at described grid 30 both sides source drain region is referred to as to barrier oxide layer 21, then in the both sides of described grid 30 and barrier oxide layer 21, form first side wall layer, then described first side wall layer is carried out to dry etching, removal is positioned at the first side wall layer of described barrier oxide layer 21, only retain the first side wall 40 that is positioned at described grid 30 both sides.
Due in first side wall 40 forming processes, because dry etch process is also different to the etching selection ratio of different components density, for example higher to the large region etch rate of density, the region etch rate little to density is lower, therefore, can make the barrier oxide layer 21 of source-drain area in zones of different thickness difference, the thickness that is for example positioned at SRAM district barrier oxide layer 21 can be less than the thickness that is positioned at WAT district barrier oxide layer 21, and thickness difference is conventionally at 5A～25A.And due to Light-Doped Drain Technology Implantation Energy little (normally 5K is following), the different-thickness of source-drain area barrier oxide layer 21 will exert an influence to the degree of depth of light dope Implantation, this there are differences the electric property that directly causes the identical cmos device of zones of different, therefore causes the electrical uniformity decreases of silicon chip.
Therefore, how to address the above problem, just become those skilled in the art and be badly in need of the problem of considering.
Summary of the invention
The object of the present invention is to provide a kind of inhomogeneity method of large-sized silicon wafers device performance that improves, can form in zones of different the barrier oxide layer of consistency of thickness, improve the electrical uniformity of silicon chip.
To achieve these goals, the present invention proposes a kind of inhomogeneity method of large-sized silicon wafers device performance that improves, comprise step:
Semiconductor substrate is provided, on described semiconductor substrate surface, is formed with gate dielectric layer, is positioned at the grid on described gate dielectric layer surface and is positioned at the first side wall of described grid both sides;
Use chemical acid solution to remove the gate dielectric layer that is positioned at grid both sides and semiconductor substrate surface, expose Semiconductor substrate;
Use original position steam growth technique again to form gate dielectric layer at semiconductor substrate surface.
Further, the material of described gate dielectric layer is silicon dioxide.
Further, described chemical acid solution is hydrofluoric acid.
Further, the concentration ratio of described hydrofluoric acid is HF:H
2o=1:200.
Further, the range of reaction temperature of described original position steam growth technique is 900 DEG C～1100 DEG C.
Further, the reaction pressure scope of described original position steam growth technique is 5Torr～20Torr.
Further, the reacting gas of described original position steam growth technique is oxygen and hydrogen.
Further, the range of flow of described oxygen is 10slm～30slm, and the range of flow of described hydrogen is 1slm～5slm.
Further, the reaction time range of described original position steam growth technique is 10s～40s.
Further, using original position steam growth technique after semiconductor substrate surface forms gate dielectric layer again, the Semiconductor substrate of described grid both sides is carried out to Light-Doped Drain Technology injection, form device.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: after forming first side wall, gate dielectric layer can reason as mentioned in background technology cause there is difference at the thickness of zones of different, adopt chemical acid solution all to remove the gate dielectric layer of grid both sides, then use original position steam growth technique again to form the gate dielectric layer of consistency of thickness at semiconductor substrate surface, because the gate dielectric layer that original position steam growth technique forms is also consistent at the thickness in different densities region, the impact that can avoid different-thickness gate dielectric layer to inject follow-up Light-Doped Drain Technology, and then can ensure the electrical uniformity of device forming.
Brief description of the drawings
Fig. 1 forms the structural representation after first side wall in prior art;
Fig. 2 is the flow chart that improves the inhomogeneity method of large-sized silicon wafers device performance in one embodiment of the invention;
Fig. 3 to figure Fig. 5 is the generalized section improving in one embodiment of the invention in the inhomogeneity procedure of large-sized silicon wafers device performance.
Embodiment
Below in conjunction with schematic diagram, the inhomogeneity method of raising large-sized silicon wafers device performance of the present invention is described in more detail, the preferred embodiments of the present invention are wherein represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with way of example, the present invention is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, in the present embodiment, proposed a kind of inhomogeneity method of raising large-sized silicon wafers device performance, comprise step:
S100: Semiconductor substrate 100 is provided, and described Semiconductor substrate is formed with gate dielectric layer 200 on 100 surfaces, is positioned at the grid 300 on described gate dielectric layer 200 surfaces and is positioned at the first side wall 400 of described grid 300 both sides, as shown in Figure 3;
In this step, described Semiconductor substrate 100 is silicon substrate, wherein be formed with well region and shallow trench isolation from (scheming not shown), surface in Semiconductor substrate 100 forms gate dielectric layer 200, the material of described gate dielectric layer 200 is silicon dioxide, can adopt chemical vapour deposition (CVD) or thermal oxidation method to form; Surface at described gate dielectric layer 200 forms grid 300, then on the surface of described gate dielectric layer 200 and the both sides of grid 300 form first side wall layer, then adopt dry etching to remove the first side wall layer that is positioned at described gate dielectric layer 200 surfaces, only retain the first side wall layer that is positioned at described grid 300 both sides, form first side wall 400.
S200: use chemical acid solution to remove the gate dielectric layer 200 that is positioned at grid 300 both sides and Semiconductor substrate 100 surfaces, expose Semiconductor substrate 100, as shown in Figure 4;
But mentioned as background technology, dry etching can cause the thickness difference of gate dielectric layer 200 in different densities region, and then affect follow-up Light-Doped Drain Technology and inject, therefore in step S200, adopt chemical acid solution to remove the gate dielectric layer 200 that is positioned at grid 300 both sides and Semiconductor substrate 100 surfaces; In the present embodiment, described chemical acid solution is hydrofluoric acid, and its concentration ratio is HF:H
2o=1:200.
S300: use original position steam growth technique again to form gate dielectric layer at semiconductor substrate surface, as shown in Figure 5.
In step S300, use original position steam growth technique (In Suit Steam Generation, ISSG) again form gate dielectric layer, referred to here as barrier oxide layer 210, because original position steam growth technique can be consistent at the thickness of the barrier oxide layer 210 of different densities region formation, therefore can avoid the problem of background technology; In the present embodiment, the reacting gas that described original position steam growth technique adopts is oxygen and hydrogen, and the range of flow of described oxygen is 10slm～30slm, for example, be 20slm; The range of flow of described hydrogen is 1slm～5slm; The range of reaction temperature of described original position steam growth technique is 900 DEG C～1100 DEG C, for example, be 1000 DEG C, and reaction pressure scope is 5Torr～20Torr, for example, be 10Torr.
After again forming barrier oxide layer 210, carry out subsequent technique, the Semiconductor substrate 100 of described grid 300 both sides is carried out to Light-Doped Drain Technology injection, form device.
To sum up, in the inhomogeneity method of raising large-sized silicon wafers device performance providing in the embodiment of the present invention, after forming first side wall, gate dielectric layer can reason as mentioned in background technology cause there is difference at the thickness of zones of different, adopt chemical acid solution all to remove the gate dielectric layer of grid both sides, then use original position steam growth technique again to form the gate dielectric layer of consistency of thickness at semiconductor substrate surface, because the gate dielectric layer that original position steam growth technique forms is also consistent at the thickness in different densities region, the impact that can avoid different-thickness gate dielectric layer to inject follow-up Light-Doped Drain Technology, and then can ensure the electrical uniformity of device forming.
Above are only the preferred embodiments of the present invention, the present invention is not played to any restriction.Any person of ordinary skill in the field; not departing from the scope of technical scheme of the present invention; the technical scheme that the present invention is disclosed and technology contents make any type of variations such as replacement or amendment that are equal to; all belong to the content that does not depart from technical scheme of the present invention, within still belonging to protection scope of the present invention.
Claims (10)
1. improve the inhomogeneity method of large-sized silicon wafers device performance, comprise step:
Semiconductor substrate is provided, on described semiconductor substrate surface, is formed with gate dielectric layer, is positioned at the grid on described gate dielectric layer surface and is positioned at the first side wall of described grid both sides;
Use chemical acid solution to remove the gate dielectric layer that is positioned at grid both sides and semiconductor substrate surface, expose Semiconductor substrate;
Use original position steam growth technique again to form gate dielectric layer at semiconductor substrate surface.
2. the inhomogeneity method of raising large-sized silicon wafers device performance as claimed in claim 1, is characterized in that, the material of described gate dielectric layer is silicon dioxide.
3. the inhomogeneity method of raising large-sized silicon wafers device performance as claimed in claim 2, is characterized in that, described chemical acid solution is hydrofluoric acid.
4. the inhomogeneity method of raising large-sized silicon wafers device performance as claimed in claim 3, is characterized in that, the concentration ratio of described hydrofluoric acid is HF:H
2o=1:200.
5. the inhomogeneity method of raising large-sized silicon wafers device performance as claimed in claim 1, is characterized in that, the range of reaction temperature of described original position steam growth technique is 900 DEG C～1100 DEG C.
6. the inhomogeneity method of raising large-sized silicon wafers device performance as claimed in claim 5, is characterized in that, the reaction pressure scope of described original position steam growth technique is 5Torr～20Torr.
7. the inhomogeneity method of raising large-sized silicon wafers device performance as claimed in claim 5, is characterized in that, the reacting gas of described original position steam growth technique is oxygen and hydrogen.
8. the inhomogeneity method of raising large-sized silicon wafers device performance as claimed in claim 7, is characterized in that, the range of flow of described oxygen is 10slm～30slm, and the range of flow of described hydrogen is 1slm～5slm.
9. the inhomogeneity method of raising large-sized silicon wafers device performance as claimed in claim 5, is characterized in that, the reaction time range of described original position steam growth technique is 10s～40s.
10. the inhomogeneity method of raising large-sized silicon wafers device performance as claimed in claim 1, it is characterized in that, using original position steam growth technique after semiconductor substrate surface forms gate dielectric layer again, Semiconductor substrate to described grid both sides is carried out Light-Doped Drain Technology injection, forms device.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108447770A (en) * | 2018-03-08 | 2018-08-24 | 清华大学 | The preparation method of silica membrane |
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Application publication date: 20140618 |