CN103855071B - A kind of preparation method of semiconductor device - Google Patents
A kind of preparation method of semiconductor device Download PDFInfo
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- CN103855071B CN103855071B CN201210513831.XA CN201210513831A CN103855071B CN 103855071 B CN103855071 B CN 103855071B CN 201210513831 A CN201210513831 A CN 201210513831A CN 103855071 B CN103855071 B CN 103855071B
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- shallow trench
- active area
- material layer
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- etching
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 239000000463 material Substances 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000002955 isolation Methods 0.000 claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000002194 amorphous carbon material Substances 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000004528 spin coating Methods 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 229910018069 Cu3N Inorganic materials 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- JTCFNJXQEFODHE-UHFFFAOYSA-N [Ca].[Ti] Chemical compound [Ca].[Ti] JTCFNJXQEFODHE-UHFFFAOYSA-N 0.000 description 1
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910017464 nitrogen compound Inorganic materials 0.000 description 1
- 150000002830 nitrogen compounds Chemical group 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- XRFHCHCLSRSSPQ-UHFFFAOYSA-N strontium;oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Sr+2] XRFHCHCLSRSSPQ-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
The present invention relates to the preparation method of a kind of semiconductor device, including: providing Semiconductor substrate, described substrate is including at least core active district and surrounding active area；Sequentially form gate dielectric, gate material layers and hard mask layer over the substrate；Patterned hard mask layer and described gate material layers, with core active district and described around form opening on active area；Sacrificial material layer, to fill the opening formed in described core active district；Described sacrificial material layer in etching removal active area opening around；Perform the first shallow trench etching, so that active area around to be formed the first shallow trench；Remove the sacrificial material layer in described core active district opening；Performing the second shallow trench etching, to form core active district shallow trench in described substrate, around described, active area forms degree of depth surrounding's active area shallow trench more than the isolation of described core active district shallow trench.The method of the invention is more prone to control relative to prior art, and more accurate.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to the preparation side of a kind of semiconductor device
Method.
Background technology
Improving mainly by constantly reducing the size of IC-components to improve it of performance of integrated circuits
Speed realize.At present, due to quasiconductor in pursuing high device density, high-performance and low cost
Industry has advanced to nanotechnology process node, particularly when dimensions of semiconductor devices drop to 32nm or
Time following, bring a series of challenge to the manufacture of device.
Along with the reduction of device size, the restriction filled due to space in preparation process so that preparation
When 32nm and following device, particularly at close quarters, it is difficult to control depth-width ratio, such as at 32nm
Active area and neighboring area in flush memory device need preparation to have the shallow trench isolation of different depth
(shallow trench isolation, STI), prepares, at described active area, the STI that the degree of depth is 1800 angstroms,
Prepare, at active region, the STI that the degree of depth is 3000 angstroms, but prior art is difficulty with this purpose.
Currently available technology make described etching process stop typically by the angle being accurately controlled STI
In 1800 angstroms, but this degree of depth and STI critical size and angle have close relationship, if described
The critical size of STI and angle have skew somewhat, then make the degree of depth of described STI become heterogeneity,
As shown in Figure 1.
Prepare the method for shallow trench isolation of different depth at present as shown in figures 2-6, first quasiconductor is provided
Substrate 101, over the substrate formed gate oxide level 102, polysilicon layer 103, hard mask layer 104,
Second advanced patterned layer (advanced pattern film), oxynitride layer, oxide skin(coating) and first are first
Entering patterned layer (advanced pattern film) 106, wherein said hard mask layer 104 can be oxide
With nitride composite laminate, form the photoresist layer of patterning, reference the most over the substrate
Fig. 3, with described photoresist for the advanced patterned layer 106 of mask layer patterning described first, is then forming institute
State on pattern deposition spacer material layer 107, with reference to Fig. 4, pattern described spacer material layer, with
Form clearance wall in described first advanced patterned layer, then remove the advanced patterned layer of residue described first, ginseng
According to Fig. 5, around described, first on active region, form the photoresist layer of patterning, pattern described oxygen
Change the advanced patterned layer of layer, oxynitride layer and second, referring finally to Fig. 6, with what Fig. 5 obtained
Pattern is that mask is etched, and is etched to described Semiconductor substrate 101, with respectively in active area and week
Enclose region and form the shallow trench isolation that the degree of depth is different.
Form, at active area and active region, the shallow trench that the degree of depth is different although prior art discloses
Isolation, but existing method relies on the most very much the critical size with the isolation of described shallow trench and angle, described
Critical size and angle slightly offset, and cause degree of depth heterogeneity, and whole process is the most loaded down with trivial details, it is difficult to control
System, the yield of product is the lowest.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will be in detailed description of the invention
Part further describes.The Summary of the present invention is not meant to attempt to limit institute
The key feature of claimed technical scheme and essential features, more do not mean that and attempt to determine and wanted
Seek the protection domain of the technical scheme of protection.
The invention provides the preparation method of a kind of semiconductor device, including:
Thering is provided Semiconductor substrate, described substrate is including at least core active district and surrounding active area；
Sequentially form gate dielectric, gate material layers and hard mask layer over the substrate；
Pattern described hard mask layer and described gate material layers, with in described core active district and described week
It is with in source region formation opening；
Sacrificial material layer, to fill the opening formed in described core active district；
Described sacrificial material layer in etching removal active area opening around；
Perform the first shallow trench etching, so that active area around described to be formed the first shallow trench；
Remove the sacrificial material layer in described core active district opening；
Perform the second shallow trench etching, to form core active district shallow trench in described substrate, described
Around active area forms degree of depth surrounding's active area shallow trench more than described core active district shallow trench.
As preferably, conformal deposited sacrificial material layer, to fill the opening formed in described core active district.
As preferably, described hard mask layer is the silicon nitride and oxide being sequentially depositing.
As preferably, described sacrificial material layer is dielectric medium, inorganic matter, amorphous carbon and metal material layer
In one or more.
As preferably, the deposition process of described sacrificial material layer is CVD, PVD, ALD or controls rotation
It is coated with.
As preferably, select sacrificial material layer described in dry method or wet etching, have around described to remove
Described sacrificial material layer in source region opening.
As preferably, described dry etching is isotropic etching.
As preferably, HBr, Cl are selected in described first shallow trench etching2、O2、N2、NF3、Ar、He
And CF4In one or more.
As preferably, HBr, Cl are selected in described second shallow trench etching2、O2、N2、NF3、Ar、He
And CF4In one or more.
As preferably, described gate material layers is polysilicon layer.
As preferably, described method also includes forming the shallow trench isolation of core active district further and surrounding has
The step of source region shallow trench isolation.
As preferably, in described core active district shallow trench and described around formed in active area shallow trench
Silicon oxide layer, described silicon oxide layer covers described substrate, planarizes described silicon oxide layer to described substrate.
In the present invention, by two shallow trench etching steps, respectively core active district and around active
The shallow trench isolation that the degree of depth is different is formed, wherein only in described week in first time shallow trench etching process in district
Be with in source region and form shallow trench, and described in be etched in active area in stop in described sacrificial material layer,
Around the degree of depth of shallow trench described in active area is the isolation of active area shallow trench and surrounding active area shallow trench
Depth difference between isolation, then performs second time shallow trench and is etched to target depth, by controlling this erosion
Quarter process realize zones of different have different depth shallow trench isolation, more hold relative to prior art
Easy to control, and more accurate.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Accompanying drawing shows
Go out embodiments of the invention and description thereof, be used for explaining assembly of the invention and principle.In the accompanying drawings,
Fig. 1 is the shallow trench isolation degree of depth inhomogenous device schematic diagram that prior art prepares；
Fig. 2-6 is the preparation process schematic diagram in prior art containing different depth shallow trench isolating device；
Fig. 7-12 is the preparation process schematic diagram in the present invention containing different depth shallow trench isolating device；
Figure 13 is the process chart in the preparation present invention containing different depth shallow trench isolating device.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention the most thoroughly
Understand.It is, however, obvious to a person skilled in the art that the present invention can be without one
Or multiple these details and be carried out.In other example, in order to avoid obscuring with the present invention,
Technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by proposing detailed description in following description, so that this to be described
Bright described semiconductor device containing highly controllable fin and preparation method thereof.Obviously, the execution of the present invention is also
It is not limited to the specific details that the technical staff of semiconductor applications is familiar with.Presently preferred embodiments of the present invention is detailed
It is described as follows, but in addition to these describe in detail, the present invention can also have other embodiments.
Should give it is noted that term used herein above is merely to describe specific embodiment, rather than meaning
Figure limits the exemplary embodiment according to the present invention.As used herein, unless context is the brightest
Really pointing out, otherwise singulative is also intended to include plural form.Additionally, it should be understood that, when
This specification uses term " comprise " and/or time " including ", its indicate exist described feature, entirety,
Step, operation, element and/or assembly, but do not preclude the presence or addition of other features one or more, whole
Body, step, operation, element, assembly and/or combinations thereof.
Now, the exemplary embodiment according to the present invention it is more fully described with reference to the accompanying drawings.But, this
A little exemplary embodiments can be implemented with multiple different form, and should not be construed to be limited solely to this
In the embodiment that illustrated.It should be appreciated that these embodiments are provided to obtain the public affairs of the present invention
Open thorough and complete, and the design of these exemplary embodiments is fully conveyed to ordinary skill
Personnel.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use identical
Reference represents identical element, thus will omit description of them.
Below in conjunction with the Fig. 7-12 semiconductor device to the shallow trench isolation different containing the degree of depth of the present invention
Preparation method be described further:
With reference to Fig. 7, first providing Semiconductor substrate 201, described substrate includes at least core active district (Core
Active Area, AA) and around active area (Periphery Active Area, PAA), described partly lead
Body substrate can be at least one in the following material being previously mentioned: silicon, silicon-on-insulator (SOI), absolutely
Stacking SiGe (S-SiGeOI), germanium on insulator SiClx on stacking silicon (SSOI), insulator on edge body
(SiGeOI) and germanium on insulator (GeOI) etc., can also be formed other in the semiconductor substrate
Active device.Preferred silicon-on-insulator (SOI) in the present invention, described silicon-on-insulator (SOI) wraps
Include and be followed successively by support substrate, oxide insulating layer and semiconductor material layer, wherein said top from the bottom up
The semiconductor material layer in portion is monocrystalline silicon layer, polysilicon layer, SiC or SiGe.
Being sequentially depositing gate dielectric 202 on a semiconductor substrate, wherein said gate material layers can be
Silicon oxide (SiO2) or silicon oxynitride (SiON).The oxidation technology known by those skilled in the art can be used
Such as furnace oxidation, rapid thermal annealing oxidation (RTO), in situ steam oxidation (ISSG) etc. form silicon oxide
The gate dielectric of material.Silicon oxide is performed nitriding process and can form silicon oxynitride, wherein, described nitrogen
Metallization processes can be high temperature furnace pipe nitridation, rapid thermal annealing nitridation or pecvd nitride, certainly, also may be used
To use other nitriding process, repeat no more here.Described gate dielectric can pass through thermal oxide,
Nitridation or oxynitridation process are formed.When forming gate dielectric, it is also possible to be applied in combination above-mentioned technique.
Gate dielectric can include following any conventional dielectric: SiO2、Si3N4、SiON、SiON2、
Such as TiO2、Al2O3、ZrO2、HfO2、Ta2O5、La2O3High-k dielectric and include calcium titanium
Other similar oxide of ore deposit type oxide, but it is not limited to this.Generally, high-k dielectric is amenable to high temperature
(900 DEG C) anneal.Gate dielectric can also include any combination of above-mentioned dielectric substance.
Gate dielectric can include traditional dielectric substance such as have electric medium constant from about 4 to
The oxide of silicon, nitride and the nitrogen oxides of about 20 (true aerial surveties).Or, gate dielectric
The usual relatively high dielectric constant electricity that there is electric medium constant from about 20 at least about 100 can be included
Dielectric material.The preferred high-k of gate dielectric (high K) material.Described hafnium includes oxidation
Hafnium, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide,
Strontium barium oxide titanium, Barium monoxide titanium, strontium oxide titanium, aluminium oxide etc..Particularly preferably hafnium oxide, oxidation
Zirconium and aluminium oxide.The formation process of gate dielectric can use well known to those skilled in the art any existing
Having technology, compare preferably chemical vapour deposition technique, the thickness of gate dielectric is 15 to 60 angstroms.
Deposition of gate material layer 203 on described gate dielectric is the preferred Si of described gate material layers, many
Crystal silicon, SiGe, Ge or III-V material, the most preferably polysilicon layer.
Then in described gate material layers deposit hard mask layer, described hard mask layer can be nitride,
Oxide and/or metal hard mask layer, such as SiN, A-C, SiO2, BN, SiON, TiN and Cu3N
In one or more.In a detailed description of the invention of the present invention, described hard mask layer is preferably nitrogen
Compound layer 204 and the combination of oxide skin(coating) 205, wherein said nitride layer can be SiN, described oxygen
Compound layer can be SiON or SiO2, but not limitation and this example.
Forming method in above-mentioned gate material layers 203 and described hard mask layer 204,205 can be selected
Chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD)
Low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy that methods etc. are formed are raw
One in long (SEG).
With reference to Fig. 8, pattern described hard mask layer and described gate material layers, with at described core active
Opening is formed in district and described surrounding active area；
Specifically, the photoresist layer (not shown) of patterning is formed the most over the substrate, wherein
Described photoresist layer defines critical size and the number of shallow trench isolation to be formed, then with institute
Stating photoresist layer is mask, etches described hard mask layer and described gate material layers, stops at described grid
Pole dielectric layer, to protect described substrate, respectively described core active district and around formed in active area many
Individual opening, the critical size as preferred described surrounding active area inner opening is more than in described core active district
The size of opening.
With reference to Fig. 9, sacrificial material layer, to fill the opening formed in described core active district；
Specifically, conformal deposited sacrificial material layer over the substrate, to be filled up completely with described core active
The opening formed in district, and around described in active area, at sidewall and the described grid of described opening
Form one layer of sacrificial material layer on dielectric layer, do not fully seal described opening, as shown in Figure 9.
As preferably, described sacrificial material layer is dielectric layer, inorganic material layer, amorphous carbon or metal
One or more in material layer, the forming method of described sacrificial material layer is chemical gaseous phase deposition
(CVD) what method, physical vapor deposition (PVD) method or ald (ALD) method etc. were formed is low
Pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) or control spin coating (controlled
Spin-on) one in.
With reference to Figure 10, the described sacrificial material layer in etching removal active area opening around；
Specifically, etch described sacrificial material layer, the whole sacrificial material layer in removal active area around,
To open described surrounding active area, and in described core active district, only remove part described sacrifice material
The bed of material, as preferably, can select dry etching or wet etching to realize above-mentioned mesh in this step
, wherein when selecting dry etching, described dry etching controls as isotropic etching.
With reference to Figure 11, perform the first shallow trench etching, so that active area around described to be formed the first shallow ridges
Groove；
Specifically, can select the engraving method of routine in this step, in core active district, etching is removed
The described sacrificial material layer of part and described hard mask layer, and first etch to beat in active area around described
Open described gate dielectric, then etch described semiconductor material layer, form the first shallow trench.
HBr, Cl can be selected in a detailed description of the invention of the present invention2、O2、N2、NF3、Ar、
He and CF4In one or more as etching gas, as preferably, described etching is selected CF4、
NF3Gas, it can in addition contain plus N2、O2In one as etching atmosphere, wherein said gas
Flow be 20-100sccm, preferably 50-80sccm, described etching pressure is 30-150mTorr,
Etching period is 5-120s, preferably 5-60s, more preferably 5-30s, and the most described dry etching selects
With Ar as diluent gas.
In this step, described in be etched in core active district in stop in described sacrificial material layer, and
Around in described substrate, define first shallow trench with certain depth, described shallow trench in active area
The degree of depth be the depth difference between the isolation of core active district shallow trench with active area shallow trench isolation around,
Therefore by control the etching process of this step realize zones of different have the shallow trench of different depth every
From, this step is more prone to control relative to prior art, and more accurate.
With reference to Figure 12, remove the sacrificial material layer in described core active district opening, perform the second shallow trench
Etching, to form core active district shallow trench in described substrate, around described, active area forms the degree of depth
Surrounding's active area shallow trench more than the isolation of described core active district shallow trench.
Specifically, the most described core active district and described surrounding active area are etched,
In described core active district, remove remaining sacrificial material layer, be then etched to the purpose degree of depth, and in week
On the basis of described first shallow trench isolation, etching is proceeded in enclosing district's active area, deeper to obtain
Active area shallow trench around, to required target depth.
HBr, Cl can be selected in this step2、O2、N2、NF3, Ar, He and CF4In one
Or multiple as etching gas, concrete etching condition is referred to the first shallow trench isolation etching, it is possible to
To be adjusted as required, do not repeat them here.
Formed after described shallow trench, described method also include being formed further core active district shallow trench every
From the step isolated with active area shallow trench around, specifically, in described core active district shallow trench and
Forming silicon oxide layer in described surrounding active area shallow trench, described silicon oxide layer covers described substrate；Smooth
Change described silicon oxide layer to described substrate.
In the present invention, by two shallow trench etching steps, respectively core active district and around active
The shallow trench isolation that the degree of depth is different is formed, wherein only in described week in first time shallow trench etching process in district
Be with in source region and form shallow trench, and described in be etched in core active district in stop at described sacrificial material layer
On, around the degree of depth of shallow trench described in active area is the shallow trench isolation of core active district and surrounding is active
Depth difference between district's shallow trench isolation, then performs second time shallow trench and is etched to target depth, pass through
Control this etching process, to realize zones of different, there is the shallow trench isolation of different depth, relative to existing skill
Art is more prone to control, and more accurate.
Figure 13 is the process chart preparing semiconductor device of the present invention, comprises the following steps:
Step 201 provides Semiconductor substrate, and described substrate is the most active including at least core active district and surrounding
District；
Step 202 sequentially forms gate dielectric, gate material layers and hard mask layer over the substrate；
Step 203 patterns described hard mask layer and described gate material layers, with in described core active district
With formation opening on described surrounding active area；
Step 204 sacrificial material layer, to fill the opening formed in described core active district；
Described sacrificial material layer in step 205 etching removal active area opening around；
Step 206 performs the first shallow trench etching, to form the first shallow trench in active area around described；
Step 207 removes the sacrificial material layer in described core active district opening；
Step 208 performs the second shallow trench etching, to form core active district shallow trench in described substrate,
Around described, the active area formation degree of depth is shallow more than surrounding's active area of described core active district shallow trench isolation
Groove.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment
It is only intended to citing and descriptive purpose, and is not intended to limit the invention to described scope of embodiments
In.In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-described embodiment, root
Can also make more kinds of variants and modifications according to the teachings of the present invention, these variants and modifications all fall within this
Within inventing scope required for protection.Protection scope of the present invention by the appended claims and etc.
Effect scope is defined.
Claims (12)
1. a preparation method for semiconductor device, including:
Thering is provided Semiconductor substrate, described substrate is including at least core active district and surrounding active area；
Sequentially form gate dielectric, gate material layers and hard mask layer over the substrate；
Pattern described hard mask layer and described gate material layers, with in described core active district and described week
It is with in source region formation opening；
Sacrificial material layer, to fill the opening formed in described core active district；
Described sacrificial material layer in etching removal active area opening around；
Perform the first shallow trench etching, to form the first shallow trench in active area around described, described the
One shallow trench stops in being etched in described active area in described sacrificial material layer, in described surrounding active area
The degree of depth of described first shallow trench is the isolation of described active area shallow trench and surrounding active area shallow trench is isolated
Between depth difference；
Remove the sacrificial material layer in described core active district opening；
Perform the second shallow trench etching, to form core active district shallow trench in described substrate, described
Around active area forms degree of depth surrounding's active area shallow trench more than described core active district shallow trench.
Method the most according to claim 1, it is characterised in that conformal deposited sacrificial material layer, with
Fill the opening formed in described core active district.
Method the most according to claim 1, it is characterised in that described hard mask layer is for being sequentially depositing
Silicon nitride and oxide.
Method the most according to claim 1, it is characterised in that described sacrificial material layer be dielectric medium,
One or more in inorganic matter, amorphous carbon and metal material layer.
Method the most according to claim 1, it is characterised in that the deposition side of described sacrificial material layer
Method is CVD, PVD, ALD or controls spin coating.
Method the most according to claim 1, it is characterised in that select dry method or wet etching institute
State sacrificial material layer, to remove the described sacrificial material layer in described surrounding active area opening.
Method the most according to claim 6, it is characterised in that described dry etching is isotropism
Etching.
Method the most according to claim 1, it is characterised in that described first shallow trench etching is selected
HBr、Cl2、O2、N2、NF3, Ar, He and CF4In one or more.
Method the most according to claim 1, it is characterised in that described second shallow trench etching is selected
HBr、Cl2、O2、N2、NF3, Ar, He and CF4In one or more.
Method the most according to claim 1, it is characterised in that described gate material layers is polycrystalline
Silicon layer.
11. methods according to claim 1, it is characterised in that described method also includes further
Form the shallow trench isolation of core active district and the step of surrounding active area shallow trench isolation.
12. according to the method described in claim 1 or 11, it is characterised in that in described core active district
Forming silicon oxide layer in shallow trench and in described surrounding active area shallow trench, described silicon oxide layer covers described
Substrate, planarizes described silicon oxide layer to described substrate.
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