CN103853675B

CN103853675B - A kind of method and apparatus for accessing internal memory

Info

Publication number: CN103853675B
Application number: CN201210520124.3A
Authority: CN
Inventors: 赵长虹; 苏健
Original assignee: HiSilicon Technologies Co Ltd
Current assignee: HiSilicon Technologies Co Ltd
Priority date: 2012-12-06
Filing date: 2012-12-06
Publication date: 2017-03-15
Anticipated expiration: 2032-12-06
Also published as: CN103853675A

Abstract

The invention discloses a kind of method and apparatus for accessing internal memory, belongs to computer realm.Method includes：The first step, receives the order of the access internal memory that external equipment sends, carries the number of the data cell that external equipment needs are accessed and the memory address for accessing in order；Second step, according to the bandwidth of bus free, determines the first numerical value and second value；3rd step, if the number that memory address is the integral multiple of second value bus bit wide sum and data cell is more than or equal to second value, read or write second value data cell, reduce the number of data cell, increase memory address, second value is updated to the first numerical value, this step is returned；4th step, if memory address is not the integral multiple of second value bus bit wide sum, second value is obtained third value divided by 2 less than second value and more than or equal to 1 by data cell number, and second value is updated to third value, returns the 3rd step.The present invention improves the efficiency for accessing internal memory.

Description

A kind of method and apparatus for accessing internal memory

Technical field

The present invention relates to computer realm, more particularly to a kind of method and apparatus for accessing internal memory.

Background technology

In computer systems, computer frequently conducts interviews to internal memory, and the operation for accessing internal memory includes read operation And write operation.

At present, the method for accessing internal memory is specially：The order of the access internal memory that external equipment sends is received, is taken in the order The number of the data cell of access and the memory address for accessing is needed with external equipment, if the corresponding operation of the order is reading behaviour Make, the memory address of external device access is the integral multiple of 4 bus bit wide sums, and external equipment needs the data that access The number of unit is more than or equal to 4, then the memory address for being accessed from external equipment in internal memory starts to read 4 data sheets Unit, if the memory address of external device access is not the integral multiple of 4 bus bit wide sums, or external equipment needs access The number of data cell then starts to read 1 data cell from the memory address of external device access in internal memory less than 4；Such as Really the corresponding operation of the order is for write operation and external equipment needs the number of the data cell for accessing more than or equal to 1, then exist The memory address accessed from external equipment in internal memory starts to write 1 data cell.

During the present invention is realized, inventor has found that prior art at least has problems with：

If the memory address accessed by external equipment is not the integral multiple or external equipment needs of 4 bus bit wide sums When the number of the data cell of access is less than 4, then the memory address for being accessed from external equipment in internal memory starts to read 1 number According to unit, if external equipment needs the number of the data cell for accessing to be more than or equal to 1, from external equipment institute in internal memory The memory address of access starts to write 1 data cell, and the mode for so accessing internal memory can reduce the efficiency for accessing internal memory.

Content of the invention

In order to solve problem of the prior art, a kind of method and apparatus for accessing internal memory is embodiments provided.Institute State technical scheme as follows：

In a first aspect, a kind of method for accessing internal memory, methods described includes：

The first step, receives the order of the access internal memory that external equipment sends, and carrying the external equipment in the order needs The number of data cell to be accessed and the memory address for accessing；

Second step, according to the idle bandwidth of terminal internal bus, determines the first numerical value and second value, described first numerical value etc. In the second value, first numerical value and the second value both greater than or equal to 1 and be all 2 index power；

3rd step, if the memory address is the integral multiple of the second value bus bit wide sum and the data The number of unit is more than or equal to the second value, then read according to the memory address or write the second value number According to unit, the number of the data cell is reduced according to the second value and increases the memory address, by described second Numerical value is updated to first numerical value, returns this step；

4th step, if the memory address is not the integral multiple or the number of the second value bus bit wide sum The second value is then obtained third value divided by 2 less than the second value and more than or equal to 1 by the number according to unit, The second value is updated to the third value, the 3rd step is returned.

In conjunction with a first aspect, in the first possible implementation of above-mentioned first aspect, described according to total in terminal The idle bandwidth of line, determines that the first numerical value and second value, first numerical value are equal to the second value, including：

According to the idle bandwidth of terminal internal bus, the bandwidth range belonging to the bandwidth of the bus free is determined；

Bandwidth range according to belonging to the bandwidth of the bus free, from the bandwidth range for having stored and the first numerical value Corresponding first numerical value of bandwidth of the bus free is determined in corresponding relation, and determines second value, described first numerical value etc. In the second value.

In conjunction with a first aspect, in second possible implementation of above-mentioned first aspect, described according to described second Numerical value reduces the number of the data cell and increases the memory address, including：

The number of the data cell for needing to access the external equipment reduces the second value, the institute after being reduced State the number of the data cell that external equipment needs to access；

According to the second value, the memory address of the external device access and bus bit wide, increased according to equation below Plus the memory address of the external device access,

Addr2=Addr1+buswidth/8*n

Wherein, in the formula, Addr2 is the memory address of the external device access after increasing, and Addr1 is to increase Plus before the external device access memory address, buswidth be the bus bit wide, n be the second value.

In conjunction with any one possible implementation of second possible implementation of first aspect to first aspect, In the third possible implementation of above-mentioned first aspect, described receive external equipment send access internal memory order it Afterwards, also include：

The number of the data cell for needing to access the external equipment is stored in the first depositor；

The memory address of the external device access is stored in the second depositor.

In conjunction with the third possible implementation of first aspect, in the 4th kind of possible realization side of above-mentioned first aspect In formula, after number and the increase memory address for reducing the data cell according to the second value, also wrap Include：

The number of the data cell stored in first depositor is updated to the data cell after reducing Number；

The memory address stored in second depositor is updated to the memory address after increasing.

Second aspect, a kind of equipment of access internal memory, the equipment include：

Receiver module, for receiving the order of the access internal memory of external equipment transmission, carries the outside in the order Equipment needs the number of the data cell for accessing and the memory address for accessing；

Determining module, for according to the idle bandwidth of terminal internal bus, determining the first numerical value and second value, described first Numerical value is equal to the second value, first numerical value and the second value both greater than or equal to 1 and all be 2 index secondary Side；

Read or writing module, if being the integer of the second value bus bit wide sum for the memory address Times and the data cell number be more than or equal to the second value, then according to the memory address read or write described in Second value data cell, reduces the number of the data cell according to the second value and increases the internal memory ground The second value is updated to first numerical value, returns this module by location；

Reduce module, if for the memory address be not the second value bus bit wide sum integral multiple or The second value is then obtained the 3rd divided by 2 less than the second value and more than or equal to 1 by the number of the data cell The second value is updated to the third value by numerical value, is returned and is read or writing module.

In conjunction with second aspect, in the first possible implementation of above-mentioned second aspect, the determining module includes：

First determining unit, for according to the idle bandwidth of terminal internal bus, determining belonging to the bandwidth of the bus free In bandwidth range；

Second determining unit, for the bandwidth range according to belonging to the bandwidth of the bus free, from the band for having stored Corresponding first numerical value of bandwidth of the bus free is determined in the corresponding relation of wide scope and the first numerical value, and determines the second number Value, first numerical value are equal to the second value.

In conjunction with second aspect, in second possible implementation of above-mentioned second aspect, the reading writes mould Block includes：

Read or writing unit, if being the integer of the second value bus bit wide sum for the memory address Times and the data cell number be more than or equal to the second value, then according to the memory address read or write described in The second value is updated to first numerical value by second value data cell；

First reduces unit, for the external equipment needs the number of the data cell for accessing reduce second number Value, the external equipment after being reduced need the number of the data cell for accessing；

Adding unit, for according to the second value, the memory address of the external device access and bus bit wide, root According to the memory address that equation below increases the external device access,

Addr2=Addr1+buswidth/8*n

In conjunction with any one possible implementation of second possible implementation of second aspect to second aspect, In the third possible implementation of above-mentioned second aspect, the equipment also includes：

First memory module, for needing the number of the data cell for accessing to be stored in the first deposit by the external equipment In device；

Second memory module, for the memory address of the external device access is stored in the second depositor.

In conjunction with the third possible implementation of second aspect, in the 4th kind of possible realization side of above-mentioned second aspect In formula, the equipment also includes：

First update module, for the number of the data cell stored in first depositor to be updated to reduce The number of the data cell afterwards；

Second update module, for being updated to the institute after increasing by the memory address stored in second depositor State memory address.

The third aspect, a kind of equipment of access internal memory, the equipment include memorizer and processor, for executing described one Plant the method for accessing internal memory.

In embodiments of the present invention, the first step, receives the order of the access internal memory that external equipment sends, carries in the order External equipment needs the number of the data cell for accessing and the memory address for accessing；Second step, idle according to terminal internal bus Bandwidth, determines that the first numerical value and second value, the first numerical value are equal to second value, and the first numerical value and second value both greater than or are waited In 1 and be all 2 index power；3rd step, if memory address is the integral multiple of the second value bus bit wide sum And the number of data cell is more than or equal to second value, then read according to the memory address or write second value data Unit, reduces the number of data cell according to second value and increases memory address, second value is updated to the first numerical value, Return this step；4th step, if memory address is not the integral multiple of second value bus bit wide sum or data cell Second value is then obtained third value divided by 2, second value is updated to less than second value and more than or equal to 1 by number Third value, returns the 3rd step.Wherein, when the memory address of external device access is not second value bus bit wide sum The number of integral multiple or the data cell be less than second value when, will not immediately will determine second value be reduced to 1 and read or 1 data cell of write, thus, the efficiency for accessing internal memory can be improved.

Description of the drawings

Fig. 1 is a kind of method flow diagram for accessing internal memory provided in an embodiment of the present invention；

Fig. 2 is another kind of method flow diagram for accessing internal memory provided in an embodiment of the present invention；

Fig. 3 is another kind of method flow diagram for accessing internal memory provided in an embodiment of the present invention；

Fig. 4 is another kind of method flow diagram for accessing internal memory provided in an embodiment of the present invention；

Fig. 5 is another kind of method flow diagram for accessing internal memory provided in an embodiment of the present invention；

Fig. 6 is another kind of method flow diagram for accessing internal memory provided in an embodiment of the present invention；

Fig. 7 is a kind of apparatus structure schematic diagram for accessing internal memory provided in an embodiment of the present invention；

Fig. 8 is another kind of apparatus structure schematic diagram for accessing internal memory provided in an embodiment of the present invention.

Specific embodiment

For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention Formula is described in further detail.

A kind of method for accessing internal memory is embodiments provided, referring to Fig. 1, method flow includes：

Step 101：The order of the access internal memory that external equipment sends is received, and the external equipment is carried in the order to be needed to visit The number of the data cell that asks and the memory address for accessing；

Step 102：According to the idle bandwidth of terminal internal bus, determine that the first numerical value and second value, the first numerical value are equal to Second value, the first numerical value and second value both greater than or equal to 1 and be all 2 index power；

Step 103：If memory address is the number of the integral multiple of second value bus bit wide sum and data cell It is more than or equal to second value, then is read according to memory address or write second value data cell, subtracted according to second value Second value is updated to the first numerical value, returns this step by the number of few data cell and increase memory address；

Step 104：If memory address be not the integral multiple of second value bus bit wide sum or data cell Second value is then obtained third value divided by 2 less than second value and more than or equal to 1 by number, and second value is updated to the Three numerical value, return to step 103.

In embodiments of the present invention, the first step, receives the order of the access internal memory that external equipment sends, carries in the order External equipment needs the number of the data cell for accessing and the memory address for accessing；Second step, idle according to terminal internal bus Bandwidth, determines that the first numerical value and second value, the first numerical value are equal to second value, and the first numerical value and second value both greater than or are waited In 1 and be all 2 index power；3rd step, if memory address is the integral multiple and number of second value bus bit wide sum It is more than or equal to second value according to the number of unit, then is read according to memory address or write second value data cell, root The number of data cell is reduced according to second value and increases memory address, second value is updated to the first numerical value, this is returned Step；4th step, if memory address be not the integral multiple of second value bus bit wide sum or data cell number little In second value and more than or equal to 1, then second value is obtained third value divided by 2, second value is updated to the 3rd number Value, returns the 3rd step.Wherein, when the memory address of external device access is not the integral multiple of second value bus bit wide sum Or the number of the data cell is when being less than second value, will not will determine that second value be reduced to 1 and read or write 1 immediately Data cell, thus, the efficiency for accessing internal memory can be improved.

A kind of method for accessing internal memory is embodiments provided, referring to Fig. 2, method flow includes：

Step 201：The order of the access internal memory that external equipment sends is received, is carried outside this in the order of the access internal memory Equipment needs the number of the data cell for accessing and the memory address for accessing；

Wherein, external equipment needs the number of the data cell for accessing to there is a maximum, in the present embodiment will be outer Portion's equipment needs the maximum of the number of the data cell for accessing to illustrate as a example by 16.

Wherein, in the present embodiment, external equipment need access data cell number more than or equal to 1 and less than or It is equal to 16.

Wherein, the external equipment carried in the order of the access internal memory is needed the number of the data cell for accessing to store In the first depositor, the memory address of external device access is stored in the second depositor.

Wherein, the size of a data cell and a bus bit wide is equal in magnitude.

Step 202：According to the idle bandwidth of terminal internal bus, determine that the first numerical value and second value, the first numerical value are equal to Second value, if the first numerical value and second value are 16；

Specifically, according to the bandwidth that terminal internal bus is idle, determine the bandwidth belonging to the idle bandwidth of terminal internal bus Scope, the bandwidth range according to belonging to the bandwidth of the bus free for determining are right from the bandwidth range for having stored and the first numerical value Corresponding first numerical value of bandwidth of the bus free in should being related to, is obtained, and determines second value, the first numerical value and second value Equal, the first numerical value and second value both greater than or equal to 1 and be all 2 index power, if the first numerical value and second value It is 16.

Wherein, the corresponding relation of the first numerical value and control signal is preserved in advance, when the first numerical value for determining is 16, to CPU sends 16 corresponding control signal of the first numerical value, makes CPU execute the 16 corresponding block16 operations of the first numerical value, block16 Operation is to read from internal memory or write 16 data cells.

Step 203：Whether the memory address for judging external device access is the integral multiple of 16 bus bit wide sums, and Judge that external equipment needs whether the number of the data cell for accessing is equal to second value 16, if the internal memory of external device access Address is that the number of the data cell that the integral multiple of 16 bus bit wide sums and external equipment needs are accessed is counted equal to second Value 16, then execution step 204, otherwise, execution step 205；

Specifically, the memory address of external device access and 16 bus bit wide sums are compared, judge outside setting Whether the standby memory address for accessing is the integral multiple of 16 bus bit wide sums, and judges that external equipment needs the data for accessing Whether the number of unit is equal to 16, if the memory address of external device access be the integral multiple of 16 bus bit wide sums and External equipment needs the number of the data cell for accessing to be equal to 16, then execution step 204, otherwise, execution step 205.

For example, the bit wide of bus is 128bit, as 16Byte, and external equipment needs the number of data cell for accessing to be 16,16 bus bit wide sums are that the bus bit wide sum of 16*16Byte, i.e., 16 is 256Byte, the internal memory accessed by bus Address and 16 bus bit wide sums 256Byte compare, and judge whether the memory address accessed by bus is 16 bus bit wides The integral multiple of sum 256Byte, and judge that external equipment needs the number of the data cell for accessing to be equal to second value 16, such as The memory address accessed by fruit bus is the integral multiple of 16 bus bit wide sums 256Byte, then execution step 204.

Step 204：Read according to the memory address of external device access or write 16 data cells of second value, terminated Operation；

Wherein, when the corresponding operation of the order of external device access internal memory is read operation, external device access internal memory The number of the data cell that external equipment needs are accessed and the memory address for accessing is carried in order.

Wherein, when the corresponding operation of the order of external device access internal memory is write operation, external device access internal memory In order in addition to carrying the external equipment number for needing the data cell for accessing and the memory address for accessing, in the order also Carry the data cell that external equipment needs to access.

Wherein, when the corresponding operation of the order of external device access internal memory is read operation, then set from outside in internal memory The standby memory address for accessing starts to read 16 data cells, when the corresponding operation of the order of external device access internal memory is to write behaviour When making, then start to write 16 data cells from the memory address of external device access in internal memory.

Wherein, start to read 16 data cells from the memory address of external device access in internal memory and be specially：Including In depositing, start from the memory address of external device access 16 data cells are set to outside by the bus transfer in terminal Standby.

Wherein, start to write 16 data units from the memory address of external device access in internal memory and be specially：Including In depositing, 16 data cells carried in the order of external device access internal memory are visited from external equipment by the bus in terminal The memory address that asks starts to be transferred to internal memory.

Wherein, after reading or write 16 data cells of second value according to the memory address of external device access, will Zeros data in first depositor and the second depositor.

Wherein, in the present embodiment, it is 16 that external equipment needs the maximum of the number of the data cell for accessing, according to outer After the memory address that portion's equipment is accessed reads or writes 16 data cells, the data cell of external device access is 0, then tie Beam is operated.

Step 205：By second value 16 divided by 2, it is 8 to obtain third value, and second value is updated to third value 8；

Wherein, second value is updated to after third value 8, second value is just changed into 8.

Step 206：Whether the memory address for judging external device access is the integral multiple of 8 bus bit wide sums, and Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 8, if external device access Memory address be 8 bus bit wide sums integral multiple and external equipment need access data cell number more than or Second value 8 is equal to, then execution step 207, otherwise, execution step 208；

Specifically, the memory address of external device access and 8 bus bit wide sums are compared, judge external equipment Whether the memory address of access is the integral multiple of 8 bus bit wide sums, and judges that external equipment needs the data sheet for accessing Whether the number of unit is more than or equal to 8, if the memory address of external device access be the integral multiple of 8 bus bit wide sums simultaneously And external equipment needs the number of the data cell for accessing to be more than or equal to 8, then execution step 207, otherwise, execution step 208.

Step 207：Read according to the memory address of external device access or 8 data cells of write, and according to the second number Value 8 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, by second Numerical value 8 is updated to the first numerical value 16, return to step 203；

Specifically, start to read or write 8 data cells from the memory address of external device access, according to second value 8 numbers for reducing the data cell that external equipment needs to access, and according to second value 8 and bus bit wide, according to following public affairs Formula (1) increases the memory address of external device access, and second value 8 is updated to the first numerical value 16, return to step 203,

Addr2=Addr1+buswidth/8*8 (1)

Wherein, in formula (1), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

Wherein, according to the concrete operations of the number of the data cell of the minimizing external equipment needs access of second value 8 it is：Will External equipment needs the number of the data cell for accessing to deduct second value 8.

Wherein, when the corresponding operation of the order of external device access internal memory is read operation, then set from outside in internal memory The standby memory address for accessing starts to read 8 data cells, when the corresponding operation of the order of external device access internal memory is to write behaviour When making, then start to write 8 data cells from the memory address of external device access in internal memory.

Wherein, start to read 8 data cells from the memory address of external device access in internal memory and be specially：In internal memory In, by 8 data cells started from the memory address of external device access by the bus transfer in terminal to external equipment.

Wherein, start to write 8 data units from the memory address of external device access in internal memory and be specially：In internal memory In, by 8 data cells carried in the order of external device access internal memory by the bus in terminal from external device access Memory address start to be transferred to internal memory.

Wherein, after reading or write 8 data cells according to the memory address of external device access, by the first depositor In external equipment need access data cell number be updated to reduce after data cell number, by the second depositor In external device access memory address be updated to increase after memory address.

Step 208：By second value 8 divided by 2, it is 4 to obtain third value, and second value is updated to third value 4；

Wherein, second value is updated to after third value 4, second value is just changed into 4.

Step 209：Whether the memory address for judging external device access is the integral multiple of 4 bus bit wide sums, and Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 4, if external device access Memory address be 4 bus bit wide sums integral multiple and external equipment need access data cell number more than or Second value 4 is equal to, then execution step 210, otherwise, execution step 211；

Specifically, the memory address of external device access and 4 bus bit wide sums are compared, judge external equipment Whether the memory address of access is the integral multiple of 4 bus bit wide sums, and judges that external equipment needs the data sheet for accessing Whether the number of unit is more than or equal to 4, if the memory address of external device access be the integral multiple of 4 bus bit wide sums simultaneously And external equipment needs the number of the data cell for accessing to be more than or equal to 4, then execution step 210, otherwise, execution step 211.

Step 210：Read according to the memory address of external device access or 4 data cells of write, and according to the second number Value 4 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, by second Numerical value 4 is updated to the first numerical value 16, return to step 203；

Specifically, start to read or write 4 data cells from the memory address of external device access, according to second value 4 numbers for reducing the data cell that external equipment needs to access, and according to second value 4 and bus bit wide, according to equation below (2) increase the memory address of external device access, second value 4 is updated to the first numerical value 16, return to step 203,

Addr2=Addr1+buswidth/8*4 (2)

Wherein, in formula (2), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

Wherein, according to the concrete operations of the number of the data cell of the minimizing external equipment needs access of second value 4 it is：Will External equipment needs the number of the data cell for accessing to deduct second value 4.

Wherein, when the corresponding operation of the order of external device access internal memory is read operation, then set from outside in internal memory The standby memory address for accessing starts to read 4 data cells, when the corresponding operation of the order of external device access internal memory is to write behaviour When making, then start to write 4 data cells from the memory address of external device access in internal memory.

Wherein, start to read 4 data cells from the memory address of external device access in internal memory and be specially：In internal memory In, by 4 data cells started from the memory address of external device access by the bus transfer in terminal to external equipment.

Wherein, start to write 4 data units from the memory address of external device access in internal memory and be specially：In internal memory In, by 4 data cells carried in the order of external device access internal memory by the bus in terminal from external device access Memory address start to be transferred to internal memory.

Wherein, after reading or write 4 data cells according to the memory address of external device access, by the first depositor In external equipment need access data cell number be updated to reduce after data cell number, by the second depositor In external device access memory address be updated to increase after memory address.

Step 211：By second value 4 divided by 2, it is 2 to obtain third value, and second value is updated to third value 2；

Wherein, second value is updated to after third value 2, second value is just changed into 2.

Step 212：Whether the memory address for judging external device access is the integral multiple of 2 bus bit wide sums, and Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 2, if external device access Memory address be 2 bus bit wide sums integral multiple and external equipment need access data cell number more than or Second value 2 is equal to, then execution step 213, otherwise, execution step 214；

Specifically, the memory address of external device access and 2 bus bit wide sums are compared, judge external equipment Whether the memory address of access is the integral multiple of 2 bus bit wide sums, and judges that external equipment needs the data sheet for accessing Whether the number of unit is more than or equal to 2, if the memory address of external device access be the integral multiple of 2 bus bit wide sums simultaneously And external equipment needs the number of the data cell for accessing to be more than or equal to 2, then execution step 213, otherwise, execution step 214.

Step 213：Read according to the memory address of external device access or 2 data cells of write, and according to the second number Value 2 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, by second Numerical value 2 is updated to the first numerical value 16, return to step 203；

Specifically, start to read or write 2 data cells from the memory address of external device access, according to second value 2 numbers for reducing the data cell that external equipment needs to access, and according to second value 2 and bus bit wide, according to equation below (3) increase the memory address of external device access, second value 2 is updated to the first numerical value 16, return to step 203,

Addr2=Addr1+buswidth/8*2 (3)

Wherein, in formula (3), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

Wherein, according to the concrete operations of the number of the data cell of the minimizing external equipment needs access of second value 2 it is：Will External equipment needs the number of the data cell for accessing to deduct second value 2.

Wherein, when the corresponding operation of the order of external device access internal memory is read operation, then set from outside in internal memory The standby memory address for accessing starts to read 2 data cells, when the corresponding operation of the order of external device access internal memory is to write behaviour When making, then start to write 2 data cells from the memory address of external device access in internal memory.

Wherein, start to read 2 data cells from the memory address of external device access in internal memory and be specially：In internal memory In, by 2 data cells started from the memory address of external device access by the bus transfer in terminal to external equipment.

Wherein, start to write 2 data units from the memory address of external device access in internal memory and be specially：In internal memory In, by 2 data cells carried in the order of external device access internal memory by the bus in terminal from external device access Memory address start to be transferred to internal memory.

Wherein, after reading or write 2 data cells according to the memory address of external device access, by the first depositor In external equipment need access data cell number be updated to reduce after data cell number, by the second depositor In external device access memory address be updated to increase after memory address.

Step 214：By second value 2 divided by 2, it is 1 to obtain third value, and second value is updated to third value 1；

Wherein, second value is updated to after third value 1, second value is just changed into 1.

Step 215：Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 1, If it is, execution step 216, otherwise, end operation；

Specifically, the number and second value 1 that external equipment is needed the data cell for accessing is compared, if outside Equipment needs the number of the data cell for accessing to be more than or equal to 1, then execution step 216, otherwise, end operation.

Step 216：Read according to the memory address of external device access or 1 data cell of write, and according to the second number Value 1 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, by second Numerical value 1 is updated to the first numerical value 16, return to step 203.

Specifically, start to read or write 1 data cell from the memory address of external device access, according to second value 1 number for reducing the data cell that external equipment needs to access, and according to second value 1 and bus bit wide, according to equation below (4) increase the memory address of external device access, second value 1 is updated to the first numerical value 16, return to step 203,

Addr2=Addr1+buswidth/8*1 (4)

Wherein, in formula (4), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

Wherein, according to the concrete operations of the number of the data cell of the minimizing external equipment needs access of second value 1 it is：Will External equipment needs the number of the data cell for accessing to deduct second value 1.

Wherein, when the corresponding operation of the order of external device access internal memory is read operation, then set from outside in internal memory The standby memory address for accessing starts to read 1 data cell, when the corresponding operation of the order of external device access internal memory is to write behaviour When making, then start to write 1 data cell from the memory address of external device access in internal memory.

Wherein, start to read 1 data cell from the memory address of external device access in internal memory and be specially：In internal memory In, by 1 data cell started from the memory address of external device access by the bus transfer in terminal to external equipment.

Wherein, start to write 1 data unit from the memory address of external device access in internal memory and be specially：In internal memory In, by 1 data cell carried in the order of external device access internal memory by the bus in terminal from external device access Memory address start to be transferred to internal memory.

Wherein, after reading or write 1 data cell according to the memory address of external device access, by the first depositor In external equipment need access data cell number be updated to reduce after data cell number, by the second depositor In external device access memory address be updated to increase after memory address.

A kind of method for accessing internal memory is embodiments provided, referring to Fig. 3, method flow includes：

Step 301：The order of the access internal memory that external equipment sends is received, is carried outside this in the order of the access internal memory Equipment needs the number of the data cell for accessing and the memory address for accessing；

Step 302：According to the idle bandwidth of terminal internal bus, determine that the first numerical value and second value, the first numerical value are equal to Second value, if the first numerical value and second value are 8；

Specifically, according to the bandwidth that terminal internal bus is idle, determine the bandwidth belonging to the idle bandwidth of terminal internal bus Scope, the bandwidth range according to belonging to the bandwidth of the bus free for determining are right from the bandwidth range for having stored and the first numerical value Corresponding first numerical value of bandwidth of the bus free in should being related to, is obtained, and determines second value, the first numerical value and second value Equal, the first numerical value and second value both greater than or equal to 1 and be all 2 index power, if the first numerical value and second value It is 8.

Wherein, the corresponding relation of the first numerical value and control signal is preserved in advance, when the first numerical value for determining is 8, to CPU Send 8 corresponding control signal of the first numerical value, make CPU execute the corresponding block8 operations of the first numerical value 8, block8 operations be from Read in internal memory or write 8 data cells.

Step 303：Whether the memory address for judging external device access is the integral multiple of 8 bus bit wide sums, and Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 8, if external device access Memory address be 8 bus bit wide sums integral multiple and external equipment need access data cell number more than or Second value 8 is equal to, then execution step 304, otherwise, execution step 305；

Specifically, the memory address of external device access and 8 bus bit wide sums are compared, judge external equipment Whether the memory address of access is the integral multiple of 8 bus bit wide sums, and judges that external equipment needs the data sheet for accessing Whether the number of unit is more than or equal to 8, if the memory address of external device access be the integral multiple of 8 bus bit wide sums simultaneously And external equipment needs the number of the data cell for accessing to be more than or equal to 8, then execution step 304, otherwise, execution step 305.

Step 304：Read according to the memory address of external device access or 8 data cells of write, and according to the second number Value 8 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, will determine Second value 8 be updated to the first numerical value 8, return to step 303；

Specifically, start to read or write 8 data cells from the memory address of external device access, according to second value 8 numbers for reducing the data cell that external equipment needs to access, and according to second value 8 and bus bit wide, according to equation below (5) increase the memory address of external device access, second value 8 is updated to the first numerical value 8, return to step 303,

Addr2=Addr1+buswidth/8*8 (5)

Wherein, in formula (5), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

Step 305：By second value 8 divided by 2, it is 4 to obtain third value, and second value is updated to third value 4；

Step 306：Whether the memory address for judging external device access is the integral multiple of 4 bus bit wide sums, and Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 4, if external device access Memory address be 4 bus bit wide sums integral multiple and external equipment need access data cell number more than or Second value 4 is equal to, then execution step 307, otherwise, execution step 308；

Specifically, the memory address of external device access and 4 bus bit wide sums are compared, judge external equipment Whether the memory address of access is the integral multiple of 4 bus bit wide sums, and judges that external equipment needs the data sheet for accessing Whether the number of unit is more than or equal to 4, if the memory address of external device access be the integral multiple of 4 bus bit wide sums simultaneously And external equipment needs the number of the data cell for accessing to be more than or equal to 4, then execution step 307, otherwise, execution step 308.

Step 307：Read according to the memory address of external device access or 4 data cells of write, and according to the second number Value 4 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, by second Numerical value 4 is updated to the first numerical value 8, return to step 303；

Specifically, start to read or write 4 data cells from the memory address of external device access, according to second value 4 numbers for reducing the data cell that external equipment needs to access, and according to second value 4 and bus bit wide, according to equation below (6) increase the memory address of external device access, second value 4 is updated to the first numerical value 8, return to step 303,

Addr2=Addr1+buswidth/8*4 (6)

Wherein, in formula (6), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

Step 308：By second value 4 divided by 2, it is 2 to obtain third value, and second value is updated to third value 2；

Step 309：Whether the memory address for judging external device access is the integral multiple of 2 bus bit wide sums, and Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 2, if external device access Memory address be 2 bus bit wide sums integral multiple and external equipment need access data cell number more than or Second value 2 is equal to, then execution step 310, otherwise, execution step 311；

Specifically, the memory address of external device access and 2 bus bit wide sums are compared, judge external equipment Whether the memory address of access is the integral multiple of 2 bus bit wide sums, and judges that external equipment needs the data sheet for accessing Whether the number of unit is more than or equal to 2, if the memory address of external device access be the integral multiple of 2 bus bit wide sums simultaneously And external equipment needs the number of the data cell for accessing to be more than or equal to 2, then execution step 310, otherwise, execution step 311.

Step 310：Read according to the memory address of external device access or 2 data cells of write, and according to the second number Value 2 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, by second Numerical value 2 is updated to the first numerical value 8, return to step 303；

Specifically, start to read or write 2 data cells from the memory address of external device access, according to second value 2 numbers for reducing the data cell that external equipment needs to access, and according to second value 2 and bus bit wide, according to equation below (7) increase the memory address of external device access, second value 2 is updated to the first numerical value 8, return to step 303,

Addr2=Addr1+buswidth/8*2 (7)

Wherein, in formula (7), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

Step 311：By second value 2 divided by 2, it is 1 to obtain third value, and second value is updated to third value 1；

Step 312：Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 1, If it is, execution step 313, otherwise, end operation；

Specifically, the number and second value 1 that external equipment is needed the data cell for accessing is compared, if outside Equipment needs the number of the data cell for accessing to be more than or equal to 1, then execution step 313, otherwise, end operation.

Step 313：Read according to the memory address of external device access or 1 data cell of write, and according to the second number Value 1 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, by second Numerical value 1 is updated to the first numerical value 8, return to step 303.

Specifically, start to read or write 1 data cell from the memory address of external device access, according to second value 1 number for reducing the data cell that external equipment needs to access, and according to second value 1 and bus bit wide, according to equation below (8) increase the memory address of external device access, second value 1 is updated to the first numerical value 8, return to step 303,

Addr2=Addr1+buswidth/8*1 (8)

Wherein, in formula (8), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

A kind of method for accessing internal memory is embodiments provided, referring to Fig. 4, method flow includes：

Step 401：The order of the access internal memory that external equipment sends is received, is carried outside this in the order of the access internal memory Equipment needs the number of the data cell for accessing and the memory address for accessing；

Step 402：According to the idle bandwidth of terminal internal bus, determine that the first numerical value and second value, the first numerical value are equal to Second value, if the first numerical value and second value are 4；

Specifically, according to the bandwidth that terminal internal bus is idle, determine the bandwidth belonging to the idle bandwidth of terminal internal bus Scope, the bandwidth range according to belonging to the bandwidth of the bus free for determining are right from the bandwidth range for having stored and the first numerical value Corresponding first numerical value of bandwidth of the bus free in should being related to, is obtained, and determines second value, the first numerical value and second value Equal, the first numerical value and second value both greater than or equal to 1 and be all 2 index power, if the first numerical value and second value It is 4.

Wherein, the corresponding relation of the first numerical value and control signal is preserved in advance, when the first numerical value for determining is 4, to CPU Send 4 corresponding control signal of the first numerical value, make CPU execute the corresponding block4 operations of the first numerical value 4, block4 operations be from Read in internal memory or write 4 data cells.

Step 403：Whether the memory address for judging external device access is the integral multiple of 4 bus bit wide sums, and Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 4, if external device access Memory address be 4 bus bit wide sums integral multiple and external equipment need access data cell number more than or Second value 4 is equal to, then execution step 404, otherwise, execution step 405；

Specifically, the memory address of external device access and 4 bus bit wide sums are compared, judge external equipment Whether the memory address of access is the integral multiple of 4 bus bit wide sums, and judges that external equipment needs the data sheet for accessing Whether the number of unit is more than or equal to 4, if the memory address of external device access be the integral multiple of 4 bus bit wide sums simultaneously And external equipment needs the number of the data cell for accessing to be more than or equal to 4, then execution step 404, otherwise, execution step 405.

Step 404：Read according to the memory address of external device access or 4 data cells of write, and according to the second number Value 4 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, will determine Second value 4 be updated to the first numerical value 4, return to step 403；

Specifically, start to read or write 4 data cells from the memory address of external device access, according to second value 4 numbers for reducing the data cell that external equipment needs to access, and according to second value 4 and bus bit wide, according to equation below (9) increase the memory address of external device access, second value 4 is updated to the first numerical value 4, return to step 403,

Addr2=Addr1+buswidth/8*4 (9)

Wherein, in formula (9), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

Step 405：By second value 4 divided by 2, it is 2 to obtain third value, and second value is updated to third value 2；

Step 406：Whether the memory address for judging external device access is the integral multiple of 2 bus bit wide sums, and Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 2, if external device access Memory address be 2 bus bit wide sums integral multiple and external equipment need access data cell number more than or Second value 2 is equal to, then execution step 407, otherwise, execution step 408；

Specifically, the memory address of external device access and 2 bus bit wide sums are compared, judge external equipment Whether the memory address of access is the integral multiple of 2 bus bit wide sums, and judges that external equipment needs the data sheet for accessing Whether the number of unit is more than or equal to 2, if the memory address of external device access be the integral multiple of 2 bus bit wide sums simultaneously And external equipment needs the number of the data cell for accessing to be more than or equal to 2, then execution step 407, otherwise, execution step 408.

Step 407：Read according to the memory address of external device access or 2 data cells of write, and according to the second number Value 2 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, by second Numerical value 2 is updated to the first numerical value 4, return to step 403；

Specifically, start to read or write 2 data cells from the memory address of external device access, according to second value 2 numbers for reducing the data cell that external equipment needs to access, and according to second value 2 and bus bit wide, according to equation below (10) increase the memory address of external device access, second value 2 is updated to the first numerical value 4, return to step 403,

Addr2=Addr1+buswidth/8*2 (10)

Wherein, in formula (10), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

Step 408：By second value 2 divided by 2, it is 1 to obtain third value, and second value is updated to third value 1；

Step 409：Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 1, If it is, execution step 410, otherwise, end operation；

Specifically, the number and second value 1 that external equipment is needed the data cell for accessing is compared, if outside Equipment needs the number of the data cell for accessing to be more than or equal to 1, then execution step 410, otherwise, end operation.

Step 410：Read according to the memory address of external device access or 1 data cell of write, and according to the second number Value 1 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, by second Numerical value 1 is updated to the first numerical value 4, return to step 403.

Specifically, start to read or write 1 data cell from the memory address of external device access, according to second value 1 number for reducing the data cell that external equipment needs to access, and according to second value 1 and bus bit wide, according to equation below (11) increase the memory address of external device access, second value 1 is updated to the first numerical value 4, return to step 403,

Addr2=Addr1+buswidth/8*1 (11)

Wherein, in formula (11), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

A kind of method for accessing internal memory is embodiments provided, referring to Fig. 5, method flow includes：

Step 501：The order of the access internal memory that external equipment sends is received, is carried outside this in the order of the access internal memory Equipment needs the number of the data cell for accessing and the memory address for accessing；

Step 502：According to the idle bandwidth of terminal internal bus, determine that the first numerical value and second value, the first numerical value are equal to Second value, if the first numerical value and second value are 2；

Specifically, according to the bandwidth that terminal internal bus is idle, determine the bandwidth belonging to the idle bandwidth of terminal internal bus Scope, the bandwidth range according to belonging to the bandwidth of the bus free for determining are right from the bandwidth range for having stored and the first numerical value Corresponding first numerical value of bandwidth of the bus free in should being related to, is obtained, and determines second value, the first numerical value and second value Equal, the first numerical value and second value both greater than or equal to 1 and be all 2 index power, if the first numerical value and second value It is 2.

Wherein, the corresponding relation of the first numerical value and control signal is preserved in advance, when the first numerical value for determining is 2, to CPU Send 2 corresponding control signal of the first numerical value, make CPU execute the corresponding block2 operations of the first numerical value 2, block2 operations be from Read in internal memory or write 2 data cells.

Step 503：Whether the memory address for judging external device access is the integral multiple of 2 bus bit wide sums, and Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 2, if external device access Memory address be 2 bus bit wide sums integral multiple and external equipment need access data cell number more than or Second value 2 is equal to, then execution step 504, otherwise, execution step 505；

Specifically, the memory address of external device access and 2 bus bit wide sums are compared, judge external equipment Whether the memory address of access is the integral multiple of 2 bus bit wide sums, and judges that external equipment needs the data sheet for accessing Whether the number of unit is more than or equal to 2, if the memory address of external device access be the integral multiple of 2 bus bit wide sums simultaneously And external equipment needs the number of the data cell for accessing to be more than or equal to 2, then execution step 504, otherwise, execution step 505.

Step 504：Read according to the memory address of external device access or 2 data cells of write, and according to the second number Value 2 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, will determine Second value 2 be updated to the first numerical value 2, return to step 503；

Specifically, start to read or write 2 data cells from the memory address of external device access, according to second value 2 numbers for reducing the data cell that external equipment needs to access, and according to second value 2 and bus bit wide, according to equation below (12) increase the memory address of external device access, second value 2 is updated to the first numerical value 2, return to step 503,

Addr2=Addr1+buswidth/8*2 (12)

Wherein, in formula (12), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

Step 505：By second value 2 divided by 2, it is 1 to obtain third value, and second value is updated to third value 1；

Step 506：Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 1, If it is, execution step 507, otherwise, end operation；

Specifically, the number and second value 1 that external equipment is needed the data cell for accessing is compared, if outside Equipment needs the number of the data cell for accessing to be more than or equal to 1, then execution step 507, otherwise, end operation.

Step 507：Read according to the memory address of external device access or 1 data cell of write, and according to the second number Value 1 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, by second Numerical value 1 is updated to the first numerical value 2, return to step 503.

Specifically, start to read or write 1 data cell from the memory address of external device access, according to second value 1 number for reducing the data cell that external equipment needs to access, and according to second value 1 and bus bit wide, according to equation below (13) increase the memory address of external device access, second value 1 is updated to the first numerical value 2, return to step 503,

Addr2=Addr1+buswidth/8*1 (13)

Wherein, in formula (13), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

A kind of method for accessing internal memory is embodiments provided, referring to Fig. 6, method flow includes：

Step 601：The order of the access internal memory that external equipment sends is received, is carried outside this in the order of the access internal memory Equipment needs the number of the data cell for accessing and the memory address for accessing；

Step 602：According to the idle bandwidth of terminal internal bus, determine that the first numerical value and second value, the first numerical value are equal to Second value, if the first numerical value and second value are 1；

Specifically, according to the bandwidth that terminal internal bus is idle, determine the bandwidth belonging to the idle bandwidth of terminal internal bus Scope, the bandwidth range according to belonging to the bandwidth of the bus free for determining are right from the bandwidth range for having stored and the first numerical value Corresponding first numerical value of bandwidth of the bus free in should being related to, is obtained, and determines second value, the first numerical value and second value Both greater than or equal to 1 and be all 2 index power, if the first numerical value and second value are 1.

Wherein, the corresponding relation of the first numerical value and control signal is preserved in advance, when the first numerical value for determining is 1, to CPU Send 1 corresponding control signal of the first numerical value, make CPU execute the corresponding single operations of the first numerical value 1, single operations be from Read in internal memory or write 1 data cell.

Step 603：Judge that whether external equipment needs the number of the data cell for accessing more than or equal to second value 1, If it is, execution step 604, otherwise, end operation；

Specifically, the number and numerical value 1 that external equipment is needed the data cell for accessing is compared, and judges external equipment Need whether the number of the data cell for accessing is more than or equal to 1, if external equipment needs the number of the data cell for accessing It is more than or equal to 1, then execution step 604, otherwise, end operation.

Step 604：Read according to the memory address of external device access or 1 data cell of write, and according to the second number Value 1 reduces external equipment to be needed the number of the data cell for accessing and increases the memory address of external device access, will determine Second value 1 be updated to the first numerical value 1, return to step 603；

Specifically, start to read or write 1 data cell from the memory address of external device access, according to second value 1 number for reducing the data cell that external equipment needs to access, and according to second value 1 and bus bit wide, according to equation below (14) increase the memory address of external device access, second value 1 is updated to the first numerical value 1, return to step 603,

Addr2=Addr1+buswidth/8*1 (14)

Wherein, in formula (14), Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing External device access memory address, buswidth be bus bit wide.

A kind of equipment for accessing internal memory is embodiments provided, referring to Fig. 7, the equipment includes：

Receiver module 701, for receiving the order of the access internal memory of external equipment transmission, carries in the order outside this and sets The number of the standby data cell for needing to access and the memory address for accessing；

Determining module 702, for according to the idle bandwidth of terminal internal bus, determining the first numerical value and second value, described First numerical value is equal to the second value, first numerical value and the second value both greater than or equal to 1 and be all 2 index Power；

Read or writing module 703, if being the second value bus bit wide sum for the memory address The number of integral multiple and the data cell is more than or equal to the second value, then read according to the memory address or write The second value data cell, reduces the number of the data cell according to the second value and increases the internal memory The second value is updated to first numerical value, returns this module 703 by address；

Module 704 is reduced, if not being the integer of the second value bus bit wide sum for the memory address Times or the data cell number less than the second value and more than or equal to 1, then the second value is obtained divided by 2 The second value is updated to the third value by third value, is returned and is read or writing module.

Wherein it is determined that module 702 includes：

First determining unit, for according to the idle bandwidth of terminal internal bus, determining belonging to the bandwidth of the bus free Bandwidth range；

Wherein, read or writing module 703 includes：

Adding unit, for according to second value, the memory address of the external device access and bus bit wide, according to as follows Formula increases the memory address of the external device access,

Addr2=Addr1+buswidth/8*n

Wherein, in formula, Addr2 is the memory address of the external device access after increasing, and Addr1 is outer before increasing The memory address that portion's equipment is accessed, buswidth are bus bit wide, and n is second value.

Further, the equipment also includes：

First memory module, for needing the number of the data cell for accessing to be stored in the first depositor by external equipment In；

Second memory module, for the memory address of external device access is stored in the second depositor.

Further, the equipment also includes：

First update module, for being updated to the data after reducing by the number of the data cell stored in the first depositor The number of unit；

Second update module, for the internal memory ground after being updated to increase by the memory address stored in the second depositor Location.

A kind of equipment for accessing internal memory is embodiments provided, referring to Fig. 8, the equipment includes：

Memorizer 801 and processor 802, for executing the following method for accessing internal memory：

Wherein, the bandwidth idle according to terminal internal bus, determines the first numerical value and second value, first numerical value The second value is equal to, including：

Wherein, number and the increase memory address for reducing the data cell according to the second value, Including：

Addr2=Addr1+buswidth/8*n

Further, after the order for receiving the access internal memory that external equipment sends, also include：

Further, number and the increase internal memory ground for reducing the data cell according to the second value After location, also include：

One of ordinary skill in the art will appreciate that realizing that all or part of step of above-described embodiment can pass through hardware To complete, it is also possible to which the hardware for being instructed correlation by program is completed, and described program can be stored in a kind of computer-readable In storage medium, storage medium mentioned above can be read only memory, disk or CD etc..

The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all spirit in the present invention and Within principle, any modification, equivalent substitution and improvements that is made etc. should be included within the scope of the present invention.

Claims

1. a kind of access internal memory method, it is characterised in that methods described includes：

The first step, receives the order of the access internal memory that external equipment sends, and carrying the external equipment in the order needs to visit The number of the data cell that asks and the memory address for accessing；

Second step, according to the idle bandwidth of terminal internal bus, determines the bandwidth range belonging to the bandwidth of the bus free；Root According to the bus free bandwidth belonging to bandwidth range, from the corresponding relation of the bandwidth range for having stored and the first numerical value Determine corresponding first numerical value of bandwidth of the bus free, and determine second value, first numerical value is equal to described second Numerical value, first numerical value and the second value both greater than or equal to 1 and be all 2 index power；

3rd step, if the corresponding numerical value of the memory address is the corresponding numerical value of the second value bus bit wide sum The number of integral multiple and the data cell is more than or equal to the second value, then read according to the memory address or write The second value data cell, reduces the individual of the data cell that the external equipment needs are accessed according to the second value Count and increase the corresponding numerical value of the memory address, the second value is updated to first numerical value, this step is returned；

4th step, if the corresponding numerical value of the memory address is not the corresponding numerical value of the second value bus bit wide sum Integral multiple or the data cell number less than the second value and more than or equal to 1, then the second value is removed Third value is obtained with 2, the second value is updated to the third value, return the 3rd step.

2. method according to claim 1, it is characterised in that described the data cell is reduced according to the second value Number and increase the memory address, including：

The number of the data cell for needing to access the external equipment reduces the second value, described outer after being reduced Portion's equipment needs the number of the data cell for accessing；

According to the second value, the memory address of the external device access and bus bit wide, institute is increased according to equation below The memory address of external device access is stated,

Addr2=Addr1+buswidth/8*n

Wherein, in the formula, Addr2 is the memory address of the external device access after increasing, before Addr1 is for increasing The external device access memory address, buswidth be the bus bit wide, n be the second value.

3. method according to claim 1 and 2, it is characterised in that the access internal memory that the reception external equipment sends After order, also include：

4. method according to claim 3, it is characterised in that described the data cell is reduced according to the second value Number and after increasing the memory address, also include：

The number of the data cell stored in first depositor is updated to the individual of the data cell after minimizing Number；

5. a kind of access internal memory equipment, it is characterised in that the equipment includes：

Receiver module, for receiving the order of the access internal memory of external equipment transmission, carries the external equipment in the order Need the number of the data cell of access and the memory address for accessing；

Determining module, for according to the idle bandwidth of terminal internal bus, determining the bandwidth belonging to the bandwidth of the bus free Scope；Bandwidth range according to belonging to the bandwidth of the bus free, from the right of the bandwidth range for having stored and the first numerical value Corresponding first numerical value of the middle bandwidth for determining the bus free should be related to, and determine second value, first numerical value and institute Second value is stated both greater than or equal to 1 and be all 2 index power；

Read or writing module, if being the second value bus bit wide sum for the corresponding numerical value of the memory address The number of the integral multiple of corresponding numerical value and the data cell is more than or equal to the second value, then according to internal memory ground Location is read or writes the second value data cell, and reducing the external equipment according to the second value needs access The second value is updated to first number by the number of data cell and the corresponding numerical value of the increase memory address Value, returns this module；

Module is reduced, if not being that the second value bus bit wide sum is corresponding for the corresponding numerical value of the memory address Numerical value integral multiple or the data cell number less than the second value and be more than or equal to 1, then by described second Numerical value obtains third value divided by 2, and the second value is updated to the third value, returns and reads or writing module.

6. equipment according to claim 5, it is characterised in that the reading or writing module include：

Read or writing unit, if for the memory address be the second value bus bit wide sum integral multiple and The number of the data cell is more than or equal to the second value, then read according to the memory address or write described second The second value is updated to first numerical value by numerical value data cell；

First reduces unit, for the external equipment being needed the number of the data cell for accessing reduce the second value, The external equipment after being reduced needs the number of the data cell for accessing；

Adding unit, for according to the second value, the memory address of the external device access and bus bit wide, according to such as Lower formula increases the memory address of the external device access,

Addr2=Addr1+buswidth/8*n

7. the equipment according to claim 5 or 6, it is characterised in that the equipment also includes：

First memory module, for needing the number of the data cell for accessing to be stored in the first depositor by external equipment；

8. equipment according to claim 7, it is characterised in that the equipment also includes：

First update module, after being updated to reduce by the number of the data cell stored in first depositor The number of data cell；

Second update module, for the internal memory ground after being updated to increase by the memory address stored in second depositor Location.

9. a kind of equipment for accessing internal memory, it is characterised in that the equipment includes memorizer and processor, for executing such as right The method for requiring a kind of access internal memory described in 1 to 4 any claim.