CN103853675A

CN103853675A - Method and equipment for accessing memory

Info

Publication number: CN103853675A
Application number: CN201210520124.3A
Authority: CN
Inventors: 赵长虹; 苏健
Original assignee: HiSilicon Technologies Co Ltd
Current assignee: HiSilicon Technologies Co Ltd
Priority date: 2012-12-06
Filing date: 2012-12-06
Publication date: 2014-06-11
Anticipated expiration: 2032-12-06
Also published as: CN103853675B

Abstract

The invention discloses a method and equipment for accessing a memory, and belongs to the field of computers. The method comprises the steps of 1, receiving a command which is sent by external equipment and is used for accessing the memory, wherein the command carries the number of data units to be accessed by the external equipment and a to-be-accessed memory address; 2, determining a first value and a second value according to an unoccupied bandwidth of a bus; 3, if the memory address is an integral multiple of the sum of bit widths of buses with the number of the second value and the number of the data units is greater than or equal to the second value, reading or writing the second value of the data units, reducing the number of the data units, increasing the memory address, updating the second value to be the first value, and returning to the start of the step; 4, if the memory address is not the integral multiple of the sum of bit widths of buses with the number of the second value and the number of the data units is smaller than the second value and greater than or equal to 1, dividing the second value by 2 to obtain a third value, updating the second value to be the third value, and returning to the third step. According to the method disclosed by the invention, the memory access efficiency is improved.

Description

A kind of method and apparatus of access memory

Technical field

The present invention relates to computer realm, particularly a kind of method and apparatus of access memory.

Background technology

In computer system, computing machine conducts interviews frequently to internal memory, and the operation of access memory comprises read operation and write operation.

At present, the method of access memory is specially: receive the order of the access memory of external unit transmission, in this order, carry the number of data cell and the memory address of access that external unit need to be accessed, if this order correspondence be operating as read operation, the memory address of external device access is the integral multiple of 4 bus bit wide sums, and the number of the data cell that need to access of external unit is more than or equal to 4, the memory address of accessing from external unit in internal memory starts to read 4 data cells, if the memory address of external device access is not the integral multiple of 4 bus bit wide sums, or the number of the data cell that need to access of external unit is less than 4, in internal memory, start to read 1 data cell from the memory address of external device access, if the number that is operating as the data cell that write operation and external unit need to access of this order correspondence is more than or equal to 1, the memory address of accessing from external unit in internal memory starts to write 1 data cell.

Realizing in process of the present invention, inventor finds that prior art at least exists following problem:

If not being the integral multiple of 4 bus bit wide sums or the number of the data cell that external unit need to be accessed, the memory address that external unit is accessed is less than at 4 o'clock, the memory address of accessing from external unit in internal memory starts to read 1 data cell, if the number of the data cell that external unit need to be accessed is more than or equal to 1, the memory address of accessing from external unit in internal memory starts to write 1 data cell, and the mode of access memory can reduce the efficiency of access memory like this.

Summary of the invention

In order to solve the problem of prior art, the embodiment of the present invention provides a kind of method and apparatus of access memory.Described technical scheme is as follows:

First aspect, a kind of method of access memory, described method comprises:

The first step, receives the order of the access memory of external unit transmission, carries the number of data cell and the memory address of access that described external unit need to be accessed in described order;

Second step, according to the bandwidth of terminal internal bus free time, determines the first numerical value and second value, and described the first numerical value equals described second value, and described the first numerical value and described second value are all more than or equal to 1 and be all 2 index power;

The 3rd step, if being a described second value integral multiple of bus bit wide sum and the number of described data cell, described memory address is more than or equal to described second value, read or write a described second value data cell according to described memory address, reduce the number of described data cell and increase described memory address according to described second value, described second value is updated to described the first numerical value, returns to this step;

The 4th step, be less than described second value and be more than or equal to 1 if described memory address is not a described second value integral multiple of bus bit wide sum or the number of described data cell, described second value is obtained to third value divided by 2, described second value is updated to described third value, returns to the 3rd step.

In conjunction with first aspect, in the possible implementation of the first of above-mentioned first aspect, described according to the bandwidth of terminal internal bus free time, determine the first numerical value and second value, described the first numerical value equals described second value, comprising:

According to the bandwidth of terminal internal bus free time, determine the bandwidth range that the bandwidth of described bus free time belongs to;

The bandwidth range belonging to according to the bandwidth of described bus free time, from the corresponding relation of the bandwidth range stored and the first numerical value, determine the first numerical value corresponding to bandwidth of described bus free time, and definite second value, described the first numerical value equals described second value.

In conjunction with first aspect, in the possible implementation of the second of above-mentioned first aspect, describedly reduce the number of described data cell and increase described memory address according to described second value, comprising:

The number of the data cell that described external unit need to be accessed reduces described second value, the number of the data cell that the described external unit after being reduced need to be accessed;

According to the memory address of described second value, described external device access and bus bit wide, increase the memory address of described external device access according to following formula,

Addr2=Addr1+buswidth/8*n

Wherein, in described formula, Addr2 is the memory address of the described external device access after increasing, and Addr1 is the memory address of the described external device access before increasing, and buswidth is described bus bit wide, and n is described second value.

Any possible implementation in conjunction with first aspect to the possible implementation of the second of first aspect, in the third possible implementation of above-mentioned first aspect, after the order of the access memory that described reception external unit sends, also comprises:

The number of the data cell that described external unit need to be accessed is stored in the first register;

The memory address of described external device access is stored in the second register.

In conjunction with the third possible implementation of first aspect, in the 4th kind of possible implementation of above-mentioned first aspect, described reduce the number of described data cell and increase described memory address according to described second value after, also comprise:

The number of the described data cell of storing in described the first register is updated to the number of the described data cell after minimizing;

The described memory address of storing in described the second register is updated to the described memory address after increase.

Second aspect, a kind of equipment of access memory, described equipment comprises:

Receiver module, the order of access memory sending for receiving external unit, carries the number of data cell and the memory address of access that described external unit need to be accessed in described order;

Determination module, for according to the bandwidth of terminal internal bus free time, determines the first numerical value and second value, and described the first numerical value equals described second value, and described the first numerical value and described second value are all more than or equal to 1 and be all 2 index power;

Read or writing module, if be that a described second value integral multiple of bus bit wide sum and the number of described data cell are more than or equal to described second value for described memory address, read or write a described second value data cell according to described memory address, reduce the number of described data cell and increase described memory address according to described second value, described second value is updated to described the first numerical value, returns to this module;

Reduce module, if be not that a described second value integral multiple of bus bit wide sum or the number of described data cell are less than described second value and are more than or equal to 1 for described memory address, described second value is obtained to third value divided by 2, described second value is updated to described third value, returns and read or writing module.

In conjunction with second aspect, in the possible implementation of the first of above-mentioned second aspect, described determination module comprises:

The first determining unit, for according to the bandwidth of terminal internal bus free time, determines the bandwidth range that the bandwidth of described bus free time belongs to;

The second determining unit, for the bandwidth range belonging to according to the bandwidth of described bus free time, from the corresponding relation of the bandwidth range stored and the first numerical value, determine the first numerical value corresponding to bandwidth of described bus free time, and definite second value, described the first numerical value equals described second value.

In conjunction with second aspect, in the possible implementation of the second of above-mentioned second aspect, described in read or writing module comprises:

Read or writing unit, if be that a described second value integral multiple of bus bit wide sum and the number of described data cell are more than or equal to described second value for described memory address, read or write a described second value data cell according to described memory address, described second value is updated to described the first numerical value;

First reduces unit, reduces described second value, the number of the data cell that the described external unit after being reduced need to be accessed for the number of data cell that described external unit need to be accessed;

Increase unit, for according to the memory address of described second value, described external device access and bus bit wide, increase the memory address of described external device access according to following formula,

Addr2=Addr1+buswidth/8*n

Any possible implementation in conjunction with second aspect to the possible implementation of the second of second aspect, in the third possible implementation of above-mentioned second aspect, described equipment also comprises:

The first memory module, is stored in the first register for the number of data cell that described external unit need to be accessed;

The second memory module, for being stored in the second register by the memory address of described external device access.

In conjunction with the third possible implementation of second aspect, in the 4th kind of possible implementation of above-mentioned second aspect, described equipment also comprises:

The first update module, is updated to the number of the described data cell after minimizing for the number of described data cell that described the first register is stored;

The second update module, is updated to the described memory address after increase for the described memory address that described the second register is stored.

The third aspect, a kind of equipment of access memory, described equipment comprises storer and processor, for carrying out the method for described a kind of access memory.

In embodiments of the present invention, the first step, receives the order of the access memory of external unit transmission, carries the number of data cell and the memory address of access that external unit need to be accessed in this order; Second step, according to the bandwidth of terminal internal bus free time, determines the first numerical value and second value, and the first numerical value equals second value, and the first numerical value and second value are all more than or equal to 1 and be all 2 index power; The 3rd step, if being the integral multiple of a described second value bus bit wide sum and the number of data cell, memory address is more than or equal to second value, read or write a second value data cell according to described memory address, reduce the number of data cell and increase memory address according to second value, second value is updated to the first numerical value, returns to this step; The 4th step, be less than second value and be more than or equal to 1 if memory address is not a second value integral multiple of bus bit wide sum or the number of data cell, second value is obtained to third value divided by 2, second value is updated to third value, return to the 3rd step.Wherein, when the memory address of external device access is not that a second value integral multiple of bus bit wide sum or the number of this data cell are while being less than second value, can be not immediately will not determine that second value is reduced to 1 and read or write 1 data cell, so, can improve the efficiency of access memory.

Brief description of the drawings

Fig. 1 is the method flow diagram of a kind of access memory of providing of the embodiment of the present invention;

Fig. 2 is the method flow diagram of the another kind of access memory that provides of the embodiment of the present invention;

Fig. 3 is the method flow diagram of the another kind of access memory that provides of the embodiment of the present invention;

Fig. 4 is the method flow diagram of the another kind of access memory that provides of the embodiment of the present invention;

Fig. 5 is the method flow diagram of the another kind of access memory that provides of the embodiment of the present invention;

Fig. 6 is the method flow diagram of the another kind of access memory that provides of the embodiment of the present invention;

Fig. 7 is the apparatus structure schematic diagram of a kind of access memory of providing of the embodiment of the present invention;

Fig. 8 is the apparatus structure schematic diagram of the another kind of access memory that provides of the embodiment of the present invention.

Embodiment

For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.

The embodiment of the present invention provides a kind of method of access memory, and referring to Fig. 1, method flow comprises:

Step 101: receive the order of the access memory of external unit transmission, carry the number of data cell and the memory address of access that this external unit need to be accessed in this order;

Step 102: according to the bandwidth of terminal internal bus free time, determine the first numerical value and second value, the first numerical value equals second value, the first numerical value and second value are all more than or equal to 1 and be all 2 index power;

Step 103: be more than or equal to second value if memory address is the integral multiple of a second value bus bit wide sum and the number of data cell, read or write a second value data cell according to memory address, reduce the number of data cell and increase memory address according to second value, second value is updated to the first numerical value, returns to this step;

Step 104: be less than second value and be more than or equal to 1 if memory address is not a second value integral multiple of bus bit wide sum or the number of data cell, second value is obtained to third value divided by 2, second value is updated to third value, returns to step 103.

In embodiments of the present invention, the first step, receives the order of the access memory of external unit transmission, carries the number of data cell and the memory address of access that external unit need to be accessed in this order; Second step, according to the bandwidth of terminal internal bus free time, determines the first numerical value and second value, and the first numerical value equals second value, and the first numerical value and second value are all more than or equal to 1 and be all 2 index power; The 3rd step, if being the integral multiple of a second value bus bit wide sum and the number of data cell, memory address is more than or equal to second value, read or write a second value data cell according to memory address, reduce the number of data cell and increase memory address according to second value, second value is updated to the first numerical value, returns to this step; The 4th step, be less than second value and be more than or equal to 1 if memory address is not a second value integral multiple of bus bit wide sum or the number of data cell, second value is obtained to third value divided by 2, second value is updated to third value, return to the 3rd step.Wherein, when the memory address of external device access is not that a second value integral multiple of bus bit wide sum or the number of this data cell are while being less than second value, can be not immediately will not determine that second value is reduced to 1 and read or write 1 data cell, so, can improve the efficiency of access memory.

The embodiment of the present invention provides a kind of method of access memory, and referring to Fig. 2, method flow comprises:

Step 201: receive the order of the access memory of external unit transmission, carry the number of data cell and the memory address of access that this external unit need to be accessed in the order of this access memory;

Wherein, there is a maximal value in the number of the data cell that external unit need to be accessed, and the maximal value of the number of the data cell that in the present embodiment external unit need to be accessed describes taking 16 as example.

Wherein, in the present embodiment, the number of the data cell that external unit need to be accessed is more than or equal to 1 and be less than or equal to 16.

Wherein, the number of the data cell that this external unit carrying in the order of this access memory need to be accessed is stored in the first register, and the memory address of external device access is stored in the second register.

Wherein, the equal and opposite in direction of the size of a data cell and a bus bit wide.

Step 202: according to the bandwidth of terminal internal bus free time, determine the first numerical value and second value, the first numerical value equals second value, if the first numerical value and second value are 16;

Particularly, according to the bandwidth of terminal internal bus free time, determine the bandwidth range that the bandwidth of terminal internal bus free time belongs to, the bandwidth range belonging to according to the bandwidth of definite bus free time is from the corresponding relation of the bandwidth range stored and the first numerical value, obtain the first numerical value corresponding to bandwidth of this bus free time, and definite second value, the first numerical value and second value equate, the first numerical value and second value are all more than or equal to 1 and be all 2 index power, if the first numerical value and second value are 16.

Wherein, preserve in advance the corresponding relation of the first numerical value and control signal, in the time that the first numerical value of determining is 16, send the control signal of the first numerical value 16 correspondences to CPU, make CPU carry out the block16 operation of the first numerical value 16 correspondences, block16 is operating as and from internal memory, reads or write 16 data cells.

Step 203: whether the memory address that judges external device access is the integral multiple of 16 bus bit wide sums, and whether the number that judges the data cell that external unit need to access equals second value 16, if being the integral multiple of 16 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access equals second value 16, perform step 204, otherwise, execution step 205;

Particularly, the memory address of external device access and 16 bus bit wide sums are compared, whether the memory address that judges external device access is the integral multiple of 16 bus bit wide sums, and whether the number that judges the data cell that external unit need to access equals 16, if being the integral multiple of 16 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access equals 16, perform step 204, otherwise, execution step 205.

For example, the bit wide of bus is 128bit, be 16Byte, the number of the data cell that external unit need to be accessed is 16, 16 bus bit wide sums are 16*16Byte, 16 bus bit wide sums are 196Byte, the memory address that bus is accessed and 16 bus bit wide sum 196Byte comparison, judge whether the memory address that bus is accessed is the integral multiple of 16 bus bit wide sum 196Byte, and the number that judges the data cell that external unit need to access equals second value 16, if the memory address that bus is accessed is the integral multiple of 16 bus bit wide sum 196Byte, perform step 204.

Step 204: read or write 16 data cells of second value, end operation according to the memory address of external device access;

Wherein, when the order correspondence of external device access internal memory be operating as read operation time, in the order of external device access internal memory, carry the number of data cell and the memory address of access that external unit need to be accessed.

Wherein, when the order correspondence of external device access internal memory be operating as write operation time, in the order of external device access internal memory, except carrying the number of data cell and the memory address of access that external unit need to access, in this order, also carry the data cell that external unit need to be accessed.

Wherein, when the order correspondence of external device access internal memory be operating as read operation time, in internal memory, start to read 16 data cells from the memory address of external device access, when the order correspondence of external device access internal memory be operating as write operation time, in internal memory, start to write 16 data cells from the memory address of external device access.

Wherein, in internal memory, start to read 16 data cells from the memory address of external device access and be specially: internal memory, by 16 data cells that start from the memory address of external device access by the bus transfer in terminal to external unit.

Wherein, in internal memory, starting to write 16 data units from the memory address of external device access is specially: internal memory, 16 data cells of carrying in the order of external device access internal memory are started to be transferred to internal memory by the bus in terminal from the memory address of external device access.

Wherein, after reading or write 16 data cells of second value according to the memory address of external device access, by the data zero clearing in the first register and the second register.

Wherein, in the present embodiment, the maximal value of the number of the data cell that external unit need to be accessed is 16, and after reading or write 16 data cells according to the memory address of external device access, the data cell of external device access is 0, end operation.

Step 205: divided by 2, obtaining third value is 8, and second value is updated to third value 8 by second value 16;

Wherein, second value is updated to after third value 8, second value just becomes 8.

Step 206: whether the memory address that judges external device access is the integral multiple of 8 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to second value 8, if being the integral multiple of 8 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to second value 8, perform step 207, otherwise, execution step 208;

Particularly, the memory address of external device access and 8 bus bit wide sums are compared, whether the memory address that judges external device access is the integral multiple of 8 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to 8, if being the integral multiple of 8 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to 8, perform step 207, otherwise, execution step 208.

Step 207: read or write 8 data cells according to the memory address of external device access, and reduce according to second value 8 number of data cell and the memory address of increase external device access that external unit need to be accessed, second value 8 is updated to the first numerical value 16, returns to step 203;

Particularly, start to read or write 8 data cells from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 8, and according to second value 8 and bus bit wide, increase the memory address of external device access according to following formula (1), second value 8 is updated to the first numerical value 16, returns to step 203

Addr2=Addr1+buswidth/8*8 （1）

Wherein, in formula (1), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

Wherein, the concrete operations that reduce the number of the data cell that external unit need to access according to second value 8 are: the number of the data cell that external unit need to be accessed deducts second value 8.

Wherein, when the order correspondence of external device access internal memory be operating as read operation time, in internal memory, start to read 8 data cells from the memory address of external device access, when the order correspondence of external device access internal memory be operating as write operation time, in internal memory, start to write 8 data cells from the memory address of external device access.

Wherein, in internal memory, start to read 8 data cells from the memory address of external device access and be specially: internal memory, by 8 data cells that start from the memory address of external device access by the bus transfer in terminal to external unit.

Wherein, in internal memory, starting to write 8 data units from the memory address of external device access is specially: internal memory, 8 data cells of carrying in the order of external device access internal memory are started to be transferred to internal memory by the bus in terminal from the memory address of external device access.

Wherein, after reading or write 8 data cells according to the memory address of external device access, the number of the data cell that the external unit in the first register need to be accessed is updated to the number of the data cell after minimizing, and the memory address of the external device access in the second register is updated to the memory address after increase.

Step 208: divided by 2, obtaining third value is 4, and second value is updated to third value 4 by second value 8;

Wherein, second value is updated to after third value 4, second value just becomes 4.

Step 209: whether the memory address that judges external device access is the integral multiple of 4 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to second value 4, if being the integral multiple of 4 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to second value 4, perform step 210, otherwise, execution step 211;

Particularly, the memory address of external device access and 4 bus bit wide sums are compared, whether the memory address that judges external device access is the integral multiple of 4 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to 4, if being the integral multiple of 4 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to 4, perform step 210, otherwise, execution step 211.

Step 210: read or write 4 data cells according to the memory address of external device access, and reduce according to second value 4 number of data cell and the memory address of increase external device access that external unit need to be accessed, second value 4 is updated to the first numerical value 16, returns to step 203;

Particularly, start to read or write 4 data cells from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 4, and according to second value 4 and bus bit wide, increase the memory address of external device access according to following formula (2), second value 4 is updated to the first numerical value 16, returns to step 203

Addr2=Addr1+buswidth/8*4 （2）

Wherein, in formula (2), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

Wherein, the concrete operations that reduce the number of the data cell that external unit need to access according to second value 4 are: the number of the data cell that external unit need to be accessed deducts second value 4.

Wherein, when the order correspondence of external device access internal memory be operating as read operation time, in internal memory, start to read 4 data cells from the memory address of external device access, when the order correspondence of external device access internal memory be operating as write operation time, in internal memory, start to write 4 data cells from the memory address of external device access.

Wherein, in internal memory, start to read 4 data cells from the memory address of external device access and be specially: internal memory, by 4 data cells that start from the memory address of external device access by the bus transfer in terminal to external unit.

Wherein, in internal memory, starting to write 4 data units from the memory address of external device access is specially: internal memory, 4 data cells of carrying in the order of external device access internal memory are started to be transferred to internal memory by the bus in terminal from the memory address of external device access.

Wherein, after reading or write 4 data cells according to the memory address of external device access, the number of the data cell that the external unit in the first register need to be accessed is updated to the number of the data cell after minimizing, and the memory address of the external device access in the second register is updated to the memory address after increase.

Step 211: divided by 2, obtaining third value is 2, and second value is updated to third value 2 by second value 4;

Wherein, second value is updated to after third value 2, second value just becomes 2.

Step 212: whether the memory address that judges external device access is the integral multiple of 2 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to second value 2, if being the integral multiple of 2 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to second value 2, perform step 213, otherwise, execution step 214;

Particularly, the memory address of external device access and 2 bus bit wide sums are compared, whether the memory address that judges external device access is the integral multiple of 2 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to 2, if being the integral multiple of 2 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to 2, perform step 213, otherwise, execution step 214.

Step 213: read or write 2 data cells according to the memory address of external device access, and reduce according to second value 2 number of data cell and the memory address of increase external device access that external unit need to be accessed, second value 2 is updated to the first numerical value 16, returns to step 203;

Particularly, start to read or write 2 data cells from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 2, and according to second value 2 and bus bit wide, increase the memory address of external device access according to following formula (3), second value 2 is updated to the first numerical value 16, returns to step 203

Addr2=Addr1+buswidth/8*2 （3）

Wherein, in formula (3), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

Wherein, the concrete operations that reduce the number of the data cell that external unit need to access according to second value 2 are: the number of the data cell that external unit need to be accessed deducts second value 2.

Wherein, when the order correspondence of external device access internal memory be operating as read operation time, in internal memory, start to read 2 data cells from the memory address of external device access, when the order correspondence of external device access internal memory be operating as write operation time, in internal memory, start to write 2 data cells from the memory address of external device access.

Wherein, in internal memory, start to read 2 data cells from the memory address of external device access and be specially: internal memory, by 2 data cells that start from the memory address of external device access by the bus transfer in terminal to external unit.

Wherein, in internal memory, starting to write 2 data units from the memory address of external device access is specially: internal memory, 2 data cells of carrying in the order of external device access internal memory are started to be transferred to internal memory by the bus in terminal from the memory address of external device access.

Wherein, after reading or write 2 data cells according to the memory address of external device access, the number of the data cell that the external unit in the first register need to be accessed is updated to the number of the data cell after minimizing, and the memory address of the external device access in the second register is updated to the memory address after increase.

Step 214: divided by 2, obtaining third value is 1, and second value is updated to third value 1 by second value 2;

Wherein, second value is updated to after third value 1, second value just becomes 1.

Step 215: whether the number that judges the data cell that external unit need to access is more than or equal to second value 1, if so, performs step 216, otherwise, end operation;

Particularly, the number of the data cell that external unit need to be accessed and second value 1 compare, if the number of the data cell that external unit need to be accessed is more than or equal to 1, perform step 216, otherwise, end operation.

Step 216: read or write 1 data cell according to the memory address of external device access, and reduce according to second value 1 number of data cell and the memory address of increase external device access that external unit need to be accessed, second value 1 is updated to the first numerical value 16, returns to step 203.

Particularly, start to read or write 1 data cell from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 1, and according to second value 1 and bus bit wide, increase the memory address of external device access according to following formula (4), second value 1 is updated to the first numerical value 16, returns to step 203

Addr2=Addr1+buswidth/8*1 （4）

Wherein, in formula (4), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

Wherein, the concrete operations that reduce the number of the data cell that external unit need to access according to second value 1 are: the number of the data cell that external unit need to be accessed deducts second value 1.

Wherein, when the order correspondence of external device access internal memory be operating as read operation time, in internal memory, start to read 1 data cell from the memory address of external device access, when the order correspondence of external device access internal memory be operating as write operation time, in internal memory, start to write 1 data cell from the memory address of external device access.

Wherein, in internal memory, start to read 1 data cell from the memory address of external device access and be specially: internal memory, by 1 data cell starting from the memory address of external device access by the bus transfer in terminal to external unit.

Wherein, in internal memory, starting to write 1 data unit from the memory address of external device access is specially: internal memory, 1 data cell of carrying in the order of external device access internal memory is started to be transferred to internal memory by the bus in terminal from the memory address of external device access.

Wherein, after reading or write 1 data cell according to the memory address of external device access, the number of the data cell that the external unit in the first register need to be accessed is updated to the number of the data cell after minimizing, and the memory address of the external device access in the second register is updated to the memory address after increase.

The embodiment of the present invention provides a kind of method of access memory, and referring to Fig. 3, method flow comprises:

Step 301: receive the order of the access memory of external unit transmission, carry the number of data cell and the memory address of access that this external unit need to be accessed in the order of this access memory;

Step 302: according to the bandwidth of terminal internal bus free time, determine the first numerical value and second value, the first numerical value equals second value, if the first numerical value and second value are 8;

Particularly, according to the bandwidth of terminal internal bus free time, determine the bandwidth range that the bandwidth of terminal internal bus free time belongs to, the bandwidth range belonging to according to the bandwidth of definite bus free time is from the corresponding relation of the bandwidth range stored and the first numerical value, obtain the first numerical value corresponding to bandwidth of this bus free time, and definite second value, the first numerical value and second value equate, the first numerical value and second value are all more than or equal to 1 and be all 2 index power, if the first numerical value and second value are 8.

Wherein, preserve in advance the corresponding relation of the first numerical value and control signal, in the time that the first numerical value of determining is 8, send the control signal of the first numerical value 8 correspondences to CPU, make CPU carry out the block8 operation of the first numerical value 8 correspondences, block8 is operating as and from internal memory, reads or write 8 data cells.

Step 303: whether the memory address that judges external device access is the integral multiple of 8 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to second value 8, if being the integral multiple of 8 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to second value 8, perform step 304, otherwise, execution step 305;

Particularly, the memory address of external device access and 8 bus bit wide sums are compared, whether the memory address that judges external device access is the integral multiple of 8 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to 8, if being the integral multiple of 8 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to 8, perform step 304, otherwise, execution step 305.

Step 304: read or write 8 data cells according to the memory address of external device access, and reduce according to second value 8 number of data cell and the memory address of increase external device access that external unit need to be accessed, definite second value 8 is updated to the first numerical value 8, returns to step 303;

Particularly, start to read or write 8 data cells from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 8, and according to second value 8 and bus bit wide, increase the memory address of external device access according to following formula (5), second value 8 is updated to the first numerical value 8, returns to step 303

Addr2=Addr1+buswidth/8*8 （5）

Wherein, in formula (5), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

Step 305: divided by 2, obtaining third value is 4, and second value is updated to third value 4 by second value 8;

Step 306: whether the memory address that judges external device access is the integral multiple of 4 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to second value 4, if being the integral multiple of 4 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to second value 4, perform step 307, otherwise, execution step 308;

Particularly, the memory address of external device access and 4 bus bit wide sums are compared, whether the memory address that judges external device access is the integral multiple of 4 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to 4, if being the integral multiple of 4 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to 4, perform step 307, otherwise, execution step 308.

Step 307: read or write 4 data cells according to the memory address of external device access, and reduce according to second value 4 number of data cell and the memory address of increase external device access that external unit need to be accessed, second value 4 is updated to the first numerical value 8, returns to step 303;

Particularly, start to read or write 4 data cells from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 4, and according to second value 4 and bus bit wide, increase the memory address of external device access according to following formula (6), second value 4 is updated to the first numerical value 8, returns to step 303

Addr2=Addr1+buswidth/8*4 （6）

Wherein, in formula (6), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

Step 308: divided by 2, obtaining third value is 2, and second value is updated to third value 2 by second value 4;

Step 309: whether the memory address that judges external device access is the integral multiple of 2 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to second value 2, if being the integral multiple of 2 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to second value 2, perform step 310, otherwise, execution step 311;

Particularly, the memory address of external device access and 2 bus bit wide sums are compared, whether the memory address that judges external device access is the integral multiple of 2 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to 2, if being the integral multiple of 2 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to 2, perform step 310, otherwise, execution step 311.

Step 310: read or write 2 data cells according to the memory address of external device access, and reduce according to second value 2 number of data cell and the memory address of increase external device access that external unit need to be accessed, second value 2 is updated to the first numerical value 8, returns to step 303;

Particularly, start to read or write 2 data cells from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 2, and according to second value 2 and bus bit wide, increase the memory address of external device access according to following formula (7), second value 2 is updated to the first numerical value 8, returns to step 303

Addr2=Addr1+buswidth/8*2 （7）

Wherein, in formula (7), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

Step 311: divided by 2, obtaining third value is 1, and second value is updated to third value 1 by second value 2;

Step 312: whether the number that judges the data cell that external unit need to access is more than or equal to second value 1, if so, performs step 313, otherwise, end operation;

Particularly, the number of the data cell that external unit need to be accessed and second value 1 compare, if the number of the data cell that external unit need to be accessed is more than or equal to 1, perform step 313, otherwise, end operation.

Step 313: read or write 1 data cell according to the memory address of external device access, and reduce according to second value 1 number of data cell and the memory address of increase external device access that external unit need to be accessed, second value 1 is updated to the first numerical value 8, returns to step 303.

Particularly, start to read or write 1 data cell from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 1, and according to second value 1 and bus bit wide, increase the memory address of external device access according to following formula (8), second value 1 is updated to the first numerical value 8, returns to step 303

Addr2=Addr1+buswidth/8*1 （8）

Wherein, in formula (8), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

The embodiment of the present invention provides a kind of method of access memory, and referring to Fig. 4, method flow comprises:

Step 401: receive the order of the access memory of external unit transmission, carry the number of data cell and the memory address of access that this external unit need to be accessed in the order of this access memory;

Step 402: according to the bandwidth of terminal internal bus free time, determine the first numerical value and second value, the first numerical value equals second value, if the first numerical value and second value are 4;

Particularly, according to the bandwidth of terminal internal bus free time, determine the bandwidth range that the bandwidth of terminal internal bus free time belongs to, the bandwidth range belonging to according to the bandwidth of definite bus free time is from the corresponding relation of the bandwidth range stored and the first numerical value, obtain the first numerical value corresponding to bandwidth of this bus free time, and definite second value, the first numerical value and second value equate, the first numerical value and second value are all more than or equal to 1 and be all 2 index power, if the first numerical value and second value are 4.

Wherein, preserve in advance the corresponding relation of the first numerical value and control signal, in the time that the first numerical value of determining is 4, send the control signal of the first numerical value 4 correspondences to CPU, make CPU carry out the block4 operation of the first numerical value 4 correspondences, block4 is operating as and from internal memory, reads or write 4 data cells.

Step 403: whether the memory address that judges external device access is the integral multiple of 4 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to second value 4, if being the integral multiple of 4 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to second value 4, perform step 404, otherwise, execution step 405;

Particularly, the memory address of external device access and 4 bus bit wide sums are compared, whether the memory address that judges external device access is the integral multiple of 4 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to 4, if being the integral multiple of 4 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to 4, perform step 404, otherwise, execution step 405.

Step 404: read or write 4 data cells according to the memory address of external device access, and reduce according to second value 4 number of data cell and the memory address of increase external device access that external unit need to be accessed, definite second value 4 is updated to the first numerical value 4, returns to step 403;

Particularly, start to read or write 4 data cells from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 4, and according to second value 4 and bus bit wide, increase the memory address of external device access according to following formula (9), second value 4 is updated to the first numerical value 4, returns to step 403

Addr2=Addr1+buswidth/8*4 （9）

Wherein, in formula (9), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

Step 405: divided by 2, obtaining third value is 2, and second value is updated to third value 2 by second value 4;

Step 406: whether the memory address that judges external device access is the integral multiple of 2 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to second value 2, if being the integral multiple of 2 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to second value 2, perform step 407, otherwise, execution step 408;

Particularly, the memory address of external device access and 2 bus bit wide sums are compared, whether the memory address that judges external device access is the integral multiple of 2 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to 2, if being the integral multiple of 2 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to 2, perform step 407, otherwise, execution step 408.

Step 407: read or write 2 data cells according to the memory address of external device access, and reduce according to second value 2 number of data cell and the memory address of increase external device access that external unit need to be accessed, second value 2 is updated to the first numerical value 4, returns to step 403;

Particularly, start to read or write 2 data cells from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 2, and according to second value 2 and bus bit wide, increase the memory address of external device access according to following formula (10), second value 2 is updated to the first numerical value 4, returns to step 403

Addr2=Addr1+buswidth/8*2 （10）

Wherein, in formula (10), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

Step 408: divided by 2, obtaining third value is 1, and second value is updated to third value 1 by second value 2;

Step 409: whether the number that judges the data cell that external unit need to access is more than or equal to second value 1, if so, performs step 410, otherwise, end operation;

Particularly, the number of the data cell that external unit need to be accessed and second value 1 compare, if the number of the data cell that external unit need to be accessed is more than or equal to 1, perform step 410, otherwise, end operation.

Step 410: read or write 1 data cell according to the memory address of external device access, and reduce according to second value 1 number of data cell and the memory address of increase external device access that external unit need to be accessed, second value 1 is updated to the first numerical value 4, returns to step 403.

Particularly, start to read or write 1 data cell from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 1, and according to second value 1 and bus bit wide, increase the memory address of external device access according to following formula (11), second value 1 is updated to the first numerical value 4, returns to step 403

Addr2=Addr1+buswidth/8*1 （11）

Wherein, in formula (11), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

The embodiment of the present invention provides a kind of method of access memory, and referring to Fig. 5, method flow comprises:

Step 501: receive the order of the access memory of external unit transmission, carry the number of data cell and the memory address of access that this external unit need to be accessed in the order of this access memory;

Step 502: according to the bandwidth of terminal internal bus free time, determine the first numerical value and second value, the first numerical value equals second value, if the first numerical value and second value are 2;

Particularly, according to the bandwidth of terminal internal bus free time, determine the bandwidth range that the bandwidth of terminal internal bus free time belongs to, the bandwidth range belonging to according to the bandwidth of definite bus free time is from the corresponding relation of the bandwidth range stored and the first numerical value, obtain the first numerical value corresponding to bandwidth of this bus free time, and definite second value, the first numerical value and second value equate, the first numerical value and second value are all more than or equal to 1 and be all 2 index power, if the first numerical value and second value are 2.

Wherein, preserve in advance the corresponding relation of the first numerical value and control signal, in the time that the first numerical value of determining is 2, send the control signal of the first numerical value 2 correspondences to CPU, make CPU carry out the block2 operation of the first numerical value 2 correspondences, block2 is operating as and from internal memory, reads or write 2 data cells.

Step 503: whether the memory address that judges external device access is the integral multiple of 2 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to second value 2, if being the integral multiple of 2 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to second value 2, perform step 504, otherwise, execution step 505;

Particularly, the memory address of external device access and 2 bus bit wide sums are compared, whether the memory address that judges external device access is the integral multiple of 2 bus bit wide sums, and whether the number that judges the data cell that external unit need to access is more than or equal to 2, if being the integral multiple of 2 bus bit wide sums and the number of the data cell that external unit need to be accessed, the memory address of external device access is more than or equal to 2, perform step 504, otherwise, execution step 505.

Step 504: read or write 2 data cells according to the memory address of external device access, and reduce according to second value 2 number of data cell and the memory address of increase external device access that external unit need to be accessed, definite second value 2 is updated to the first numerical value 2, returns to step 503;

Particularly, start to read or write 2 data cells from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 2, and according to second value 2 and bus bit wide, increase the memory address of external device access according to following formula (12), second value 2 is updated to the first numerical value 2, returns to step 503

Addr2=Addr1+buswidth/8*2 （12）

Wherein, in formula (12), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

Step 505: divided by 2, obtaining third value is 1, and second value is updated to third value 1 by second value 2;

Step 506: whether the number that judges the data cell that external unit need to access is more than or equal to second value 1, if so, performs step 507, otherwise, end operation;

Particularly, the number of the data cell that external unit need to be accessed and second value 1 compare, if the number of the data cell that external unit need to be accessed is more than or equal to 1, perform step 507, otherwise, end operation.

Step 507: read or write 1 data cell according to the memory address of external device access, and reduce according to second value 1 number of data cell and the memory address of increase external device access that external unit need to be accessed, second value 1 is updated to the first numerical value 2, returns to step 503.

Particularly, start to read or write 1 data cell from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 1, and according to second value 1 and bus bit wide, increase the memory address of external device access according to following formula (13), second value 1 is updated to the first numerical value 2, returns to step 503

Addr2=Addr1+buswidth/8*1 （13）

Wherein, in formula (13), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

The embodiment of the present invention provides a kind of method of access memory, and referring to Fig. 6, method flow comprises:

Step 601: receive the order of the access memory of external unit transmission, carry the number of data cell and the memory address of access that this external unit need to be accessed in the order of this access memory;

Step 602: according to the bandwidth of terminal internal bus free time, determine the first numerical value and second value, the first numerical value equals second value, if the first numerical value and second value are 1;

Particularly, according to the bandwidth of terminal internal bus free time, determine the bandwidth range that the bandwidth of terminal internal bus free time belongs to, the bandwidth range belonging to according to the bandwidth of definite bus free time is from the corresponding relation of the bandwidth range stored and the first numerical value, obtain the first numerical value corresponding to bandwidth of this bus free time, and definite second value, the first numerical value and second value are all more than or equal to 1 and be all 2 index power, if the first numerical value and second value are 1.

Wherein, preserve in advance the corresponding relation of the first numerical value and control signal, in the time that the first numerical value of determining is 1, send the control signal of the first numerical value 1 correspondence to CPU, make CPU carry out the single operation of the first numerical value 1 correspondence, single is operating as and from internal memory, reads or write 1 data cell.

Step 603: whether the number that judges the data cell that external unit need to access is more than or equal to second value 1, if so, performs step 604, otherwise, end operation;

Particularly, the number of the data cell that external unit need to be accessed and numerical value 1 compare, whether the number that judges the data cell that external unit need to access is more than or equal to 1, if the number of the data cell that external unit need to be accessed is more than or equal to 1, perform step 604, otherwise, end operation.

Step 604: read or write 1 data cell according to the memory address of external device access, and reduce according to second value 1 number of data cell and the memory address of increase external device access that external unit need to be accessed, definite second value 1 is updated to the first numerical value 1, returns to step 603;

Particularly, start to read or write 1 data cell from the memory address of external device access, reduce the number of the data cell that external unit need to access according to second value 1, and according to second value 1 and bus bit wide, increase the memory address of external device access according to following formula (14), second value 1 is updated to the first numerical value 1, returns to step 603

Addr2=Addr1+buswidth/8*1 （14）

Wherein, in formula (14), Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide.

The embodiment of the present invention provides a kind of equipment of access memory, and referring to Fig. 7, this equipment comprises:

Receiver module 701, the order of access memory sending for receiving external unit, carries the number of data cell and the memory address of access that this external unit need to be accessed in this order;

Determination module 702, for according to the bandwidth of terminal internal bus free time, determines the first numerical value and second value, and described the first numerical value equals described second value, and described the first numerical value and described second value are all more than or equal to 1 and be all 2 index power;

Read or writing module 703, if be that a described second value integral multiple of bus bit wide sum and the number of described data cell are more than or equal to described second value for described memory address, read or write a described second value data cell according to described memory address, reduce the number of described data cell and increase described memory address according to described second value, described second value is updated to described the first numerical value, returns to this module 703;

Reduce module 704, if be not that a described second value integral multiple of bus bit wide sum or the number of described data cell are less than described second value and are more than or equal to 1 for described memory address, described second value is obtained to third value divided by 2, described second value is updated to described third value, returns and read or writing module.

Wherein, determination module 702 comprises:

The first determining unit, for according to the bandwidth of terminal internal bus free time, determines the bandwidth range that the bandwidth of this bus free time belongs to;

Wherein, read or writing module 703 comprises:

Increase unit, for according to the memory address of second value, this external device access and bus bit wide, increase the memory address of this external device access according to following formula,

Addr2=Addr1+buswidth/8*n

Wherein, in formula, Addr2 is the memory address of the external device access after increasing, and Addr1 is the memory address of the external device access before increasing, and buswidth is bus bit wide, and n is second value.

Further, described equipment also comprises:

The first memory module, is stored in the first register for the number of data cell that external unit need to be accessed;

The second memory module, for being stored in the second register by the memory address of external device access.

Further, described equipment also comprises:

The first update module, is updated to the number of the data cell after minimizing for the number of data cell that the first register is stored;

The second update module, is updated to the memory address after increase for the described memory address that the second register is stored.

The embodiment of the present invention provides a kind of equipment of access memory, and referring to Fig. 8, this equipment comprises:

Storer 801 and processor 802, for carrying out the method for following access memory:

Wherein, described according to the bandwidth of terminal internal bus free time, determine the first numerical value and second value, described the first numerical value equals described second value, comprising:

Wherein, describedly reduce the number of described data cell and increase described memory address according to described second value, comprising:

Addr2=Addr1+buswidth/8*n

Further, after the order of the access memory that described reception external unit sends, also comprise:

Further, described reduce the number of described data cell and increase described memory address according to described second value after, also comprise:

One of ordinary skill in the art will appreciate that all or part of step that realizes above-described embodiment can complete by hardware, also can carry out the hardware that instruction is relevant by program completes, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium of mentioning can be ROM (read-only memory), disk or CD etc.

The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims

1. a method for access memory, is characterized in that, described method comprises:

2. method according to claim 1, is characterized in that, described according to the bandwidth of terminal internal bus free time, determines the first numerical value and second value, and described the first numerical value equals described second value, comprising:

3. method according to claim 1, is characterized in that, describedly reduces the number of described data cell and increases described memory address according to described second value, comprising:

Addr2=Addr1+buswidth/8*n

4. according to the method described in the arbitrary claim of claims 1 to 3, it is characterized in that, after the order of the access memory that described reception external unit sends, also comprise:

5. method according to claim 4, is characterized in that, described reduce the number of described data cell and increase described memory address according to described second value after, also comprise:

6. an equipment for access memory, is characterized in that, described equipment comprises:

7. equipment according to claim 6, is characterized in that, described determination module comprises:

8. equipment according to claim 6, is characterized in that, described in read or writing module comprises:

Addr2=Addr1+buswidth/8*n

9. according to the equipment described in the arbitrary claim of claim 6 to 8, it is characterized in that, described equipment also comprises:

10. equipment according to claim 9, is characterized in that, described equipment also comprises:

The first update module, is updated to the number of the data cell after minimizing for the number of described data cell that described the first register is stored;

The second update module, is updated to the memory address after increase for the described memory address that described the second register is stored.

The equipment of 11. 1 kinds of access memory, is characterized in that, described equipment comprises storer and processor, for carrying out the method for a kind of access memory as described in claim as arbitrary in claim 1 to 5.