CN103852946B - A kind of array base palte and preparation method thereof, display device - Google Patents
A kind of array base palte and preparation method thereof, display device Download PDFInfo
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- CN103852946B CN103852946B CN201410062665.5A CN201410062665A CN103852946B CN 103852946 B CN103852946 B CN 103852946B CN 201410062665 A CN201410062665 A CN 201410062665A CN 103852946 B CN103852946 B CN 103852946B
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 112
- 239000002184 metal Substances 0.000 claims abstract description 112
- 239000010408 film Substances 0.000 claims abstract description 73
- 238000010276 construction Methods 0.000 claims abstract description 56
- 239000012212 insulator Substances 0.000 claims abstract description 55
- 230000000875 corresponding Effects 0.000 claims abstract description 54
- 239000010409 thin film Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000001755 magnetron sputter deposition Methods 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 20
- 239000000969 carrier Substances 0.000 claims description 18
- 238000000059 patterning Methods 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 238000005755 formation reaction Methods 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 238000000265 homogenisation Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 176
- 239000004973 liquid crystal related substance Substances 0.000 description 30
- 210000002858 crystal cell Anatomy 0.000 description 16
- 230000005684 electric field Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000012528 membrane Substances 0.000 description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000003628 erosive Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Abstract
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, display device, relates to Display Technique field, it is possible to make the thickness homogenization of the thin layer contacted with chock insulator matter.This array base palte includes viewing area and non-display area；Non-display area includes that grid line that transverse and longitudinal intersects and data wire and the region at thin film transistor (TFT) place, grid line and data wire are formed by spaced target carries out magnetron sputtering then carrying out Patternized technique；Being formed with gasket construction in the region corresponding to target interval region of non-display area, the metal film layer that corresponding target interval region is formed is just equal to the thickness of the metal film layer that region is formed with corresponding target with the thickness sum of gasket construction.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and preparation method thereof, display device.
Background technology
Along with developing rapidly of Display Technique, TFT-LCD(Thin Film Transistor Liquid Crystal
Display, Thin Film Transistor-LCD) as a kind of panel display apparatus, because of it, to have volume little, low in energy consumption, without spoke
Penetrate and the feature such as cost of manufacture is relatively low, be increasingly becoming the display product of main flow.
TFT-LCD is made up of array base palte and color membrane substrates.Fill between mutual array base palte and color membrane substrates to box
Enter liquid crystal, form liquid crystal cell, by controlling the deflection of liquid crystal, thus realize the control to light intensity, then by color film base
The filtration of plate, it is achieved coloured image shows.Typically require and multiple chock insulator matter be set between array base palte and color membrane substrates,
Thick to support the box of liquid crystal cell.
In the manufacturing process of existing array base palte, need metal film layer 10(such as gate metal layer, source and drain metal
Layer etc.) it is deposited on by the way of magnetron sputtering on transparency carrier 100.Concrete, form a plurality of of metal film layer by being used for
Target 12 as it is shown in figure 1, splice with the form of spaced arrangement, then the target spliced is carried out magnetron sputtering with
The metal film layer 10 being formed on transparency carrier 100, so can improve the utilization rate of target.But, due to adjacent two
There is between bar target interval region 120.Therefore, during magnetron sputtering, it is formed at above-mentioned at this interval region 120
The thickness of the metal film layer 10 of bright substrate 100 is less than the target thickness just to the metal film layer 10 that region 121 is formed.Institute
Can be uneven with the metal film layer 10 formed, so it is formed at this metal film layer 10 surface and chock insulator matter joint
The surface smoothness of thin layer can reduce, thus cause the height between the multiple chock insulator matters on array base palte uneven
One, such as, on the corresponding transparency carrier 100 of target interval region 120, the height of metal film layer 10 can be less than normal value so that position
Chock insulator matter thereon cannot be played a supporting role, and in turn results in the generation of the bad phenomenon such as display exception, has a strong impact on product
Quality.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and preparation method thereof, display device, it is possible to make and chock insulator matter
The thickness homogenization of the thin layer contacted.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that
The one side of the embodiment of the present invention, it is provided that a kind of array base palte, including viewing area and non-display area；Described non-
Viewing area includes grid line that transverse and longitudinal intersects and data wire and the region at thin film transistor (TFT) place, described grid line and described data
Line forms metal film layer by spaced target carries out magnetron sputtering and is patterned described metal film layer
And formed；The region corresponding to described target interval region of described non-display area is formed with gasket construction, described correspondence
The described metal film layer that described target interval region is formed is with the thickness sum of described gasket construction with corresponding described target just
Equal to the thickness of the described metal film layer that region is formed.
The another aspect of the embodiment of the present invention, it is provided that a kind of display device, including any one array base as above
Plate.
The another aspect of the embodiment of the present invention, it is provided that the manufacture method of a kind of array base palte, described array base palte includes showing
Show region and non-display area；Described method is included in described non-display area, and spaced target is carried out magnetron sputtering
Form metal film layer and described metal film layer be patterned and form grid line and the method for data wire that transverse and longitudinal is intersected,
And the method forming thin film transistor (TFT)；It is characterized in that, described method also includes:
In described non-display area, the region corresponding to described target interval region forms gasket construction, described
The described metal film layer of corresponding described target interval region formation and the thickness sum of described gasket construction and corresponding described target
Material is just equal to the thickness of the described metal film layer that region is formed.
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, display device, and this array base palte includes display
Region and non-display area；This non-display area includes the position residing for grid line that transverse and longitudinal intersects and data wire and thin film transistor (TFT)
Put.Wherein, grid line and data wire are formed by spaced target carries out magnetron sputtering being then patterned technique.
Gasket construction, the gold that corresponding target interval region is formed it is formed with in the region of the corresponding target interval region of non-display area
Belong to thin layer just equal to the thickness of the metal film layer that region is formed with corresponding target with the thickness sum of gasket construction.So
One, the thickness of the thin layer contacted with chock insulator matter being formed at above-mentioned metal film layer can uniform so that is positioned at battle array
The box thickness of liquid crystal cell is supported by each chock insulator matter on row substrate, thus maintains the balance that box is thick, improves product
Quality.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to
Other accompanying drawing is obtained according to these accompanying drawings.
A kind of magnetically controlled sputter method schematic diagram that Fig. 1 provides for prior art；
The structural representation of a kind of array base palte that Fig. 2 provides for the embodiment of the present invention；
The structural representation of a kind of gasket construction that Fig. 3 provides for the embodiment of the present invention；
The structural representation of the another kind of gasket construction that Fig. 4 provides for the embodiment of the present invention；
The structural representation of the another kind of array base palte that Fig. 5 provides for the embodiment of the present invention；
The manufacture method flow chart of a kind of array base palte that Fig. 6 provides for the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on
Embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained, broadly fall into present invention protection
Scope.
The embodiment of the present invention provides a kind of array base palte, as in figure 2 it is shown, include viewing area 113 and non-display area
123.Wherein, non-display area 123 includes grid line 101 that transverse and longitudinal intersects and data wire 102 and thin film transistor (TFT) TFT103 institute
Region, grid line 101 and data wire 102 are by spaced target 12(as shown in Figure 1) carry out magnetron sputtering formation
Metal film layer is also patterned formation to this metal film layer.
Wherein, the region corresponding to target 12 interval region 120 of non-display area 123 is formed with gasket construction 104,
The metal film layer 10 that corresponding target 12 interval region 120 is formed is with the thickness sum of gasket construction 104 with corresponding target 12 just
Equal to the thickness of the metal film layer 10 that region 121 is formed.
It should be noted that typically above-mentioned target 12 is spelled with the form of spaced arrangement to increase operation rate
Connect, be deposited on transparency carrier 100 to form the metal film layer 10 on array base palte by magnetron sputtering technique.Due to correspondence
The metal that region 121 is just being formed by the thickness of the metal film layer 10 that target 12 interval region 120 is formed less than corresponding target 12
The thickness of thin layer 10.So, the metal film layer 10 of formation there will be rough phenomenon so that is formed at this gold
The surface smoothness of the thin layer with chock insulator matter (not shown) joint belonging to thin layer 10 surface declines.So it is positioned at battle array
Part chock insulator matter on row substrate can not play and support the effect that liquid crystal cell box is thick.It is arranged at non-display area 123 by above-mentioned
Gasket construction 104, the thickness of metal film layer 10 formed corresponding to target 12 interval region 120 can be increased so that
The metal film layer 10 that corresponding target 12 interval region 120 is formed is with the thickness sum of gasket construction 104 with corresponding target 12 just
Equal to the thickness of the metal film layer 10 that region 121 is formed.So that be formed at this metal film layer 10 surface with every
The thin film layer thickness that underbed contacts is homogeneous.
The embodiment of the present invention provides a kind of array base palte, and this array base palte includes viewing area and non-display area；This is non-
Viewing area includes grid line that transverse and longitudinal intersects and data wire and thin film transistor (TFT) location.Wherein, grid line and data wire
Formed by spaced target is carried out magnetron sputtering being then patterned technique.Corresponding target at non-display area
The region of material interval region is formed gasket construction, the metal film layer that corresponding target interval region is formed and gasket construction
Thickness sum is just equal to the thickness of the metal film layer that region is formed with corresponding target.So, it is formed at above-mentioned metal
The thickness of the thin layer contacted with chock insulator matter of thin layer can uniform so that each chock insulator matter being positioned on array base palte
All the box thickness of liquid crystal cell is supported, thus maintains the balance that box is thick, improve the quality of product.
Further, as it is shown on figure 3, above-mentioned metal film layer 10 can include the grid being positioned at transparency carrier 100 surface
Metal level 200.
It should be noted that have a various metals thin layer 10 on array base palte, such as, constitute the gate metal of grid line 101
Source-drain electrode metal level of layer 200, the source class of composition TFT103 and drain electrode etc..For public electrode is arranged on color membrane substrates
TN(Twist Nematic, twisted-nematic) for type display device, can be as first layer metal thin layer on array base palte
Gate metal layer 200 be positioned at the surface of transparency carrier 100.Accordingly, it would be desirable to make liner knot on the surface of gate metal layer 200
Structure 104, to increase the thickness of the gate metal layer 200 formed corresponding to target 12 interval region 120, so that be formed at grid
The thickness homogenization of the thin layer contacted with chock insulator matter on pole metal level 200 surface.Such that it is able to improve the matter of array base palte
Amount.
Wherein, TN type display device, is the liquid crystal display using vertical electric field principle, by being oppositely disposed in color film
Between public electrode and the pixel electrode on array base palte on substrate, formation vertical electric field drives to ask and turns nematic-mode
Liquid crystal.Vertical electric field liquid crystal display has an advantage of large aperture ratio, and the shortcoming with the narrow visual angle of about 90 °.
Further, this gasket construction 104 can also include increasing layer 201, and this quasiconductor increasing layer 201 and TFT has
Active layer material is identical.Wherein, the semiconductor active layer of TFT can use IGZO(indium gallium zinc with layer
Oxide, indium gallium zinc oxide) constitute.So, can be by composition work while making the semiconductor active layer of TFT
Skill completes to increase the making of layer 201.Thus eliminate and the manufacturing process with the gasket construction 104 that increase layer 201 is fabricated separately,
And then processing technology raising production efficiency can be simplified.
It should be noted that in the present invention, patterning processes, can refer to include photoetching process, or, including photoetching process and
Etch step, can also include simultaneously printing, ink-jet etc. other for the technique forming predetermined pattern；Photoetching process, refers to bag
Include film forming, expose, the technique utilizing photoresist, mask plate, exposure machine etc. to form figures of the technical process such as development.Can be according to this
The corresponding patterning processes of structure choice formed in invention.
Further, as it is shown on figure 3, gasket construction 104 can also include:
In non-display area 123 by the first insulating barrier 202 sequentially formed from gate insulator 200 surface, carve
The trapezoidal stacked structure that erosion protective layer 203, source-drain electrode metal level 204 and the second insulating barrier 205 are constituted.Wherein this trapezoidal stacking
Structure specifically refers to, as it is shown on figure 3, the heap of multiple thin layers that the area being formed at gate insulator 200 surface is sequentially reduced
Stack structure.Wherein, the area of the thin layer (the first insulating barrier 202) that distance gate insulator 200 is nearest is maximum, and distance grid is exhausted
The area of the thin layer (the second insulating barrier 205) that edge layer 200 is farthest is minimum.So, the lining of the up-small and down-big structure of formation
Mat structure 104, when contacting with chock insulator matter, it is possible to increase chock insulator matter supports stability during liquid crystal cell.
So, gasket construction 104 except above-mentioned increase layer 201 in addition to, other also with forming array substrate is thin
Film layer.Owing to the above-mentioned layer 201 that increases adds the thickness of the gate insulator 200 that corresponding target 12 interval region 120 is formed.Cause
This makes the thin layer contacted with chock insulator matter formed at corresponding target 12 interval region 120 and corresponding target 12 just to region
The thickness of 121 thin layers contacted with chock insulator matter formed is of substantially equal, improves the thin film thickness with chock insulator matter joint
The homogeneity of degree.So that the box thickness of liquid crystal cell is supported by each chock insulator matter being positioned on array base palte, maintain
The balance that box is thick, improves the quality of product.
It should be noted that the array base palte that the embodiment of the present invention provides can be applicable to FSS(Fringe Field
Switching, fringe field switching) type liquid crystal display.
As shown in Figure 4, above-mentioned gasket construction 104 can also include:
The first electrode layer 300 between transparency carrier 100 and gate metal layer 200 in non-display area 123.
For the FFS type display device that the first electrode layer 300 and the second electrode lay 301 are arranged on array base palte, as
The gate metal layer 200 of the first layer metal thin layer on array base palte is positioned at the surface of the first electrode layer 300.Therefore to make
The thickness that must be formed at the thin layer that the surface of gate metal layer 200 contacts with chock insulator matter is homogeneous.Can be at non-display area
In 123, belong to layer 200 between transparency carrier 100 in the grid gold system formed corresponding to target 12 interval region 120, make by
The gasket construction 104 that first electrode layer 300 is constituted.Thus increase the gate metal formed corresponding to target 12 interval region 120
The thickness of layer 200 so that the thin film layer thickness contacted with chock insulator matter being formed at gate metal layer 200 surface is homogeneous.And then
The quality of array base palte can be improved.
Wherein, FFS technology is by parallel electric field and pixel electrode layer produced by pixel electrode edge in same plane
The longitudinal electric field produced with public electrode interlayer forms multi-dimensional electric field, makes in liquid crystal cell between pixel electrode, all directly over electrode
Aligned liquid-crystal molecule can produce rotation conversion, thus improve planar orientation system liquid crystal work efficiency and increase printing opacity effect
Rate.
In order to improve the homogeneity of the thin film layer thickness contacted with chock insulator matter on array base palte further, as it is shown in figure 5,
This gasket construction 104 can also include:
The second electrode lay 301 being positioned at the second insulating barrier 205 surface in non-display area 123.So, permissible
In non-display area 123, in the position of the thin film metal layer that corresponding target 12 interval region 120 is formed, by increasing by first
Electrode layer 300, increase layer 203 and the second electrode lay 301 to constitute gasket construction 104 so that corresponding target 12 interval region
The metal foil that region 121 is just being formed with corresponding target 12 by 120 metal film layers formed with the thickness sum of gasket construction 104
The thickness of film layer is equal, and the thin film layer thickness that such array base palte contacts with chock insulator matter is homogeneous.So that be positioned at array
The box thickness of liquid crystal cell is supported by each chock insulator matter on substrate, maintains the balance that box is thick, improves the quality of product.
Further, the first electrode layer 300 can be public electrode, and the second electrode lay 301 can be pixel electrode；Or,
First electrode layer 300 can be pixel electrode, and the second electrode lay 301 can be public electrode.
It should be noted that in the array base palte of FFS type display device, public electrode and pixel electrode can set by different layer
Putting, the electrode package being wherein positioned at upper strata containing multiple slit-type electrodes, the electrode package being positioned at lower floor containing multiple slit-type electrodes or is
Plate-shaped electrode.
For different layer is arranged at least two pattern, the different layer of at least two pattern arranges and refers to, respectively will at least
Double-layer films forms at least two pattern by patterning processes.Two kinds of different layers of pattern are arranged and refers to, by patterning processes, by
Double-layer films respectively forms a kind of pattern.Such as, public electrode and the different layer of pixel electrode arrange and refer to: by the first transparent electrode thin film
Layer forms lower electrode by patterning processes, the second transparent electrode thin film layer form upper electrode by patterning processes, wherein,
Lower electrode is public electrode (or pixel electrode), and upper electrode is pixel electrode (or public electrode).Wherein, as it is shown in figure 5,
It is positioned at the pixel electrode that upper electrode is slit shape, is positioned at the public electrode that lower electrode is planar shaped.
The embodiment of the present invention provides a kind of display device, including any one array base palte as above, has and this
The identical beneficial effect of array base palte that invention previous embodiment provides, owing to array base palte has been carried out
Describing in detail, here is omitted.
In embodiments of the present invention, display device specifically can include that liquid crystal indicator, such as this display device are permissible
For any product with display function or portions such as liquid crystal display, LCD TV, DPF, mobile phone or panel computers
Part.
The embodiment of the present invention provides a kind of display device, and including array base palte, this array base palte includes viewing area and non-
Viewing area；This non-display area includes grid line that transverse and longitudinal intersects and data wire and thin film transistor (TFT) location.Wherein,
Grid line and data wire are formed by spaced target carries out magnetron sputtering being then patterned technique.Non-display
The region of the corresponding target interval region in region is formed gasket construction, the metal film layer that corresponding target interval region is formed
Just equal to the thickness of the metal film layer that region is formed with corresponding target with the thickness sum of gasket construction.So, shape
The thickness becoming the thin layer contacted with chock insulator matter of above-mentioned metal film layer can uniform so that is positioned on array base palte
Each chock insulator matter the box thickness of liquid crystal cell is supported, thus maintain the balance that box is thick, improve the quality of product.
The embodiment of the present invention provides the manufacture method of a kind of array base palte, wherein, as in figure 2 it is shown, array base palte includes showing
Show region 113 and non-display area 123；This manufacture method is included in non-display area 123, carries out spaced target 12
Magnetron sputtering (as shown in Figure 1) forms metal film layer and is patterned this metal film layer and forms the grid that transverse and longitudinal is intersected
Line 101 and the method for data wire 102, and the method forming thin film transistor (TFT) TFT103.Wherein, above-mentioned manufacture method is all right
Including:
In non-display area 123, the region corresponding to target 12 interval region 120 forms gasket construction 104, right
The metal film layer 10 answering target 12 interval region 120 to be formed is the most right with corresponding target 12 with the thickness sum of gasket construction 104
The thickness of the metal film layer 10 that region 121 is formed is equal.
It should be noted that typically above-mentioned target 12 is spelled with the form of spaced arrangement to increase operation rate
Connect, be deposited on transparency carrier 100 to form the metal film layer 10 on array base palte by magnetron sputtering technique.Due to, right
Answer the gold that region 121 is just being formed by the thickness of the metal film layer 10 that target 12 interval region 120 formed less than corresponding target 12
Belong to the thickness of thin layer 10.So, the metal film layer 10 of formation there will be rough phenomenon so that is formed at this
The surface smoothness of the thin layer with chock insulator matter (not shown) joint on metal film layer 10 surface declines.So it is positioned at
Part chock insulator matter on array base palte can not play and support the effect that liquid crystal cell box is thick.It is arranged at non-display area by above-mentioned
The gasket construction 104 of 123, can increase the thickness of the metal film layer 10 formed corresponding to target 12 interval region 120, so that
The metal film layer 10 obtaining the formation of corresponding target 12 interval region 120 is the most right with corresponding target 12 with the thickness sum of gasket construction
The thickness of the metal film layer 10 that region 121 is formed is equal.So that be formed at this metal film layer 10 surface and dottle pin
The thin film layer thickness that thing contacts is homogeneous.
The embodiment of the present invention provides the manufacture method of a kind of array base palte, and this array base palte includes viewing area and non-display
Region；This manufacture method is included in non-display area, spaced target carries out magnetron sputtering and forms metal film layer also
Metal film layer is patterned and forms grid line and the method for data wire that transverse and longitudinal is intersected, and form thin film transistor (TFT)
Method.The method is additionally included in non-display area, forms gasket construction in the region corresponding to target interval region, corresponding
Metal film layer and the thickness sum of gasket construction that described target interval region is formed with corresponding described target just to region shape
The thickness of the metal film layer become is equal.So, the thickness of the thin layer contacted with chock insulator matter can uniform so that
The box thickness of liquid crystal cell is supported by each chock insulator matter being positioned on array base palte, thus maintains the balance that box is thick, improves
The quality of product.
Further, the method forming metal film layer 10 is included on transparency carrier 100 deposition gate insulator 200.
It should be noted that have a various metals thin layer 10 on array base palte, such as, constitute the gate metal of grid line 101
Source-drain electrode metal level of layer 200, the source class of composition TFT103 and drain electrode etc..For public electrode is arranged on color membrane substrates
TN(Twist Nematic, twisted-nematic) for type display device, can be as first layer metal thin layer on array base palte
Gate metal layer 200 be positioned at the surface of transparency carrier 100.Accordingly, it would be desirable to make liner knot on the surface of gate metal layer 200
Structure 104, to increase the thickness of the gate metal layer 200 formed corresponding to target 12 interval region 120, so that be formed at grid
The thickness homogenization of the thin layer contacted with chock insulator matter on pole metal level 200 surface.Such that it is able to improve the matter of array base palte
Amount.
Further, the method making gasket construction 104 may include that
Use the material identical with the semiconductor active layer of thin film transistor (TFT) TFT to be formed by a patterning processes and increase layer
The pattern of 201.Wherein, the semiconductor active layer of TFT can use IGZO(indium gallium zinc oxide, indium with layer
Gallium zinc oxide) constitute.So, can complete to increase by patterning processes while making the semiconductor active layer of TFT
The making of high-rise 201.Thus eliminate and the manufacturing process with the gasket construction 104 that increase layer 201 is fabricated separately, and then can
Simplify processing technology and improve production efficiency.
Further, the method making gasket construction 104, as shown in Figure 6, it is also possible to including:
S101, be formed the substrate surface of said structure by patterning processes gate metal layer 200 with increase layer 201
Between form the pattern of the first insulating barrier 202.
S102, sequentially form etch-protecting layer 203, source by patterning processes being formed with the substrate surface increasing layer 201
Drain metal layer 204 and the pattern of the second insulating barrier 205.
Wherein, the first insulating barrier 202, etch-protecting layer 203, source-drain electrode metal level the 204, second insulating barrier 205 are constituted
Trapezoidal stacked structure.
Concrete, this trapezoidal stacked structure specifically refers to, as it is shown on figure 3, be formed at the area on gate insulator 200 surface
The stacked structure of the multiple thin layers being sequentially reduced.Wherein, thin layer (the first insulating barrier that distance gate insulator 200 is nearest
202) area is maximum, and the area of the thin layer (the second insulating barrier 205) that distance gate insulator 200 is farthest is minimum.Such one
Coming, the gasket construction 104 of the up-small and down-big structure of formation, when contacting with chock insulator matter, it is possible to increase chock insulator matter supports liquid crystal cell
Time stability.
So, gasket construction 104 except above-mentioned increase layer 201 in addition to, other also with forming array substrate is thin
Film layer.Owing to the above-mentioned layer 201 that increases adds the thickness of the gate insulator 200 that corresponding target 12 interval region 120 is formed.Cause
This makes the thin layer contacted with chock insulator matter formed at corresponding target 12 interval region 120 and corresponding target 12 just to region
The thickness of 121 thin layers contacted with chock insulator matter formed is of substantially equal, improves the thin film thickness with chock insulator matter joint
The homogeneity of degree.So that the box thickness of liquid crystal cell is supported by each chock insulator matter being positioned on array base palte, maintain
The balance that box is thick, improves the quality of product.
Further, the manufacture method of the array base palte provided when the embodiment of the present invention is applied to FSS(Fringe Field
Switching, fringe field switching) type liquid crystal display time, transparency carrier 100 deposits gate insulator 200 step it
Before, the method making gasket construction 104 can also include:
The pattern of the first electrode layer 300 is formed on the surface of transparency carrier 100.
For FFS type display device that the first electrode layer 300 and the second electrode lay 301 are arranged on array base palte and
Speech, is positioned at the surface of the first electrode layer 300 as the gate metal layer 200 of the first layer metal thin layer on array base palte.Cause
This is so that the thickness of thin layer that contacts with chock insulator matter of the surface that is formed at gate metal layer 200 is homogeneous.Can be thoroughly
Before depositing the step of gate insulator 200 on bright substrate 100, form the first electrode layer 300 on the surface of transparency carrier 100
Pattern.This first electrode layer 300 constitutes gasket construction 104.Formed such that it is able to increase corresponding to target 12 interval region 120
The thickness of gate metal layer 200 so that be formed at the thin film layer thickness contacted with chock insulator matter on gate metal layer 200 surface
Homogeneous.And then the quality of array base palte can be improved.
Wherein, FFS technology is by parallel electric field and pixel electrode layer produced by pixel electrode edge in same plane
The longitudinal electric field produced with public electrode interlayer forms multi-dimensional electric field, makes in liquid crystal cell between pixel electrode, all directly over electrode
Aligned liquid-crystal molecule can produce rotation conversion, thus improve planar orientation system liquid crystal work efficiency and increase printing opacity effect
Rate.
In order to improve the flatness of the thin layer contacted with chock insulator matter on array base palte further, make gasket construction
The method of 104 can also include:
It is being formed with the substrate surface pattern by patterning processes formation the second electrode lay 301 of the second insulating barrier 205.This
Sample one, can be in the position of the thin film metal layer that corresponding target 12 interval region 120 is formed, logical in non-display area 123
Cross increase to make the first electrode layer 300, increase layer 203 and the second electrode lay 301 carrys out gasket construction 104 so that corresponding target
Metal film layer and the thickness sum of gasket construction 104 that 12 interval regions 120 are formed with corresponding target 12 just to region 121 shape
The thickness of the metal film layer become is equal, and the thin film layer thickness that such array base palte contacts with chock insulator matter is homogeneous.So that
The box thickness of liquid crystal cell is supported by each chock insulator matter must being positioned on array base palte, maintains the balance that box is thick, improves
The quality of product.
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited thereto, and any
Those familiar with the art, in the technical scope that the invention discloses, can readily occur in change or replace, should contain
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with described scope of the claims.
Claims (14)
1. an array base palte, including viewing area and non-display area；Described non-display area includes the grid line that transverse and longitudinal is intersected
With data wire and the region at thin film transistor (TFT) place, described grid line and described data wire by spaced target is carried out
Magnetron sputtering forms metal film layer and is patterned described metal film layer and is formed；It is characterized in that,
The region corresponding to described target interval region of described non-display area is formed with gasket construction, described gasket construction
It is made up of at least one of which thin layer constituting described thin film transistor (TFT)；
The described metal film layer of described correspondence described target interval region formation and the thickness sum of described gasket construction are with right
Answer described target just equal to the thickness of the described metal film layer that region is formed.
Array base palte the most according to claim 1, it is characterised in that described metal film layer includes being positioned at transparency carrier table
The gate metal layer in face.
Array base palte the most according to claim 2, it is characterised in that
Described gasket construction includes increasing layer, described in increase layer identical with the semiconductor active layer material of described thin film transistor (TFT).
Array base palte the most according to claim 3, it is characterised in that described gasket construction also includes:
Being protected by the first insulating barrier sequentially formed from described gate metal layer surface, etching in described non-display area
The trapezoidal stacked structure that layer, source-drain electrode metal level, the second insulating barrier are constituted.
Array base palte the most according to claim 4, it is characterised in that described gasket construction also includes:
The first electrode layer between described transparency carrier and described gate metal layer in described non-display area.
Array base palte the most according to claim 5, it is characterised in that described gasket construction also includes:
The second electrode lay being positioned at described second surface of insulating layer in described non-display area.
7. according to the array base palte described in claim 5 or 6, it is characterised in that
Described first electrode layer is public electrode, and described the second electrode lay is pixel electrode；Or,
Described first electrode layer is pixel electrode, and described the second electrode lay is public electrode.
8. a display device, it is characterised in that include the array base palte as described in any one of claim 1-7.
9. a manufacture method for array base palte, described array base palte includes viewing area and non-display area；Described method bag
Include at described non-display area, spaced target is carried out magnetron sputtering and forms metal film layer and to described metallic film
Layer is patterned and forms grid line and the method for data wire that transverse and longitudinal is intersected, and the method forming thin film transistor (TFT)；It is special
Levying and be, described method also includes:
In described non-display area, the region corresponding to described target interval region forms gasket construction, described liner
Structure is made up of at least one of which thin layer constituting described thin film transistor (TFT)；
The described metal film layer of described correspondence described target interval region formation and the thickness sum of described gasket construction are with right
Answer described target just equal to the thickness of the described metal film layer that region is formed.
The manufacture method of array base palte the most according to claim 9, it is characterised in that the method forming metal film layer
Including depositing gate insulator on the transparent substrate.
The manufacture method of 11. array base paltes according to claim 10, it is characterised in that make the side of described gasket construction
Method includes:
Layer is increased with using the material formation identical with the semiconductor active layer of described thin film transistor (TFT) by a patterning processes
Pattern.
The manufacture method of 12. array base paltes according to claim 11, it is characterised in that make the side of described gasket construction
Method also includes:
In described gate metal layer and described shape between layer is increased by patterning processes being formed with the substrate surface of said structure
Become the pattern of the first insulating barrier；
The substrate surface increasing layer described in be formed with sequentially forms etch-protecting layer, source-drain electrode metal level by patterning processes
The pattern of two insulating barriers；
Wherein, described first insulating barrier, etch-protecting layer, source-drain electrode metal level and the second insulating barrier constitute trapezoidal stacking knot
Structure.
The manufacture method of 13. array base paltes according to claim 12, it is characterised in that described on described transparency carrier
Before the step of deposition gate insulator, the method making described gasket construction also includes:
The pattern of the first electrode layer is formed on the surface of described transparency carrier.
The manufacture method of 14. array base paltes according to claim 13, it is characterised in that make the side of described gasket construction
Method also includes:
It is being formed with the substrate surface pattern by patterning processes formation the second electrode lay of described second insulating barrier.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410062665.5A CN103852946B (en) | 2014-02-24 | A kind of array base palte and preparation method thereof, display device | |
| US14/312,092 US9349753B2 (en) | 2014-02-24 | 2014-06-23 | Array substrate, method for producing the same and display apparatus |
| US15/133,531 US9793304B2 (en) | 2014-02-24 | 2016-04-20 | Array substrate, method for producing the same and display apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410062665.5A CN103852946B (en) | 2014-02-24 | A kind of array base palte and preparation method thereof, display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103852946A CN103852946A (en) | 2014-06-11 |
| CN103852946B true CN103852946B (en) | 2016-11-30 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102084023A (en) * | 2008-06-19 | 2011-06-01 | 东京毅力科创株式会社 | Magnetron sputtering method, and magnetron sputtering device |
| CN102566148A (en) * | 2010-11-04 | 2012-07-11 | 乐金显示有限公司 | Liquid crystal display panel and method for fabricating the same |
| CN202954086U (en) * | 2012-12-03 | 2013-05-29 | 京东方科技集团股份有限公司 | Film plating device and target materials |
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102084023A (en) * | 2008-06-19 | 2011-06-01 | 东京毅力科创株式会社 | Magnetron sputtering method, and magnetron sputtering device |
| CN102566148A (en) * | 2010-11-04 | 2012-07-11 | 乐金显示有限公司 | Liquid crystal display panel and method for fabricating the same |
| CN202954086U (en) * | 2012-12-03 | 2013-05-29 | 京东方科技集团股份有限公司 | Film plating device and target materials |
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