CN103839510A - Gate driving circuit - Google Patents
Gate driving circuit Download PDFInfo
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- CN103839510A CN103839510A CN201410115343.2A CN201410115343A CN103839510A CN 103839510 A CN103839510 A CN 103839510A CN 201410115343 A CN201410115343 A CN 201410115343A CN 103839510 A CN103839510 A CN 103839510A
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Abstract
An Nth-stage shift register of a gate driving circuit comprises an upward pull unit, an energy storage unit, a driving unit, a downward pull unit and a control unit. The upward pull unit is used for pulling the Nth-stage gate signal of a gate wire upwards to a high-level voltage according to a driving voltage and a first clock pulse signal. The energy storage unit is used for providing the driving voltage for the upward pull unit. The driving unit is used for executing a charging program on the energy storage unit according to a last-stage gate signal. The downward pull unit is used for downwards pulling the driving voltage and the Nth-stage gate signal to a low-level voltage according to a control signal. The control unit is used for generating the control signal according to a second clock pulse signal and the driving voltage. The pulse wave width of the first clock pulse signal is equal to that of the second clock pulse signal, and the rising wave edge of the first clock pulse signal is superior to that of the second clock pulse signal by 1/4-1/2 pulse wave width.
Description
Technical field
The present invention is relevant to a kind of gate driver circuit, espespecially a kind of cpable of lowering power consumption and joint space-efficient gate driver circuit.
Background technology
Generally speaking, display panel includes a plurality of pixels, gate driver circuit and source electrode drive circuit.Source electrode drive circuit is in the pixel being unlocked in order to data writing signal.Gate driver circuit comprises plural number level offset buffer, is used to provide a plurality of signals to control the open and close of every row pixel.In order to reduce cost, gate driver circuit can directly be formed at the frame region of display panel, and the display panel of the above-mentioned type is plate and carries gate type (gate-in-panel type) display panel.The offset buffer that known plate carries gate type display panel is made up of seven transistors and two electric capacity, is also 7T2C framework.But the 7T2C framework of known offset buffer can increase power consumption because comprising a plurality of electric capacity, and can occupy larger space, therefore the 7T2C framework of known offset buffer cannot be applied on the display panel of demand power saving and narrow frame.
Summary of the invention
The object of the present invention is to provide a kind of cpable of lowering power consumption and joint space-efficient gate driver circuit, to solve the problem of prior art.
Gate driver circuit of the present invention comprises plural number level offset buffer, one N level offset buffer of this plural number level offset buffer comprises a pull-up unit, be electrically connected on a gate line, in order to one N level signal of this gate line is pulled to a high levle voltage according to a driving voltage and one first clock signal; One energy-storage units, is electrically connected on this pull-up unit, is used to provide this driving voltage to this pull-up unit; One driver element, is electrically connected on this pull-up unit and this energy-storage units, is used for, according to a prime signal, this energy-storage units is carried out to charging procedure; One drop-down unit, is electrically connected on this energy-storage units and this gate line, in order to according to drop-down this driving voltage of a control signal and this N level signal to low level voltage; And a control module, be electrically connected on this drop-down unit, in order to produce this control signal according to one second clock signal and this driving voltage; Wherein N is positive integer, this high levle voltage is higher than this low level voltage, the pulse bandwidth of this first clock signal and this second clock signal is identical, and 1/4 to 1/2 pulse bandwidth of the ascending wave edge of leading this second clock signal of ascending wave edge of this first clock signal.
Compared to prior art, the offset buffer of gate driver circuit of the present invention is 7T1C framework, offset buffer of the present invention only comprises Single Capacitance, and to reduce power consumption and to save space, therefore gate driver circuit of the present invention can be applicable on the display panel of demand power saving and narrow frame.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of gate driver circuit of the present invention;
Fig. 2 is the schematic diagram of the first embodiment of the N level offset buffer of Fig. 1 gate driver circuit;
Fig. 3 is the waveform schematic diagram of the first embodiment of the coherent signal of N level offset buffer;
Fig. 4 is the waveform schematic diagram of the second embodiment of the coherent signal of N level offset buffer;
Fig. 5 is the schematic diagram of the second embodiment of the N level offset buffer of Fig. 1 gate driver circuit;
Fig. 6 is the schematic diagram of the 3rd embodiment of the N level offset buffer of Fig. 1 gate driver circuit.
[primary clustering symbol description]
100 gate driver circuits
110 (N-2), 110N, 110 (N+2) offset buffer
112 pull-up units
114 energy-storage units
116,116 ' driver element
118 drop-down unit
120 control modules
122,122 ', 122 " auxiliary drop-down unit
C electric capacity
CK1 the first clock signal
CK2 the second clock signal
CK3 the 3rd clock signal
G (n-2), G (n), G (n+2) signal
GL (n-2), GL (n), GL (n+2) gate line
P (n) control signal
Q (n) driving voltage
T1 driving transistors
T2 first controls transistor
T3 the first pull-down transistor
T4 pulls up transistor
T5 the second pull-down transistor
T6 second controls transistor
T7 assists pull-down transistor
VGH high levle voltage
VGL low level voltage.
Embodiment
Please also refer to Fig. 1 and Fig. 2.Fig. 1 is the schematic diagram of gate driver circuit of the present invention, and Fig. 2 is the schematic diagram of the first embodiment of the N level offset buffer of Fig. 1 gate driver circuit.As shown in the figure, gate driver circuit 100 comprises plural number level offset buffer 110, for convenience of description, gate driver circuit only shows (N-2) level offset buffer 110 (N-2), N level offset buffer 110N and (N+2) level offset buffer 110 (N+2), wherein only have N level offset buffer 110N in Fig. 2, to show inside structure, all the other grade of offset buffer is to be analogous to N level offset buffer 110N, so separately do not repeat.(N-2) level offset buffer 110 (N-2) is in order to export signal G (n-2), N level offset buffer 110N is in order to export signal G (n), and (N+2) level offset buffer 110 (N+2) is in order to export signal G (n+2).Signal G (n-2), G (n), G (n+2) are sequentially sent to pel array to open corresponding pixel cell via gate lines G L (n-2), GL (n), GL (N+2).In addition, signal G (n-2) can be sent to N level offset buffer 110N, with activation N level offset buffer 110N, and signal G (n) can be sent to (N+2) level offset buffer 110 (N+2), with activation (N+2) level offset buffer 110 (N+2).Wherein N is positive integer.
N level offset buffer 110N comprises a pull-up unit 112, an energy-storage units 114, a driver element 116, a drop-down unit 118 and a control module 120.Pull-up unit 112 is to be electrically connected on gate lines G L (n), in order to the N level signal of gate lines G L (n) is pulled to a high levle voltage according to a driving voltage Q (n) and one first clock signal CK1.Energy-storage units 114 is to be electrically connected on pull-up unit 112, is used to provide driving voltage Q (n) to pull-up unit 112.Driver element 116 is to be electrically connected on pull-up unit 112 and energy-storage units 114, is used for, according to (N-2) level signal G (n-2) (or other prime signals), energy-storage units 114 is carried out to charging procedure.Drop-down unit 118 is to be electrically connected on energy-storage units 114 and gate lines G L (n), in order to according to a drop-down driving voltage Q of control signal P (n) (n) and N level signal to low level voltage VGL.Control module 120 is to be electrically connected on drop-down unit 118, in order to produce control signal P (n) according to one second clock signal CK2 and driving voltage Q (n).
N level offset buffer 110N separately comprises an auxiliary drop-down unit 122, be electrically connected on energy-storage units 114, in order to according to (N+2) level signal G (n+2) (or other rear class signals) drop-down driving voltage Q (n).
In embodiments of the present invention, pull-up unit 112 comprises the T4 that pulls up transistor, the first end of T4 of pulling up transistor is to receive the first clock signal CK1, the control end of T4 of pulling up transistor is electrically connected on energy-storage units 114, in order to receive driving voltage Q (n), the second end of the T4 that pulls up transistor is electrically connected on gate lines G L (n).Driver element 116 comprises a driving transistors T1, and the first end of driving transistors T1 and control end are to receive (N-2) level signal G (n-2), and the second end of driving transistors T1 is to be electrically connected on energy-storage units 114.
Drop-down unit 118 comprises one first pull-down transistor T3 and one second pull-down transistor T5.The first end of the first pull-down transistor T3 is to be electrically connected on energy-storage units 114, the control end of the first pull-down transistor T3 is to be electrically connected on control module 120 with reception control signal P (n), and the second end of the first pull-down transistor T3 is to be electrically connected on low level voltage.The first end of the second pull-down transistor T5 is to be electrically connected on gate lines G L (n), the control end of the second pull-down transistor T5 is to be electrically connected on control module 120 with reception control signal P (n), and the second end of the second pull-down transistor T5 is to be electrically connected on low level voltage.
Energy-storage units 114 comprises a capacitor C.The first end of capacitor C is to be electrically connected on driver element 116 and pull-up unit 112, and the second end of capacitor C is to be electrically connected on gate lines G L (n).Auxiliary drop-down unit 122 comprises an auxiliary pull-down transistor T7.The first end of auxiliary pull-down transistor T7 is to receive low level voltage VGL, the control end of auxiliary pull-down transistor T7 is to receive (N+2) level signal G (n+2), and the second end of auxiliary pull-down transistor T7 is to be electrically connected on energy-storage units 114.
Please refer to Fig. 3, and in the lump with reference to figure 1 and Fig. 2.Fig. 3 is the waveform schematic diagram of the first embodiment of the coherent signal of N level offset buffer.As shown in Figure 3, the pulse bandwidth of the first clock signal CK1 and the second clock signal CK2 is identical, and 1/4 pulse bandwidth of ascending wave edge of leading the second clock signal CK2 of the ascending wave edge of the first clock signal CK1.In the time that driver element 116 receives (N-2) the level signal G (n-2) that is pulled to high levle voltage, driver element 116 can charge to energy-storage units 114, so that driving voltage Q (n) rises.And in the time that the first clock signal CK1 rises to high levle voltage VGH, the driving voltage Q (n) of energy-storage units 114 can be drawn high again because of capacitance coupling effect, moreover pull-up unit 112 is also pulled to high levle voltage VGH because the first clock signal CK1 rises to high levle voltage VGH by N level signal G (n).The high levle voltage VGH of the first clock signal CK1 is higher than low level voltage VGL.In the time that the second clock signal CK2 also rises to high levle voltage VGH, the second clock signal CK2 can be to the first control transistor T 2 precharge, but because of the current potential of driving voltage Q (n) higher, also can open so second controls transistor T 6, so that control signal P (n) is maintained to low level voltage VGL.In the time that the first clock signal CK1 drops to low level voltage VGL and the second clock signal CK2 still at high levle voltage VGH, N level signal G (n) is pulled down to low level voltage VGL, and driving voltage Q (n) is also because capacitance coupling effect is by drop-down, and then the second control transistor T 6 is closed, so that the control signal P of control module 120 (n) is pulled to high levle voltage VGH.In the time that control signal P (n) is pulled to high levle voltage VGH, the first pull-down transistor T3 of drop-down unit 118 and the second pull-down transistor T5 can open by controlled signal P (n), with further drop-down driving voltage Q (n) and N level signal G (n) to low level voltage VGL.
In addition, auxiliary drop-down unit 122 can be in the time receiving (N+2) the level signal G (n+2) that is pulled to high levle voltage drop-down driving voltage Q (n) again, to maintain the stability of N level offset buffer.
According to above-mentioned configuration, the driving voltage of offset buffer and control signal can be stablized generation and can not check and balance, and therefore the offset buffer of gate driver circuit of the present invention can stably be exported signal.Moreover the offset buffer of gate driver circuit of the present invention is made up of seven transistors and an electric capacity, is also 7T1C framework.The 7T1C framework of offset buffer of the present invention only comprises Single Capacitance, and therefore offset buffer of the present invention can reduce power consumption, and saves space.
Please refer to Fig. 4, and in the lump with reference to figure 1 and Fig. 2.Fig. 4 is the waveform schematic diagram of the second embodiment of the coherent signal of N level offset buffer.As shown in Figure 4, the pulse bandwidth of the first clock signal CK1 and the second clock signal CK2 is identical, and 1/2 pulse bandwidth of ascending wave edge of leading the second clock signal CK2 of the ascending wave edge of the first clock signal CK1.The function mode of N level offset buffer is also similar in appearance to above-mentioned explanation, so separately do not repeat.The ascending wave edge of the first clock signal CK1 is 1/4 to 1/2 pulse bandwidth of ascending wave edge of leading the second clock signal CK2 in embodiments of the present invention.
Please refer to Fig. 5, Fig. 5 is the schematic diagram of the second embodiment of the N level offset buffer of Fig. 1 gate driver circuit.The N level offset buffer 100N ' of Fig. 5 is except driver element 116 ' and auxiliary drop-down unit 122 ', and make peace the greatly assembly of N level offset buffer 100N of Fig. 2 of other assemblies is identical.Driver element 116 ' comprises a driving transistors T1, the first end of driving transistors T1 is to receive a high levle voltage V1, the control end of driving transistors T1 is to receive (N-2) level signal G (n-2), and the second end of driving transistors T1 is to be electrically connected on energy-storage units 114.Auxiliary drop-down unit 122 ' comprises an auxiliary pull-down transistor T7.The first end of auxiliary pull-down transistor T7 is to receive a low level voltage V2, the control end of auxiliary pull-down transistor T7 is to receive (N+2) level signal G (n+2), and the second end of auxiliary pull-down transistor T7 is to be electrically connected on energy-storage units 114.High levle voltage V1 can be identical or be different from high levle voltage VGH, and low level voltage V2 can be identical or be different from low level voltage VGL.According to above-mentioned configuration, in the time that driver element 116 ' receives (N-2) the level signal G (n-2) that is pulled to high levle voltage, driving transistors T1 can be unlocked, to utilize high levle voltage V1 to charge to energy-storage units 114; And in the time that auxiliary drop-down unit 122 ' receives (N+2) the level signal G (n+2) that is pulled to high levle voltage, auxiliary pull-down transistor T7 can be unlocked, to utilize the drop-down driving voltage Q of low level voltage V2 (n).The running of the N level offset buffer 100N ' of Fig. 5 is similar in appearance to the running of the N level offset buffer 100N of Fig. 2, is therefore not described further.
Please refer to Fig. 6, Fig. 6 is the schematic diagram of the second embodiment of the N level offset buffer of Fig. 1 gate driver circuit.The N level offset buffer 100N of Fig. 6 " except auxiliary drop-down unit 122 ", make peace the greatly assembly of N level offset buffer 100N of Fig. 2 of other assemblies is identical.Auxiliary drop-down unit 122 ' comprises an auxiliary pull-down transistor T7.The first end of auxiliary pull-down transistor T7 is to receive (N-2) level signal G (n-2), the control end of auxiliary pull-down transistor T7 is to receive (N+2) level signal G (n+2) or the 3rd clock signal CK3, and the second end of auxiliary pull-down transistor T7 is to be electrically connected on energy-storage units 114.The phase place of the 3rd clock signal CK3 is the phase place in contrast to the first clock signal CK1.According to above-mentioned configuration, when receiving, auxiliary drop-down unit 122 ' is pulled to (N+2) level signal G (n+2) of high levle voltage or in the time that the 3rd clock signal CK3 rises to high levle voltage, auxiliary pull-down transistor T7 can be unlocked, to utilize (N-2) level signal G (n-2) the drop-down driving voltage Q (n) that is pulled down to low level voltage.The N level offset buffer 100N of Fig. 6 " running be similar in appearance to the running of the N level offset buffer 100N of Fig. 2, be therefore not described further.
Gate driver circuit of the present invention is the frame region that is directly formed at display panel, that is to say that gate driver circuit of the present invention is to be applied to plate to carry gate type (gate-in-panel type) display panel.
In addition, in the above-described embodiments, gate driver circuit is to be applied to bi-directional drive, and therefore N level offset buffer 110N can be that signal G (n-2) drives by (N-2) level offset buffer 110 (N-2).But the present invention is not as limit, in other embodiments of the invention, N level offset buffer 110N can also be driven by the signal of other prime offset buffers.
Compared to prior art, the offset buffer of gate driver circuit of the present invention is 7T1C framework, offset buffer of the present invention only comprises Single Capacitance, and to reduce power consumption and to save space, therefore gate driver circuit of the present invention can be applicable on the display panel of demand power saving and narrow frame.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.
Claims (10)
1. a gate driver circuit, comprises plural number level offset buffer, and a N level offset buffer of this plural number level offset buffer comprises:
One pull-up unit, is electrically connected on a gate line, in order to one N level signal of this gate line is pulled to a high levle voltage according to a driving voltage and one first clock signal;
One energy-storage units, is electrically connected on this pull-up unit, is used to provide this driving voltage to this pull-up unit;
One driver element, is electrically connected on this pull-up unit and this energy-storage units, is used for, according to a prime signal, this energy-storage units is carried out to charging procedure;
One drop-down unit, is electrically connected on this energy-storage units and this gate line, in order to according to drop-down this driving voltage of a control signal and this N level signal to low level voltage; And
One control module, is electrically connected on this drop-down unit, in order to produce this control signal according to one second clock signal and this driving voltage;
Wherein N is positive integer, this high levle voltage is higher than this low level voltage, the pulse bandwidth of this first clock signal and this second clock signal is identical, and ascending wave edge 1/4 to 1/2 pulse bandwidth of leading this second clock signal of ascending wave edge of this first clock signal.
2. gate driver circuit as claimed in claim 1, is characterized in that, comprises an auxiliary drop-down unit, is electrically connected on this energy-storage units, in order to according to drop-down this driving voltage of a rear class signal.
3. gate driver circuit as claimed in claim 2, is characterized in that, this rear class signal is one (N+2) level signal.
4. gate driver circuit as claimed in claim 2, is characterized in that, this auxiliary drop-down unit comprises:
One auxiliary pull-down transistor, comprises:
One first end, in order to receive this low level voltage;
One control end, in order to receive this rear class signal; And
One second end, is electrically connected on this energy-storage units.
5. gate driver circuit as claimed in claim 1, is characterized in that, this prime signal is one (N-2) level signal.
6. gate driver circuit as claimed in claim 1, is characterized in that, this pull-up unit comprises:
One pulls up transistor, and comprises:
One first end, in order to receive this first clock signal;
One control end, is electrically connected on this energy-storage units, in order to receive this driving voltage; And
One second end, is electrically connected on this gate line.
7. gate driver circuit as claimed in claim 1, is characterized in that, this driver element comprises:
One driving transistors, comprises:
One first end, in order to receive this prime signal;
One control end, in order to receive this prime signal; And
One second end, is electrically connected on this energy-storage units.
8. gate driver circuit as claimed in claim 1, is characterized in that, this drop-down unit comprises:
One first pull-down transistor, comprises:
One first end, is electrically connected on this energy-storage units;
One control end, is electrically connected on this control module to receive this control signal; And
One second end, is electrically connected on this low level voltage; And
One second pull-down transistor, comprises:
One first end, is electrically connected on this gate line;
One control end, is electrically connected on this control module to receive this control signal; And
One second end, is electrically connected on this low level voltage.
9. gate driver circuit as claimed in claim 1, is characterized in that, this control module comprises:
One first controls transistor, comprises:
One first end, in order to receive this second clock signal;
One control end, in order to receive this second clock signal; And
One second end, is electrically connected on this drop-down unit; And
One second controls transistor, comprises:
One first end, is electrically connected on transistorized the second end of this first control;
One control end, is electrically connected on this energy-storage units to receive this driving voltage; And
One second end, is electrically connected on this low level voltage.
10. true gate driver circuit as claimed in claim 1, is characterized in that, this energy-storage units comprises:
One electric capacity, comprises:
One first end, is electrically connected on this driver element and this pull-up unit; And
One second end, is electrically connected on this gate line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410115343.2A CN103839510A (en) | 2014-03-26 | 2014-03-26 | Gate driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410115343.2A CN103839510A (en) | 2014-03-26 | 2014-03-26 | Gate driving circuit |
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| CN103839510A true CN103839510A (en) | 2014-06-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN201410115343.2A Pending CN103839510A (en) | 2014-03-26 | 2014-03-26 | Gate driving circuit |
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| CN105390086A (en) * | 2015-12-17 | 2016-03-09 | 武汉华星光电技术有限公司 | GOA (gate driver on array) circuit and displayer using same |
| CN106664085A (en) * | 2014-07-03 | 2017-05-10 | 三菱电机株式会社 | Gate driving circuit for insulated gate-type power semiconductor element |
| WO2017113438A1 (en) * | 2015-12-29 | 2017-07-06 | 武汉华星光电技术有限公司 | Gate driver on array circuit and display using gate driver on array circuit |
| CN108615498A (en) * | 2018-05-14 | 2018-10-02 | 昆山龙腾光电有限公司 | Gate driving circuit, display panel and display device |
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Application publication date: 20140604 |