CN103820862A - Method for preparing high-temperature annealing silicon wafer - Google Patents
Method for preparing high-temperature annealing silicon wafer Download PDFInfo
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- CN103820862A CN103820862A CN201210465601.0A CN201210465601A CN103820862A CN 103820862 A CN103820862 A CN 103820862A CN 201210465601 A CN201210465601 A CN 201210465601A CN 103820862 A CN103820862 A CN 103820862A
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- silicon chip
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- silicon wafer
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 78
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 78
- 239000010703 silicon Substances 0.000 title claims abstract description 78
- 238000000137 annealing Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title abstract description 34
- 239000010453 quartz Substances 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000001816 cooling Methods 0.000 claims abstract description 4
- 230000001681 protective effect Effects 0.000 claims abstract description 4
- 238000002360 preparation method Methods 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 2
- 238000004321 preservation Methods 0.000 abstract 3
- 230000002411 adverse Effects 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 13
- 239000013078 crystal Substances 0.000 description 11
- 239000002245 particle Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 238000003892 spreading Methods 0.000 description 4
- 230000007480 spreading Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010923 batch production Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000036581 peripheral resistance Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
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Abstract
The invention provides a method for preparing a high-temperature annealing silicon wafer. The method comprises the following steps: (1) after the silicon wafer is loaded well, lifting into quartz boiler tube with the temperature of 650 DEG C, and the protective atmosphere of pure Ar at the speed of 150mm/min, and performing heat preservation for 30 minutes; (2) introducing H2 into the quartz boiler tube, changing the annealing atmosphere in the mixed atmosphere of Ar and H2, and raising the temperature to 1000 DEG C; (3), stopping H2 introducing, changing the annealing atmosphere to be pure Ar atmosphere, raising the temperature to 1200 DEG C and performing heat preservation for 1 h; (4), after the heat preservation is completed, continuously introducing pure Ar, unloading from a boat after the temperature is dropped to be 650DEG C, cooling the silicon wafer to room temperature and then unloading. Through the adoption of the preparing method, cavity type micro-defects on the surface of the silicon wafer is eliminated and the haze value of the surface is reduced, and the consistency of the specific resistance of the silicon wafer in deep direction and the uniformity of the specific resistance in the radial direction are ensured. No extra adverse effects are caused, excessive procedures are not required to be increased, the production efficiency is improved, the cost is lowered, and the method is suitable for massive production.
Description
Technical field
The present invention relates to a kind of preparation method of high temperature annealing silicon chip, for the preparation of high quality unicircuit silicon substrate material.
Background technology
Silicon chip is to utilize vertical pulling method (CZ method) or zone melting method (FZ method) to obtain silicon single crystal ingot, and silicon single crystal ingot prepares through techniques such as line cutting, grinding, polishing, cleanings.In the process with CZ method growing crystal, because the gathering in room can form a kind of empty type microdefect, it is crystal primary partical defect (COP), this defect can reduce the integrity (GOI) of MOS component grid oxidizing layer, therefore the requirement of preparing in order to meet device, need to reduce the crystal primary partical defect (COP) of silicon chip surface.High-temperature annealing process is exactly a kind of effective means.General technology condition is that silicon chip is placed in to Ar atmosphere, is then warmed up to 1200 ℃ and be incubated 1h.If but in pure argon, heat-treat the decline that can cause the about 3 μ m internal resistance of the nearly surf zone of silicon chip, as shown in Figure 1.This be mainly because silicon chip clean and storage process subsequently in, can form the natural oxide film that about 15-40nm is thick at silicon chip surface, in annealing process, these oxide films can adsorb body of heater or close on the boron atom of silicon chip, these boron atoms can penetrate oxide film and then be diffused into silicon chip surface region under the effect of high temperature, cause the reduction of the rear silicon chip surface resistance of annealing.
The method overcoming the above problems mainly contains following two kinds: the one, through the polishing again of heat treated silicon chip, remove the thickness of the about 5 μ m in surface, and just can obtain the normal silicon chip of resistance; The 2nd, before high-temperature heat treatment with HF solution by Wafer Cleaning one time, remove surperficial natural oxide film, then enter immediately stove.But these two kinds of methods have limitation, and first method can cause surperficial clean area to reduce even to disappear, and the void-type defect of silicon chip surface is reappeared; Second method can cause the increase of silicon chip surface particle, as shown in Figure 2.In addition, these two kinds of methods all can cause the increase of cost.
Therefore, need to find a kind of method cheaply to reduce or eliminate the crystal primary partical defect (COP) of silicon chip surface, keeping the consistence of silicon chip surface to internal resistance rate simultaneously.
Summary of the invention
In order to overcome above-mentioned deficiency of the prior art, the object of the present invention is to provide a kind of preparation method of high temperature annealing silicon chip, in reducing silicon chip surface void-type defect density, keep the consistence of resistivity depth profile by high-temperature heat treatment, thereby improve the quality of substrate, improve the integrity of gate oxide.
For achieving the above object, the present invention is by the following technical solutions:
A preparation method for high temperature annealing silicon chip, comprises the following steps:
(1), after silicon slice loading is good, rise up into temperature as 650 ℃ take the speed of 150mm/min, in the Quartz stove tube that protective atmosphere is pure Ar, insulation 30min;
(2) in Quartz stove tube, pass into H
2, now annealing atmosphere becomes Ar and H
2mixed atmosphere, and be warmed up to 1000 ℃;
(3) stop logical H
2, annealing atmosphere is become to pure Ar atmosphere, and is warmed up to 1200 ℃ of insulation 1h;
(4) after insulation finishes, continue to pass into pure Ar, go out boat after cooling to 650 ℃, unload after silicon chip is cooled to room temperature.
In above-mentioned preparation method, Ar and H in described step (2)
2mixed atmosphere in H
2with the throughput ratio of Ar be 4%; Heat-up rate is 3～5 ℃/min.
In above-mentioned preparation method, in described step (4), the boat speed that goes out of silicon chip is 150mm/min.
The invention has the advantages that:
Compared with adopting the silicon chip of pure Ar atmosphere annealing, adopt preparation method of the present invention not only to eliminate the empty type microdefect of silicon chip surface, reduce surperficial haze value (Haze), and guaranteed consistence and the footpath homogeneity upwards of silicon chip resistivity on depth direction.
Adopt the present invention not only can prepare high-quality silicon substrate material, and can not bring additional undesirable action, do not need to increase unnecessary operation, not only improved production efficiency but also reduced cost, be suitable for batch production.
Accompanying drawing explanation
Fig. 1 is the depth profile of silicon chip resistance after pure Ar atmosphere, 1200 ℃/1h annealing.
Fig. 2 is the variation diagram of silicon chip through HF rinsing rear surface particle.
Fig. 3 is process flow sheet of the present invention.
Fig. 4 is step (2) temperature while being 950 ℃, the depth profile of silicon chip resistivity.
Fig. 5 is step (2) temperature rise rate while being 10 ℃/min, the depth profile of silicon chip resistivity.
Fig. 6 is for adopting the resistivity depth profile measuring by capacitance-voltage (C-V) method after the present invention.
Fig. 7 is for adopting the resistivity depth profile measuring by spreading resistance (SRP) method after the present invention.
Fig. 8 is the particle changing conditions of silicon chip surface before and after employing the present invention anneals.
Fig. 9 is the changing conditions of silicon chip surface haze values (Haze) before and after employing the present invention anneals.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described.
The equipment using in high temperature annealing silicon chip preparation process is the A412 type high-temperature annealing furnace of sophisticated semiconductor Materials Co., Ltd (ASM), load silicon chip with silicon carbide boat (SIC-BAOT) and carborundum ring (SIC-RING), maximum slide glass amount is 90.Silicon chip used is P type <110> monocrystalline, and diameter is 300mm, and resistivity is 8-12 Ω/cm.The measuring method of resistivity is capacitance-voltage method (C-V) and spreading resistance method (SRP).Surface particles and surperficial haze value (Haze) are measured with surface scan instrument (SP1), SP1 point defects (LPD) represents the particle of silicon chip surface, and the point defect that cannot wash off (LPD-N) represents crystal primary partical defect (COP).
As shown in Figure 3, step of the present invention (1) is that cleaned silicon chip is packed in annealing furnace, then in Ar atmosphere, is incubated 30min, and main purpose is to purge to reduce the oxygen level in boiler tube by Ar, prevents at next step logical H
2in time, causes danger; Also make the temperature of whole silicon chip be consistent, prevent from producing slip line in next step temperature-rise period simultaneously.Step (2) is at H
2with in the mixed atmosphere of Ar, be warmed up to 1000 ℃ with 3～5 ℃/min.Object is to remove the natural oxide film of silicon chip surface.The boiler tube of annealing furnace, adjacent silicon chip, silicon carbide boat all may discharge boron atom to silicon chip surface, are then adsorbed by the natural oxidizing layer of silicon chip surface, go in just may being diffused into silicon chip in the time of high temperature, cause resistivity decreased.Therefore,, in order to keep the consistence of resistivity, must first remove the natural oxide film of silicon chip surface.So by H
2be passed in boiler tube, for security consideration H
2with the throughput ratio of Ar be 4% because H
2limits of explosion be 4%～70%.H
2at high temperature can with the natural oxide film (SiO of silicon chip surface
2) occur to react as follows:
H
2+SiO
2→SiO↑+H
2O↑
Along with the carrying out of reaction, the boron atom in oxide film has also been brought in annealing atmosphere and has eliminated, and the resistivity of silicon chip surface has also just kept consistence.H
2and SiO
2the minimum temperature of reaction be 850 ℃, but experiment finds that in temperature oxide film cannot all be removed during lower than 1000 ℃, the resistance value of silicon chip surface can reduce.Fig. 4 is the resistivity changes with depth figure while being warmed up to 950 ℃ with 5 ℃/min.Can find out that technique finishes rear surface resistance and reduces.It should be noted that temperature rise rate has a great impact the elimination of oxide film.If temperature rise rate is too fast, can cause the variation that center and peripheral resistance is very large.Fig. 5 is that heat-up rate is that 10 ℃/min is warmed up to 1000 ℃, and the center and peripheral resistivity after technique completes, with the variation of the degree of depth, can find out that edge resistivity raises than centre very large.Experimental results show that when heat-up rate remains on 3～5 ℃/min, can guarantee that resistance has good homogeneity.Heat-up rate is slower in theory, and the temperature at silicon chip edge and center is more approaching, H
2and SiO
2chemical reaction carry out also more even, silicon chip edge and center resistance consistence are also better.Fig. 6 is speed while being 3 ℃/min, and resistivity is with the distribution plan of the degree of depth.The resistivity that can find out silicon chip center and peripheral has all kept good consistence on depth direction.Fig. 7 is the measuring result of spreading resistance.Due to the limitation of capacitance-voltage method (C-V method) itself, resistance that cannot Measurement accuracy silicon chip surface 1 μ m place, therefore needs to measure with spreading resistance method (SRP method).Can find out from test result, silicon chip surface is basically identical to inner resistance.
Step of the present invention (3) is that protective atmosphere is become to Ar, then temperature is raised to 1200 ℃ and be incubated 1h.The main purpose of this step is the surperficial microroughness of eliminating the crystal primary partical defect (COP) of silicon chip surface and reducing silicon chip.The inwall of crystal primary partical defect (COP) has layer oxide film, under hot environment, oxide film is decomposed into interstitial oxygen concentration and is diffused into outside silicon chip, the only remaining cavity being formed by room, then will be filled in these cavities and these cavities are filled and led up from gap Siliciumatom, crystal primary partical defect (COP) disappears thereupon.At high temperature, what the atom of silicon chip surface can be spontaneous is diffused into from the high place of energy the place that energy is low simultaneously, flow to surperficial " pit " and goes from " projection " on surface, makes surface become smooth, has reduced surperficial microroughness.Step (4) is final step of the present invention, and after insulation finishes, under pure Ar atmosphere, reducing the temperature to 650 ℃, to go out boat cooling, unloading silicon chip.
Fig. 8 is the grain value of utilizing surface scan instrument SP1 to measure before and after polished section annealing, can find out through the crystal primary partical defect (COP) of pyroprocessing rear panel sub-surface and all be eliminated, and the quantity of surface particles has also had obvious minimizing.Fig. 9 is silicon chip surface haze value (Haze) before and after processing with the present invention, the mean value of the annealed rear surface of silicon chip haze value (Haze) has reduced by 52.6%, peak reduction 70.7%, absolutely prove that the present invention has improved the surface quality of silicon chip.
In sum, adopt the present invention not only can prepare high-quality silicon substrate material, and can not bring additional undesirable action, do not need to increase unnecessary operation, not only improved production efficiency but also reduced cost, be suitable for batch production.
Claims (4)
1. a preparation method for high temperature annealing silicon chip, is characterized in that, comprises the following steps:
(1), after silicon slice loading is good, rise up into temperature as 650 ℃ take the speed of 150mm/min, in the Quartz stove tube that protective atmosphere is pure Ar, insulation 30min;
(2) in Quartz stove tube, pass into H
2, now annealing atmosphere becomes Ar and H
2mixed atmosphere, be then warmed up to 1000 ℃;
(3) stop logical H
2, annealing atmosphere is become to pure Ar atmosphere, and is warmed up to 1200 ℃ of insulation 1h;
(4) after insulation finishes, continue to pass into pure Ar, go out boat after cooling to 650 ℃, unload after silicon chip is cooled to room temperature.
2. the preparation method of high temperature annealing silicon chip according to claim 1, is characterized in that, Ar and H in described step (2)
2mixed atmosphere in H
2with the throughput ratio of Ar be 4%.
3. the preparation method of high temperature annealing silicon chip according to claim 1, is characterized in that, in described step (2), heat-up rate is 3～5 ℃/min.
4. the preparation method of high temperature annealing silicon chip according to claim 1, is characterized in that, in described step (4), the boat speed that goes out of silicon chip is 150mm/min.
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| CN201210465601.0A CN103820862A (en) | 2012-11-16 | 2012-11-16 | Method for preparing high-temperature annealing silicon wafer |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104651946A (en) * | 2015-03-19 | 2015-05-27 | 太原理工大学 | Silicon waveguide surface smoothing process based on silicon hydrogen bond current density method |
| CN105470129A (en) * | 2015-12-01 | 2016-04-06 | 北京七星华创电子股份有限公司 | Method for eliminating impact on minority carrier diffusion length from thermal donor |
| CN106257625A (en) * | 2016-08-19 | 2016-12-28 | 横店集团东磁股份有限公司 | A kind of stack high-temperature annealing process |
| CN106688080A (en) * | 2014-09-08 | 2017-05-17 | 三菱电机株式会社 | Semiconductor annealing apparatus |
| CN106920746A (en) * | 2015-12-25 | 2017-07-04 | 有研半导体材料有限公司 | A kind of method for improving silicon chip surface microdefect |
| CN106920745A (en) * | 2015-12-25 | 2017-07-04 | 有研半导体材料有限公司 | It is a kind of to eliminate the light method for mixing annealing silicon wafer surface COP |
| CN109137068A (en) * | 2018-08-09 | 2019-01-04 | 锦州神工半导体股份有限公司 | A kind of method for annealing of monocrystalline silicon piece |
| CN109166799A (en) * | 2018-09-05 | 2019-01-08 | 德淮半导体有限公司 | The preparation method of silicon wafer |
| CN109559988A (en) * | 2018-11-30 | 2019-04-02 | 德淮半导体有限公司 | The preparation method and device of silicon wafer |
| CN113089092A (en) * | 2019-12-23 | 2021-07-09 | 比亚迪股份有限公司 | Preparation method of silicon wafer, silicon wafer and battery piece |
| CN114182355A (en) * | 2021-11-30 | 2022-03-15 | 徐州鑫晶半导体科技有限公司 | Method for eliminating gap type defect B-swirl, silicon wafer and electronic device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004207601A (en) * | 2002-12-26 | 2004-07-22 | Sumitomo Mitsubishi Silicon Corp | Method for heat treatment of silicon wafer |
| CN1697130A (en) * | 2004-05-10 | 2005-11-16 | 希特隆股份有限公司 | Silicon wafer and method for manufacturing the same |
| US20060027161A1 (en) * | 2004-02-09 | 2006-02-09 | Sumco Corporation | Method for heat-treating silicon wafer and silicon wafer |
| JP2008227060A (en) * | 2007-03-12 | 2008-09-25 | Covalent Materials Corp | Method of manufacturing annealed wafer |
-
2012
- 2012-11-16 CN CN201210465601.0A patent/CN103820862A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004207601A (en) * | 2002-12-26 | 2004-07-22 | Sumitomo Mitsubishi Silicon Corp | Method for heat treatment of silicon wafer |
| US20060027161A1 (en) * | 2004-02-09 | 2006-02-09 | Sumco Corporation | Method for heat-treating silicon wafer and silicon wafer |
| CN1697130A (en) * | 2004-05-10 | 2005-11-16 | 希特隆股份有限公司 | Silicon wafer and method for manufacturing the same |
| JP2008227060A (en) * | 2007-03-12 | 2008-09-25 | Covalent Materials Corp | Method of manufacturing annealed wafer |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106688080A (en) * | 2014-09-08 | 2017-05-17 | 三菱电机株式会社 | Semiconductor annealing apparatus |
| CN104651946A (en) * | 2015-03-19 | 2015-05-27 | 太原理工大学 | Silicon waveguide surface smoothing process based on silicon hydrogen bond current density method |
| CN105470129A (en) * | 2015-12-01 | 2016-04-06 | 北京七星华创电子股份有限公司 | Method for eliminating impact on minority carrier diffusion length from thermal donor |
| CN105470129B (en) * | 2015-12-01 | 2018-10-16 | 北京北方华创微电子装备有限公司 | A method of eliminating oxygen Thermal donor influences minority diffusion length |
| CN106920746A (en) * | 2015-12-25 | 2017-07-04 | 有研半导体材料有限公司 | A kind of method for improving silicon chip surface microdefect |
| CN106920745A (en) * | 2015-12-25 | 2017-07-04 | 有研半导体材料有限公司 | It is a kind of to eliminate the light method for mixing annealing silicon wafer surface COP |
| CN106257625A (en) * | 2016-08-19 | 2016-12-28 | 横店集团东磁股份有限公司 | A kind of stack high-temperature annealing process |
| CN106257625B (en) * | 2016-08-19 | 2019-02-05 | 横店集团东磁股份有限公司 | A kind of stack high-temperature annealing process |
| CN109137068B (en) * | 2018-08-09 | 2020-10-16 | 锦州神工半导体股份有限公司 | Annealing method of monocrystalline silicon wafer |
| CN109137068A (en) * | 2018-08-09 | 2019-01-04 | 锦州神工半导体股份有限公司 | A kind of method for annealing of monocrystalline silicon piece |
| CN109166799A (en) * | 2018-09-05 | 2019-01-08 | 德淮半导体有限公司 | The preparation method of silicon wafer |
| CN109559988A (en) * | 2018-11-30 | 2019-04-02 | 德淮半导体有限公司 | The preparation method and device of silicon wafer |
| CN113089092A (en) * | 2019-12-23 | 2021-07-09 | 比亚迪股份有限公司 | Preparation method of silicon wafer, silicon wafer and battery piece |
| CN113089092B (en) * | 2019-12-23 | 2022-09-09 | 比亚迪股份有限公司 | Preparation method of silicon wafer, silicon wafer and battery piece |
| CN114182355A (en) * | 2021-11-30 | 2022-03-15 | 徐州鑫晶半导体科技有限公司 | Method for eliminating gap type defect B-swirl, silicon wafer and electronic device |
| WO2023098675A1 (en) * | 2021-11-30 | 2023-06-08 | 中环领先半导体材料有限公司 | Method for eliminating gap-type defect b-swirl, and silicon wafer and electronic device |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140528 |
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| RJ01 | Rejection of invention patent application after publication |