CN106920745A - It is a kind of to eliminate the light method for mixing annealing silicon wafer surface COP - Google Patents
It is a kind of to eliminate the light method for mixing annealing silicon wafer surface COP Download PDFInfo
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- CN106920745A CN106920745A CN201510993598.3A CN201510993598A CN106920745A CN 106920745 A CN106920745 A CN 106920745A CN 201510993598 A CN201510993598 A CN 201510993598A CN 106920745 A CN106920745 A CN 106920745A
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- Prior art keywords
- cop
- annealing
- hydrogen
- silicon wafer
- silicon
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 46
- 239000010703 silicon Substances 0.000 title claims abstract description 46
- 238000000137 annealing Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000002156 mixing Methods 0.000 title claims abstract description 8
- 239000001257 hydrogen Substances 0.000 claims abstract description 21
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 21
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 16
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- 150000002431 hydrogen Chemical class 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 239000002245 particle Substances 0.000 abstract description 6
- 230000007547 defect Effects 0.000 description 22
- 239000011800 void material Substances 0.000 description 17
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000011160 research Methods 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 230000008034 disappearance Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 230000001174 ascending effect Effects 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
The light method for mixing annealing silicon wafer surface COP is eliminated the invention discloses a kind of.In annealing process, it is warmed up to during 1100 DEG C at 650 DEG C from preheating temperature, adds hydrogen.Also, in annealing process, cooled to during 800 DEG C from 1100 DEG C, adding hydrogen.The flow of the hydrogen for being added is 0.1-1SLM flows.Using the method for the present invention, surface COP of silicon sheet situation is changed in annealing process, after annealing, the COP of silicon chip surface can be eliminated substantially, and reduce surface particles.
Description
Technical field
The light method for mixing annealing silicon wafer surface COP is eliminated the present invention relates to a kind of, belongs to technical field of integrated circuits.
Background technology
Silicon chip is the main backing material of modern super large-scale integration, generally by crystal pulling, section, grinding,
The integrated circuit level semiconductor silicon chip that the technical process such as burn into annealing, polishing, cleaning are made.Wherein, silicon chip is moved back
The research of fire has been carried out for many years, adds the research of hydrogen also to go deep into recent years wherein in the atmosphere during wafer anneal
Carry out, the silicon polished surface quality of vertical pulling and influence of the oxygen precipitation to ic yield are very big.No matter in silicon
Still in integrated circuit fabrication, silicon chip will be by high annealing for piece production.Therefore, high annealing is to silicon chip table
The research of face quality and oxygen precipitation influence seems particularly significant.
Product surface Crystal Originated Particle defect (COP) density has been a kind of quality standard in silicon chip production plant,
The presence of empty type (Void) defect is harmful to device manufacture, and the research on eliminating void-type defect also has
Much.To eliminate surface COP of silicon sheet s research many for high annealing under a hydrogen atmosphere, and discovery anneals 1 at 1200 DEG C
The Void defects of silicon chip near-surface region can be completely eliminated more than hour；Also it is related to by silicon chip surface extension long
The method of layer does not have void defects for manufacturing device area ensureing silicon chip；Also in monocrystalline silicon growing process
In just mix the formation of certain impurity effect void defects.Ground by eliminating void defects to rapid thermal treatment
Study carefully, it is considered that the elimination of void-type defect can be divided into two steps：The first step is silicon chip surface region at high temperature
Gap out diffusion of oxygen, concentration reduction, has so reformed into low oxygen area, empty inwall in the vicinity of void-type defect
Oxygen atom spreads in the presence of concentration gradient in silicon substrate in oxide layer, causes oxide layer inwall to die down；
Second step, void defect sturctures because the disappearance of oxide layer inwall is without being further added by, from interstitial silicon atoms and sky under high temperature
Quickly, void defects slowly contract the recombination rate of position during constantly discharging room and absorbing from interstitial silicon atoms
Small, disappearance.On heat treatment mode, time, atmosphere, temperature final effect in void defect expressivities, scholars
Though result of study and mechanism explain some difference, but there is the conclusion of consistent approval：For example temperature reaches
Silicon chip surface void defects could preferably be eliminated for more than 1100 DEG C, temperature is also higher, heat treatment time is more long, void
Defect expressivity is more notable.This eliminates void defects, control surface COPs numbers to silicon chip supplier in actual production
Mesh has directive function.
The content of the invention
In order to improve surface COP of silicon sheet situation, eliminated it is an object of the invention to provide one kind and gently mix annealing silicon wafer table
The method of face COP.
To achieve the above object, the present invention takes following technical scheme：
It is a kind of to eliminate the light method for mixing annealing silicon wafer surface COP, in annealing process, 1100 are being warmed up to from 650 DEG C
DEG C and cooled to during 800 DEG C from 1100 DEG C, add hydrogen, reach hydrogen is with the volume ratio of argon gas
0.5-8%.
During the ascending, descending temperature of high annealing, in order to the width for increasing silicon chip near surface clean area can add it is suitable
Hydrogen is measured to promote the elimination of silicon chip inside void defects.Micro hydrogen diffuses into the nearly top layer of silicon chip, promotes
The external diffusion of void defect external oxygens, so as to cause void defect outer oxide films to be easier dissolving, is conducive to follow-up
From the disappearance for entering filling, finally accelerating cavity of interstitial atom.
Preferably, the flow of the hydrogen for being added is 0.1-1SLM flows.
The advantage of the invention is that：
Using the method for the present invention, surface COP of silicon sheet situation is changed in annealing process, after annealing, silicon chip table
The COP in face can be eliminated substantially, and reduce surface particles.
Brief description of the drawings
Fig. 1 is contrast schematic diagram of the COP density to different depth before and after the annealing of heating and cooling addition hydrogen.
Specific embodiment
The present invention will be further described with reference to the accompanying drawings and examples, but is not meant to present invention protection model
The limitation enclosed.
Embodiment
It is that 300mm p-types (100) crystal orientation gently mixes B silicon chips with batch to test the sample for using, and silicon wafer thickness is about
725 μm, oxygen content is (18~32) × 10-6(ASTM79), resistivity is 10~20 Ω cm, and experiment silicon chip is equal
Take from adjacent silicon chip in czochralski silicon monocrystal.
The A412 high-temperature annealing furnaces produced with ASM companies carry out high annealing.1100 DEG C of annealing temperature, constant temperature
Time 1h, drops to during 800 DEG C being raised to 1100 DEG C and 1100 DEG C from 650 DEG C, is passed through flow for 0.3SLM
Hydrogen, it is 5.5% to control hydrogen and argon gas volume ratio, then with the surface of KLA-TENSOR companies production
Particle test instrument carries out the dependence test of silicon chip surface Crystal Originated Particle defect (COP).Then to annealing after
Silicon chip carries out returning impeller ramming to be tested, and measures COP Density Distributions, and research annealing atmosphere is distributed to void depth of defects indirectly
Influence.
The influence that trace hydrogen is eliminated in heating and cooling high annealing atmosphere to surface COP of silicon sheet, by surface particles
Tester tests COP results to weigh.In high-temperature annealing process, using lifting temperature course in be passed through hydrogen to silicon
The COP on piece surface can be eliminated all substantially, COP number average value of the silicon chip surface inside dimension more than 120nm
It is changed into 1.4 from 945.2.
Influence of the high annealing to silicon chip inside void defect expressivities, all carries out returning impeller ramming for the silicon chip after annealing
Test, skimming every time Changing Pattern of the COP density with depth of measure after about 5 μm.Heating and cooling are characterized with this indirectly
Add influence of the hydrogen high annealing to silicon chip inside void defects.Measurement result such as Fig. 1.It will be seen from figure 1 that
After annealing, COP distribution densities have a range of reduction, COP of the silicon chip surface inside dimension more than 120nm
Distribution density reduces more than 90%.
Claims (3)
1. it is a kind of to eliminate the light method for mixing annealing silicon wafer surface COP, it is characterised in that in annealing process,
From preheating temperature, 650 DEG C are warmed up to during 1100 DEG C, add hydrogen, and reach hydrogen is with the volume ratio of argon gas
0.5-8%.
It is 2. according to claim 1 to eliminate the light method for mixing annealing silicon wafer surface COP, it is characterised in that
Cooled to during 800 DEG C from 1100 DEG C, adding hydrogen, it is being 0.5-8% to reach hydrogen with the volume ratio of argon gas.
3. according to claim 1 and 2 to eliminate the light method for mixing annealing silicon wafer surface COP, its feature exists
In the flow of hydrogen is 0.1-1SLM flows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510993598.3A CN106920745A (en) | 2015-12-25 | 2015-12-25 | It is a kind of to eliminate the light method for mixing annealing silicon wafer surface COP |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510993598.3A CN106920745A (en) | 2015-12-25 | 2015-12-25 | It is a kind of to eliminate the light method for mixing annealing silicon wafer surface COP |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106920745A true CN106920745A (en) | 2017-07-04 |
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|---|---|---|---|
| CN201510993598.3A Pending CN106920745A (en) | 2015-12-25 | 2015-12-25 | It is a kind of to eliminate the light method for mixing annealing silicon wafer surface COP |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109166799A (en) * | 2018-09-05 | 2019-01-08 | 德淮半导体有限公司 | The preparation method of silicon wafer |
| EP3916481A4 (en) * | 2019-02-25 | 2022-03-30 | Air Water Inc. | Pellicle intermediate, pellicle, method for manufacturing pellicle intermediate, and method for manufacturing pellicle |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1838388A (en) * | 2005-03-21 | 2006-09-27 | 北京有色金属研究总院 | Rapid thermal process for silicon sheet capable of obtaining denuded zone and product thereof |
| CN103820862A (en) * | 2012-11-16 | 2014-05-28 | 有研半导体材料股份有限公司 | Method for preparing high-temperature annealing silicon wafer |
-
2015
- 2015-12-25 CN CN201510993598.3A patent/CN106920745A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1838388A (en) * | 2005-03-21 | 2006-09-27 | 北京有色金属研究总院 | Rapid thermal process for silicon sheet capable of obtaining denuded zone and product thereof |
| CN103820862A (en) * | 2012-11-16 | 2014-05-28 | 有研半导体材料股份有限公司 | Method for preparing high-temperature annealing silicon wafer |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109166799A (en) * | 2018-09-05 | 2019-01-08 | 德淮半导体有限公司 | The preparation method of silicon wafer |
| EP3916481A4 (en) * | 2019-02-25 | 2022-03-30 | Air Water Inc. | Pellicle intermediate, pellicle, method for manufacturing pellicle intermediate, and method for manufacturing pellicle |
| US12001136B2 (en) | 2019-02-25 | 2024-06-04 | Air Water Inc. | Pellicle intermediary body, pellicle, method for manufacturing of pellicle intermediary body, and pellicle manufacturing method |
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Application publication date: 20170704 |
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