CN103812350A - Piezoelectric pump drive power supply - Google Patents

Abstract

The invention discloses a piezoelectric pump drive power supply and belongs to the field of power supplies. The piezoelectric pump drive power supply comprises a signal source, uses low-voltage direct-current input, is low in cost and is high in precision.The piezoelectric pump drive power supply is composed of a power supply module, a control module, a pressure regulating module and an inverse module, wherein the control module is composed of a FPGA minimum system, a liquid crystal display module, a key module, a drive circuit and a detecting circuit. The piezoelectric pump drive power supply supplies power in low voltage direct current mode, the needed high voltage direct current can be automatically generated therein, so that the dependence on the external high voltage direct current is reduced; the power source for the piezoelectric pump drive power supply can be realized through a switching power supply or a battery, so that the use range is greatly broadened, and the application range of the piezoelectric pump is broadened.

Description

Piezoelectric pump driving power

Technical field

The invention belongs to field of power supplies.

Background technology

Piezoelectric pump is an important branch of piezoelectric actuator, has that volume is little, simple in structure, quality is light, energy consumption is low, does not have electromagnetic interference, can be according to advantages such as the flows of the voltage applying or FREQUENCY CONTROL output.Therefore, it is widely used in the fields such as chemical analysis, medicine equipment, aerospace vehicle, robot and supplying fuel for internal combustion engine.

After piezoelectricity pump structure is determined, its resolution and precision depend on the performance of Piezoelectric Driving power supply, existing Piezoelectric Driving power supply adopts high voltage operational amplifier to form voltage amplification, power amplification or both combined drive power supplys mostly, it has, and static properties is good, integrated level is high, advantages of simple structure and simple, but its output current is little, dynamic property is restricted, signal source and high voltage direct current need to be provided from outside, service condition harshness, and high voltage operational amplifier prevailing price is higher, applicable situation is limited, has greatly limited the development of piezoelectric pump.

Summary of the invention

The object of this invention is to provide one carries signal source, adopts low-voltage DC input, low, the high-precision piezoelectric pump driving power of cost.

The present invention is made up of power module, control module, voltage regulating module and inversion module, and wherein control module is by FPGA minimum system, LCD MODULE, key-press module, drive circuit and testing circuit, voltage regulating module and inversion module composition;

Power module: P1 is the input interface of low-tension supply, and the VCC obtaining after diode D14 and fuse F1 is divided into three tunnels: the first via is to the power switch tube drives chip power supply in system; The second tunnel is to other low-voltage power supply chip power supply in system; Third Road enters voltage regulating module, as the power supply of being adjusted;

Button and LCD MODULE: the KEY1～KEY6 of key-press module is connected with 6 I/O ports of FPGA; DB0 ~ the DB7 of LCD MODULE is data pin, is connected respectively with 13 I/O ports of FPGA;

Drive circuit: SPWM_A, SPWM_B, SPWM_C, SPWM_D connect 4 SPWM output pins of FPGA minimum system; SPWM_HO1, SPWM_LO1, SPWM_HO2, SPWM_LO2 receive 4 metal-oxide-semiconductor control ends of inverter bridge by winding displacement;

Detection module and interface circuit: adopt four road AD chip TLC2554, communicate by spi bus with FPGA, SDO, the SDI of U1 chip, SCLK, INT, CS, FS pin are connected with 6 I/O ports of FPGA respectively; A0 ~ A2 treats sampled signal for input San road, is respectively temperature feedback signal S_TFB, the voltage feedback signal S_VFB of inversion module and the voltage feedback signal VFB_P of voltage regulating module, and the line that S_TFB, S_VFB are identical with label in drive circuit is connected;

Voltage regulating module: V_pwm is output voltage, is connected to the input of inversion module, and U1 is that MOS drives chip UCC27324, and its input pin INA is connected to the PWM output pin of FPGA by winding displacement, and output pin OUTA connects the control end of MOSFET;

Inversion module: input voltage V_pwm is connected with the output voltage of voltage regulating module, SPWM_HO1, SPWM_LO1, SPWM_HO2, SPWM_LO2 is the driving signal of inverter bridge, they are connected respectively to U3 in drive circuit, the output pin that U4 is corresponding, SPWM_VS1, SPWM_VS2 is the unsteady supply in high-pressure side bias voltage, input to respectively U3 in drive circuit by winding displacement, the VS pin of U4, IFB is current feedback signal, through entering U3 after comparator U6 in overdrive circuit, the SD pin of U4, VFB is voltage feedback signal, it is drawn mutually from one of output, enter the input pin of AD sampling A/D chip in detection module and control module interface circuit, P3 is for driving signal output part, connect the input of piezoelectric pump, to drive piezoelectric pump work.

Advantage of the present invention and good effect

1, the present invention adopts low-voltage DC power supply, its inside can produce required high voltage direct current voluntarily, has reduced the dependence to outside high voltage direct current, can use Switching Power Supply or battery for its power supply, expand greatly the scope of application of the present invention, also expanded the scope of application of piezoelectric pump;

2, FPGA inside can produce sine wave, square wave and triangular wave, has reduced the dependence to outside source; These signals act on inverter bridge after ovennodulation, can produce sine wave drive signal, square wave driving signal and triangular wave and drive signal, adopt PID to control to guarantee the stable and accurate of its output signal simultaneously, can meet the demand of various piezoelectric pumps;

3, drive output type and the parameter of signal to arrange by button, optional output signal type has sine wave, square wave and triangular wave, and amplitude adjustable extent is 50～400V, and stepping is 0.5V, and frequency adjustable extent is 10～500Hz, and stepping is 0.1Hz;

4, adopt modular method for designing, control module and power model are designed respectively and making sheet, more logical winding displacement connection, to reduce intermodule electromagnetic interference, improve the reliability of power supply.

Accompanying drawing explanation

Fig. 1 is that general structure of the present invention connects block diagram;

Fig. 2 is power module circuitry figure of the present invention;

Fig. 3 is button of the present invention and Liquid Crystal Module circuit diagram;

Fig. 4 is drive circuit circuit diagram of the present invention;

Fig. 5 is detection module of the present invention and interface circuit;

Fig. 6 is voltage regulating module circuit diagram of the present invention;

Fig. 7 is inversion module circuit diagram of the present invention.

Embodiment

The present invention is made up of power module, control module, voltage regulating module and inversion module, and wherein control module is by FPGA minimum system, LCD MODULE, key-press module, drive circuit and testing circuit, voltage regulating module and inversion module composition;

Power module: P1 is the input interface of low-tension supply, and the VCC obtaining after diode D14 and fuse F1 is divided into three tunnels: the first via is to the power switch tube drives chip power supply in system; The second tunnel is to other low-voltage power supply chip power supply in system; Third Road enters voltage regulating module, as the power supply of being adjusted;

Button and LCD MODULE: the KEY1～KEY6 of key-press module is connected with 6 I/O ports of FPGA; DB0 ~ the DB7 of LCD MODULE is data pin, is connected respectively with 13 I/O ports of FPGA;

Drive circuit: SPWM_A, SPWM_B, SPWM_C, SPWM_D connect 4 SPWM output pins of FPGA minimum system; SPWM_HO1, SPWM_LO1, SPWM_HO2, SPWM_LO2 receive 4 metal-oxide-semiconductor control ends of inverter bridge by winding displacement;

Detection module and interface circuit: adopt four road AD chip TLC2554, communicate by spi bus with FPGA, SDO, the SDI of U1 chip, SCLK, INT, CS, FS pin are connected with 6 I/O ports of FPGA respectively; A0 ~ A2 treats sampled signal for input San road, is respectively temperature feedback signal S_TFB, the voltage feedback signal S_VFB of inversion module and the voltage feedback signal VFB_P of voltage regulating module, and the line that S_TFB, S_VFB are identical with label in drive circuit is connected;

Voltage regulating module: V_pwm is output voltage, is connected to the input of inversion module, and U1 is that MOS drives chip UCC27324, and its input pin INA is connected to the PWM output pin of FPGA by winding displacement, and output pin OUTA connects the control end of MOSFET;

Inversion module: input voltage V_pwm is connected with the output voltage of voltage regulating module, SPWM_HO1, SPWM_LO1, SPWM_HO2, SPWM_LO2 is the driving signal of inverter bridge, they are connected respectively to U3 in drive circuit, the output pin that U4 is corresponding, SPWM_VS1, SPWM_VS2 is the unsteady supply in high-pressure side bias voltage, input to respectively U3 in drive circuit by winding displacement, the VS pin of U4, IFB is current feedback signal, through entering U3 after comparator U6 in overdrive circuit, the SD pin of U4, VFB is voltage feedback signal, it is drawn mutually from one of output, enter the input pin of AD sampling A/D chip in detection module and control module interface circuit, P3 is for driving signal output part, connect the input of piezoelectric pump, to drive piezoelectric pump work.

Below in conjunction with accompanying drawing, the present invention is described in detail:

one, as shown in Figure 1, concrete implementation step is as follows for the general structure block diagram of novel piezoelectric pump driving power supply of the present invention:

1, as shown in Figure 1, the low-voltage DC of 12V ~ 24V is provided by Switching Power Supply or battery, is divided into 3 tunnels after inner protective circuit.The 1st road and the 2nd tunnel are respectively used to produce the direct current of 12V and 5V, give the low-voltage power supply chip power supply in power supply; The 3rd tunnel directly enters voltage regulating module, for generation of adjustable high voltage direct current.

2, as shown in Figure 1, control module is made up of several parts of FPGA minimum system, LCD MODULE, key-press module, drive circuit and testing circuit.Described FPGA minimum system is a fpga core plate, is used as processor and signal generator in system, and it can receive push button signalling and drive liquid crystal display screen to show.Can, according to the prompting on liquid crystal display screen, select the type of output wave and output wave frequency, amplitude are set by button, and control the startup of power supply and stop.In FPGA inside, the output waveform take final is controlled to drive circuit Si road SPWM ripple as signal wave, triangular wave as carrier wave is synthetic, for driving the inversion process of inverter bridge, final output and signal wave are with driving signal frequently.Testing circuit utilizes the feedback signal sampling of AD sampling A/D chip to inversion module and voltage regulating module, and passes to FPGA, for forming closed-loop control, thereby has improved the precision of output signal.

3, as shown in Figure 1, voltage regulating module be input as the low-voltage DC below 24V, be output as the adjustable direct current of 50V～400V, it is that duty by changing the PWM ripple of being exported by FPGA is recently realized pressure regulation.The output of voltage regulating module has been connected to inversion module, as the voltage for the treatment of inversion.In the time of the inner synthetic signal wave frequency shift of FPGA, the frequency of the driving signal of final output also changes thereupon, and in the time that the output voltage amplitude of voltage regulating module changes, the amplitude of the driving signal of final output also changes thereupon.

4, in Fig. 1, power module, voltage regulating module and inversion module are produced in a circuit board, are called power amplifier board, and the independent making sheet of control module, is called control board, between them, connects with winding displacement.

two, the concrete implementation step of the each module of the present invention is as follows:

1, be illustrated in figure 2 the circuit diagram of power module.The input interface that in Fig. 2, P1 is low-tension supply, the voltage range of input is 12V ~ 24V, can be by Switching Power Supply or battery-powered, this voltage obtains VCC after diode D14 and fuse F1; VCC is divided into three tunnels, the first via enters in the voltage stabilizing circuit of voltage stabilizing chip U2, capacitor C 13, capacitor C 14, inductance L 5, diode D15 formation, for generation of the direct current of 12V, power switch tube drives chip power supply in the system of giving, U2 is LM2576-12, capacitor C 13, C14 are electrochemical capacitor, and size is respectively 100uF and 1000uF, and L5 is I-shaped inductance; The second tunnel enters in the voltage stabilizing circuit of voltage stabilizing chip U3, capacitor C 15, capacitor C 16, inductance L 6, diode D16 formation, for generation of the direct current of 5V, other low-voltage power supply chip power supply in the system of giving, U3 is LM2576-5.0, other element is identical with the first via; Third Road enters voltage regulating module, as the power supply of being adjusted.

2, be illustrated in figure 3 button and the LCD MODULE circuit diagram in control module, Fig. 3 left-half is key-press module, and S1 ~ S6 is button, and C1 ~ C6 is ceramic disc capacitor 104, R1 ~ R6 is the fixed carbon resister of 10K Ω, and KEY1～KEY6 is connected with 6 I/O ports of FPGA; Fig. 3 right half part is LCD MODULE, LCD is the socket of LCDs 12864, liquid crystal display screen the 1st pin and the 20th pin ground connection, the 2nd pin and the 19th pin connect 5V power supply, connect between the 3rd pin and the 18th pin resistance of 220 Ω, P41 ~ P46 is for controlling pin, and DB0 ~ DB7 is data pin, and they are connected with 13 I/O ports of FPGA respectively.

3, be illustrated in figure 4 the circuit diagram of drive circuit, in Fig. 4, U3, U4 are power switch tube drives chip I R2110, every IR2110 can drive two metal-oxide-semiconductors up and down on a brachium pontis in full-bridge, add at the SPWM of U3, U4 ripple input HLN, LIN the interlock circuit being formed by triode and resistance, to prevent two metal-oxide-semiconductors conducting simultaneously on a brachium pontis, and cause serious consequence; SPWM_A, SPWM_B, SPWM_C, SPWM_D connect 4 SPWM output pins of FPGA minimum system; SPWM_HO1, SPWM_LO1, SPWM_HO2, SPWM_LO2 receive 4 metal-oxide-semiconductor control ends of inverter bridge by winding displacement.U6 is comparator LM393, it has two-way comparator, the current feedback signal IFB that its input signal is inverter bridge in native system, after a comparator, obtain overcurrent signal, this signal enters the overcurrent signal input pin SD pin of IR2110, to control the output of SPWM signal, the threshold voltage of comparator is by R8, R9 dividing potential drop gained, and the voltage got is here 0.65V.In Fig. 4, C31, C32, R32 are spare part, in side circuit, do not weld; C7, C8, C22, C24, C27, C29, C33, C34, C36 are ceramic disc capacitor, and withstand voltage is 16V, and C33, C36 size are followed successively by 0.01uF, 1000pF, and other capacitance size is 0.1uF; C21, C23, C25, C26, C28, C30, C35 are tantalum electric capacity, and withstand voltage is 16V, and size is 10uF; D1, D2 are fast quick-recovery diode, and model is FR107; Q5～Q8 is positive-negative-positive triode, and model is 2SA1015, also can substitute with S8550; In Fig. 4, resistance is fixed carbon resister, power is 0.25W, R9, R22, R24, R26, R28, R30, R31, R34 size are 10K Ω, R7, R8 size are 100 Ω, R33 size is 1K Ω, R35 size is 1.5K Ω, and R23, R25, R27, R29 size are 5.1 K Ω, and R50 is 100K Ω.

4, Figure 5 shows that the circuit diagram of detection module and control module interface circuit, U1Wei tetra-road AD chip TLC2554 in Fig. 5, itself and FPGA communicate by spi bus, SDO, the SDI of U1 chip, SCLK, INT, CS, FS pin are connected with 6 I/O ports of FPGA respectively, for reading gathered magnitude of voltage.The wire that number in the figure is identical links together in side circuit plate.A0 ~ A2 is for treating sampled signal in input San road, they are respectively temperature feedback signal S_TFB, the voltage feedback signal S_VFB of inversion module and the voltage feedback signal VFB_P of voltage regulating module, the line that S_TFB, S_VFB are identical with label in Fig. 4 is connected, and the port that VFB_P is corresponding with P3 interface is connected; P3 is winding displacement seat, and each port is all connected with holding wire or power line identical in control board, also has a winding displacement seat for correspondence with it in power amplifier board, between them, is connected by winding displacement.

5, be illustrated in figure 6 voltage regulating module circuit diagram, voltage regulating module adopts Boost circuit theory to build.In figure, VCC is adjusted voltage, provided by power module, V_pwm is output voltage, be connected to the input of inversion module, in figure, U1 is that MOS drives chip UCC27324, its input pin INA is connected to the PWM output pin of FPGA by winding displacement, output pin OUTA connects the control end of MOSFET after by resistance R 14.Inductance L 2, L3, L4 and diode D6～D11 form inductive bank, and V5 is metal-oxide-semiconductor, and model is IRF840, and resistance R 14, R15 and diode D12 form the protection loop of metal-oxide-semiconductor.Capacitor C 9 ~ C11 forms filter circuit, and resistance R 16 ~ R19 forms voltage feedback loop, and feedback voltage V FB_P is by R19 and R16 ~ R18 dividing potential drop gained.In figure, L2 ~ L4 is linear inductance, and size is 200uH; D6～D11 and D13 are fast quick-recovery rectification diode, and model is 1N3940, and D12 is fast quick-recovery diode, model 1N4148; C9, C10 are polyester capacitance, and withstand voltage is 630V, and size is respectively 47uF, 1uF, and C11 is electrochemical capacitor, and size is 100uF, and C12 is ceramic disc capacitor, and size is 0.01uF; R14 ~ R19 is fixed carbon resister, and size is respectively 4.7 Ω, 10K Ω, 1M Ω, 1M Ω, 1M Ω, 27K Ω.

6, be illustrated in figure 7 the circuit diagram of inversion module, in Fig. 7, input voltage V_pwm is connected with the output voltage of voltage regulating module in Fig. 6, and input voltage enters inverter bridge after capacitor C 1, C2 filtering; The driving signal that SPWM_HO1, SPWM_LO1, SPWM_HO2, SPWM_LO2 are inverter bridge, they have been connected to output pin corresponding to U3, U4 in Fig. 4 drive circuit by winding displacement respectively; Inductance L 1 plays afterflow and level and smooth.SPWM_VS1, SPWM_VS2 are the unsteady supply in high-pressure side bias voltage, input to respectively the VS pin of U3, U4 in Fig. 4 drive circuit by winding displacement; IFB is current feedback signal, and the SD pin that it enters U3, U4 after comparator U6 in Fig. 4, plays overcurrent protection effect; VFB is voltage feedback signal, it is drawn mutually from one of output, after the sinewave output voltage-regulating circuit adjustment forming through R13, R1, R2, C6, C7, finally enter the input pin of AD sampling A/D chip in Fig. 5, can regulate its maximum output voltage by locator R1, so that it meets sampling A/D chip measuring range; TFB is temperature feedback signal, and its value is obtained by corresponding resistor dividing potential drop in thermistor RT1 and Fig. 4, and thermistor RT1 is attached on the fin of metal-oxide-semiconductor V1 ~ V4, to react the temperature of metal-oxide-semiconductor; P3, for driving signal output part, connects the input of piezoelectric pump, to drive piezoelectric pump work.In Fig. 7, C1, C2 are electrochemical capacitor, and withstand voltage is 450V, and size is respectively 47uF, 100uF; C3 ~ C5 is CBB electric capacity, and withstand voltage is 630V, and size is respectively 0.1uF, 0.1uF, 2.2uF; C6, C8 are ceramic disc capacitor, and withstand voltage is 16V, and size is respectively 0.1uF, 0.01uF; C7 is electrochemical capacitor, and withstand voltage is 16V, and size is 4.7uF; D1 is fast quick-recovery diode, and model is 1N5408; D2 ~ D5 is fast quick-recovery diode, and model is 1N4148; V1 ~ V4 is N-channel MOS pipe, and model is IRF840; R11, R12 are constantan wire, and diameter is 1mm, and size is 0.01 Ω; R13, R2 are fixed carbon resister, and power is 0.25W, and size is respectively 200K Ω, 10K Ω; R1 is locator, and size is 10K Ω; RT1 is NTC type thermistor, and size is 10K Ω.

three, voltage-regulation principle

Can make the transfer ratio of boosting (multiplication factor) of voltage regulating module improve 3 times, i.e. transfer ratio by the known inductive bank being formed by three inductance and corresponding diode of patent of invention " high booster circuit (application number: 200410049172.4) " , D is the duty ratio of PWM ripple, known in the time changing the duty ratio of PWM, transfer ratio changes thereupon.Voltage regulating module take input voltage as 12V describes as example, known output voltage in the ideal situation

, when duty ratio is during in 0.5814 to 0.9174 interior continuous variation, output voltage V _ pwm can change continuously in 50V～400V.In practical application, FPGA, according to the value of feedback of set point and output voltage, utilizes pid algorithm to provide rational duty ratio, so that its stable output and accurately voltage.

four, carry signal source signal and produce principle

1, first will by the various signal waves of one-period (sinusoidal wave, square wave and triangular wave) and carrier wave, (triangular wave carries out digitlization, then deposits in the internal storage of FPGA.Method is as follows: (1) is divided into 4096 part by amplitude at the one-period of the signal wave of 0 to 2 interior variation with MATLAB, the corresponding range value of each Along ent, range value is amplified to 2048 times and round, obtain one be longly 4096, word wide is the sequence of 12, this sequence is kept in HEX file successively; (2) generate the ROM piece that a size is 4096, bit wide is 12, the HEX file that invocation step (1) obtains by the programmed environment of FPGA; (3), at this ROM piece of FPGA Calling, a digitized waveform must be deposited in the internal storage of FPGA.

2, adopt Direct Digital Synthesizer (DDS) principle, the shaping variable that first defines one 40 is that frequency accumulator, the shaping variable of 12 are frequency control word (initial value of frequency control word is determined by the frequency of the output drive signal setting), then define A, B, C, D are four output pins of SPWM ripple.Take sine wave as example, the production method of waveform is described: frequency accumulator value adds that frequency control word value obtains new frequency accumulator value within each clock cycle, get the address of front 12 sinusoidal wave ROM pieces that obtain as step 1 of new frequency accumulator value, utilize this address from the internal storage of FPGA, to take out corresponding sinusoidal wave range value, so go round and begin again, just can obtain a sine wave.The frequency control word value of carrier wave is 256 times of signal wave frequency control word value, thereby the carrier frequency generating is 256 times of signal wave frequency.

3, FPGA produces the range value of a signal wave and the range value of a carrier wave within each clock cycle, and compares, thereby determines the level of A, B, C, tetra-output pins of D.Method is as follows: in the time that signal wave amplitude is more than or equal to carrier amplitude, and A, D pin output high level, B, C pin output low level; In the time that signal wave amplitude is less than carrier amplitude, A, D pin output low level, B, C pin output high level, so just produced the SPWM signal for driving inverter bridge, and A, B, C, tetra-output pins of D drive respectively four power switch pipe V1 ~ V4 of inverter bridge.

Claims (1)

1. a piezoelectric pump driving power, it is characterized in that: formed by power module, control module, voltage regulating module and inversion module, wherein control module is by FPGA minimum system, LCD MODULE, key-press module, drive circuit and testing circuit, voltage regulating module and inversion module composition;

Power module: P1 is the input interface of low-tension supply, and the VCC obtaining after diode D14 and fuse F1 is divided into three tunnels: the first via is to the power switch tube drives chip power supply in system; The second tunnel is to other low-voltage power supply chip power supply in system; Third Road enters voltage regulating module, as the power supply of being adjusted;

Button and LCD MODULE: the KEY1～KEY6 of key-press module is connected with 6 I/O ports of FPGA; DB0 ~ the DB7 of LCD MODULE is data pin, is connected respectively with 13 I/O ports of FPGA;

Drive circuit: SPWM_A, SPWM_B, SPWM_C, SPWM_D connect 4 SPWM output pins of FPGA minimum system; SPWM_HO1, SPWM_LO1, SPWM_HO2, SPWM_LO2 receive 4 metal-oxide-semiconductor control ends of inverter bridge by winding displacement;

Detection module and interface circuit: adopt four road AD chip TLC2554, communicate by spi bus with FPGA, SDO, the SDI of U1 chip, SCLK, INT, CS, FS pin are connected with 6 I/O ports of FPGA respectively; A0 ~ A2 treats sampled signal for input San road, is respectively temperature feedback signal S_TFB, the voltage feedback signal S_VFB of inversion module and the voltage feedback signal VFB_P of voltage regulating module, and the line that S_TFB, S_VFB are identical with label in drive circuit is connected;

Voltage regulating module: V_pwm is output voltage, is connected to the input of inversion module, and U1 is that MOS drives chip UCC27324, and its input pin INA is connected to the PWM output pin of FPGA by winding displacement, and output pin OUTA connects the control end of MOSFET;

Inversion module: input voltage V_pwm is connected with the output voltage of voltage regulating module, SPWM_HO1, SPWM_LO1, SPWM_HO2, SPWM_LO2 is the driving signal of inverter bridge, they are connected respectively to U3 in drive circuit, the output pin that U4 is corresponding, SPWM_VS1, SPWM_VS2 is the unsteady supply in high-pressure side bias voltage, input to respectively U3 in drive circuit by winding displacement, the VS pin of U4, IFB is current feedback signal, through entering U3 after comparator U6 in overdrive circuit, the SD pin of U4, VFB is voltage feedback signal, it is drawn mutually from one of output, enter the input pin of AD sampling A/D chip in detection module and control module interface circuit, P3 is for driving signal output part, connect the input of piezoelectric pump, to drive piezoelectric pump work.

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