CN103811650A - Vertical structure LED high-voltage chip free of metal electrodes - Google Patents
Vertical structure LED high-voltage chip free of metal electrodes Download PDFInfo
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- CN103811650A CN103811650A CN201210452506.7A CN201210452506A CN103811650A CN 103811650 A CN103811650 A CN 103811650A CN 201210452506 A CN201210452506 A CN 201210452506A CN 103811650 A CN103811650 A CN 103811650A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0075—Processes relating to semiconductor body packages relating to heat extraction or cooling elements
Abstract
The invention discloses a vertical structure LED high-voltage chip free of metal electrodes. The LED high-voltage chip comprises a supporting substrate and at least two unit semiconductor epitaxial films. The supporting substrate comprises an insulating supporting substrate, a conductive supporting substrate, a through hole insulating supporting substrate and a through hole conductive supporting substrate. The unit semiconductor epitaxial films are in bonding with the supporting substrate, and a growth substrate is stripped. The adjacent unit semiconductor epitaxial films are electrically connected through transparent intermediate connection electrodes. All unit chips are connected in a series connection mode to form the vertical structure LED high-voltage chip free of the metal electrodes. All the unit chips are connected in a rectifier bridge mode or connected in a series-parallel connection mode to form the vertical structure LED high-voltage chip free of the metal electrodes.
Description
Technical field
The present invention relates to LED high voltage direct current or interchange chip without the vertical stratification of metal electrode.
Background technology
Patent application 2008101694391 discloses the LED high voltage direct current chip of positive assembling structure.One of method of fast reducing lighting cost is to adopt high current density to drive, and still, the chip of positive assembling structure, in the time that high current density drives, can face the problem of poor heat radiation.In order to solve heat dissipation problem, patent 2010105840892 discloses the LED high voltage direct current chip of vertical stratification.But the price of gold and other metals improves increasingly, the cost of metal electrode also improves thereupon.In addition, LED communication day by day develops, need to be compared with the LED chip of high switching speed.
In order to make LED enter faster huge general illumination field, still need the performance of the LED high voltage direct current chip that further improves positive assembling structure and vertical stratification and reduce production costs.The little improvement in any point in product structure and the production technology of the LED high voltage direct current chip of positive assembling structure and vertical stratification and the raising of chip performance and the reduction of production cost that bring, the speed that LED enters general illumination market is accelerated in capital, produces huge economic benefit.
Therefore, need a kind ofly to solve heat dissipation problem, can adopt large driven current density, production cost is lower, can reduce LED light fixture cost, have the LED high voltage direct current of high switching speed or exchange chip.
Summary of the invention
The object of this invention is to provide a kind of LED high pressure chip that solves heat dissipation problem, large driven current density, reduces production costs, reduces the vertical stratification without metal electrode of LED light fixture cost, high switching speed.Preferably, provide a kind of LED high pressure chip of the vertical stratification without metal electrode without beating gold thread.
In the context of the present invention, LED high pressure chip without the vertical stratification of metal electrode comprises, without the LED high voltage direct current chip of the vertical stratification of metal electrode, without the LED high-voltage alternating chip of the vertical stratification of metal electrode, without the LED high voltage direct current chip of the vertical stratification without metal electrode of beating gold thread, without the LED high-voltage alternating chip of the vertical stratification without metal electrode of beating gold thread.
Without an embodiment of the LED high pressure chip of the vertical stratification of metal electrode, comprising:
(1) support substrate;
(2) pad of discrete conduction; Pad comprises, first electrode pad, pad in the middle of at least one, second electrode pad; The first electrode pad, the second electrode pad and middle pad are formed on to be supported on substrate; The first electrode pad, the second electrode pad and middle pad and support substrate electric insulation;
(3) at least two discrete elemental semiconductor epitaxial films: elemental semiconductor epitaxial film comprises: first kind limiting layer, active layer and Second Type limiting layer; The first kind limiting layer of elemental semiconductor epitaxial film is bonded in respectively on the precalculated position of the first electrode pad and middle pad and a part for the first electrode pad and middle pad is exposed; On the second electrode pad, there is no bonding elemental semiconductor epitaxial film;
(4) quantity of pad than the quantity of elemental semiconductor epitaxial film many one, on the second electrode pad, does not have bonding elemental semiconductor epitaxial film.
(5) each pad and bonding elemental semiconductor epitaxial film Component units chip thereon;
(6) passivation layer: passivation layer is layered on the surface and side of each unit chip and the second electrode pad; Passivation layer has the window of reservation shape above the preposition of the Second Type limiting layer of elemental semiconductor epitaxial film, and a part for Second Type limiting layer exposes in window; Passivation layer has respectively the window of reservation shape above the preposition of the part of the exposure of the first electrode pad and middle pad, and a part for the first electrode pad and a part for middle pad expose in window; Passivation layer has the window of reservation shape above the preposition of the second electrode pad, and a part for the second electrode pad exposes in window;
(7) at least one transparent middle connecting electrode: transparent middle connecting electrode comprises the first transparent middle connecting electrode, the second transparent middle connecting electrode, transparent middle p-n-connecting electrode; Wherein, the first middle connecting electrode is the window above the Second Type limiting layer of an elemental semiconductor epitaxial film by passivation layer, is layered on Second Type limiting layer; In the middle of second connecting electrode by passivation layer the window above middle the pad of a stacked elemental semiconductor epitaxial film on it, be layered on the pad of centre; Middle p-n-connecting electrode couples together at least one first middle connecting electrode and at least one second middle connecting electrode;
(8) transparent connecting electrodes: transparent connecting electrode comprises the first transparent connecting electrode, the second transparent connecting electrode, transparent p-n-connecting electrode; Wherein, the first connecting electrode is the window above the Second Type limiting layer of an elemental semiconductor epitaxial film by passivation layer, is layered on Second Type limiting layer; The second connecting electrode is the window above the second electrode pad by passivation layer, is layered on the second electrode pad; P-n-connecting electrode couples together the first connecting electrode and the second connecting electrode.
Support substrate comprises: substrate is supported in (1) insulation; On the first surface of insulation support substrate, form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad.(2) conductive support substrate; On the first surface of conductive support substrate, form a layer insulating, on insulating barrier, form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad.(3) substrate is supported in through hole insulation; Through hole insulation is supported to form at least one first through hole and second through hole in substrate, in the first through hole and the second through hole, form respectively the first filler plug of conduction and the second filler plug of conduction, on the first surface of through hole insulation support substrate, form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad; On the second surface of through hole insulation support substrate, form discrete the first power pad and second source pad mutually; The first power pad and second source pad are formed and are electrically connected by the first electrode pad on the first filler plug and the second filler plug of conduction and the first surface of through hole insulation support substrate that conduct electricity and the second electrode pad respectively.(4) through hole conductive support substrate; On the first surface of through hole conductive support substrate and second surface, form respectively the first insulating barrier and the second insulating barrier; In through hole conductive support substrate and the first insulating barrier and the second insulating barrier, form at least one first through hole and at least one second through hole, in first through hole and the second through hole, form respectively the first filler plug of insulation and the second filler plug of insulation, in the first filler plug of insulation and the second filler plug of insulation, form respectively the first filler plug of conduction and the second filler plug of conduction, the first filler plug of conduction and the second filler plug of conduction and the mutual electric insulation of through hole conductive support substrate; On the first insulating barrier on the first surface of through hole conductive support substrate, form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad; On the second insulating barrier on the second surface of through hole conductive support substrate, form mutually discrete the first power pad and second source pad, the first power pad and second source pad are formed and are electrically connected with the first electrode pad on the first surface of through hole conductive support substrate and the second electrode pad respectively by the first filler plug of conduction and the second filler plug of conduction.
Without another embodiment of the LED high pressure chip of the vertical stratification of metal electrode, comprising:
(1) support substrate; Support substrate comprises, insulation support substrate; With the conductive support substrate of insulating barrier;
(2) pad of discrete conduction; Pad comprises, first electrode pad, pad in the middle of at least one; The first electrode pad and middle pad are formed on to be supported on substrate; The first electrode pad and middle pad and support substrate electric insulation;
(3) at least two discrete elemental semiconductor epitaxial films: elemental semiconductor epitaxial film comprises: first kind limiting layer, active layer and Second Type limiting layer; The described first kind limiting layer of elemental semiconductor epitaxial film is bonded in respectively on the precalculated position of the first electrode pad and middle pad and a part for the first electrode pad and middle pad is exposed;
(4) quantity of pad is identical with the quantity of elemental semiconductor epitaxial film, elemental semiconductor epitaxial film of surface bond of each pad.
(5) each elemental semiconductor epitaxial film and its bonding pad forming unit chip thereon;
(6) passivation layer: passivation layer is layered on the surface and side of each unit chip; Passivation layer has the window of reservation shape above the preposition of the Second Type limiting layer of elemental semiconductor epitaxial film, and a part for Second Type limiting layer exposes in window; Passivation layer has respectively the window of reservation shape above the preposition of the part of the exposure of the first electrode pad and middle pad, and a part for the first electrode pad and middle pad exposes respectively in window;
(7) at least one transparent middle connecting electrode: transparent middle connecting electrode comprises the first transparent middle connecting electrode, the second transparent middle connecting electrode, transparent middle p-n-connecting electrode; Wherein, the first middle connecting electrode is the window above the Second Type limiting layer of an elemental semiconductor epitaxial film by passivation layer, is layered on Second Type limiting layer; In the middle of second connecting electrode by passivation layer the window above middle the pad of a stacked elemental semiconductor epitaxial film on it, be layered on the pad of centre; Middle p-n-connecting electrode couples together at least one first middle connecting electrode and at least one second middle connecting electrode;
(8) the second transparent electrode: the second electrode is the window above the Second Type limiting layer of an elemental semiconductor epitaxial film by passivation layer, is layered on Second Type limiting layer.
The LED high pressure chip of the vertical stratification without metal electrode of the present invention, middle p-n-connecting electrode is to select from one group of connected mode the connected mode that in the middle of the first middle connecting electrode and second, connecting electrode couples together, this group connected mode comprises:
The connecting electrode window above the middle pad of the exposure of the window above the Second Type limiting layer of an elemental semiconductor epitaxial film and adjacent unit chip by passivation layer respectively in the middle of connecting electrode and second in the middle of (1) first, be layered on the middle pad of the Second Type limiting layer of an elemental semiconductor epitaxial film and the exposure of adjacent unit chip, middle p-n-connecting electrode forms the first middle connecting electrode and the second middle connecting electrode on the middle pad of adjacent unit chip the electrical connection of series connection form, all unit chip connects with series system, form the LED high voltage direct current chip without the vertical stratification of metal electrode.
(2) in the middle of, p-n-connecting electrode forms a node the first middle connecting electrode on the Second Type limiting layer of an elemental semiconductor epitaxial film and two second middle connecting electrodes formation electrical connections on the middle pad of two other adjacent unit chip, middle p-n-connecting electrode forms another node the second middle connecting electrode on the middle pad of a unit chip and two first middle connecting electrodes formation electrical connections on the Second Type limiting layer of two other adjacent elemental semiconductor epitaxial film, , rectifier bridge comprises at least two nodes, at Nodes, connecting electrode is connected the dissimilar limiting layer of the limiting layer of the same type of two elemental semiconductor epitaxial films and another elemental semiconductor epitaxial film, all unit chip is electrically connected with rectifier bridge form, form the LED high-voltage alternating chip without the vertical stratification of metal electrode.
The unit chip of (3) two groups of equal numbers is electrically connected with series connection form respectively, the unit chip of two groups of series connection is electrically connected with reverse parallel connection form,, connecting electrode connects the mode that all unit chip mixes with series and parallel connections, forms the LED high-voltage alternating chip without the vertical stratification of metal electrode.
Transparent middle connecting electrode, transparent connecting electrode, the second transparent electrode have single-layer electrodes structure or multi-layer electrode structure, and every layer of electrode is to select from one group of electrode, and this group electrode comprises, the metal oxide of conduction, thin metal film.
An embodiment: transparent middle connecting electrode, transparent connecting electrode and/or the second transparent electrode have single-layer electrodes structure, and this monolayer material is thin metal film, its thickness is in nanometer scale, less 10 times than the thickness of metal electrode, reduces production costs.
An embodiment: middle connecting electrode, connecting electrode, the second electrode have the structure of individual layer, this monolayer material is the metal oxide of transparent conduction, as ITO, etc.
An embodiment: middle connecting electrode, connecting electrode, the second electrode have two-layer structure, and this two layers of material is: one deck is the metal oxide (as ITO) of transparent conduction, another layer is thin metal film etc.
Preferred embodiment: middle connecting electrode, connecting electrode, the second electrode have identical structure.
Insulation supports that substrate comprises, aluminium oxide ceramics is supported substrate, and aluminium nitride ceramics is supported substrate, etc.Conductive support substrate comprises, tungsten copper support substrate, etc.Through hole insulation supports that substrate comprises, the low-temperature oxidation aluminium pottery that forms through hole supports substrate or aluminium nitride ceramics to support substrate, and the high temperature alumina pottery that forms through hole supports substrate or aluminium nitride ceramics to support substrate.Through hole conductive support substrate comprises, forms the tungsten copper support substrate of through hole, etc.
Therefore, there is high heat-sinking capability without the LED high pressure chip of the vertical stratification of metal electrode, the density of high drive current, low production cost, reduces the cost of LED light fixture.
Following description is applicable to all embodiments of the present invention.
(1) in figure, the ratio of each several part does not represent the ratio of actual products.
(2) in Fig. 2 to Fig. 4, a LED high pressure chip without the vertical stratification of metal electrode only includes two unit chips, and still, the LED high pressure chip of the vertical stratification without metal electrode of the present invention can comprise more than two unit chips.
(3) material of elemental semiconductor epitaxial film is to select from one group of material, and this group material comprises: (a) gallium nitride-based material; Described gallium nitride-based material comprises, GaN, AlGaN, GaInN, AlGaInN; (b) gallium phosphide sill; Described gallium phosphide sill comprises, GaP, AlGaP, GaInP, AlGaInP; (c) nitrogen phosphorus gallium sill; Described nitrogen phosphorus gallium material comprises, GaNP, AlGaNP, GaInNP, AlGaInNP; (d) Zinc oxide-base material, comprises, ZnO.
(4) material of passivation layer and insulating barrier is to select from one group of material, this group material comprises, silica gel (silicone), resin (epoxy), silica (SiO2), silicon nitride, silicon-on-glass (SOG), polyimides (polyimide), glass, polymethyl methacrylate (polymethylmethacrylate), acrylic acid (acrylic), etc.
(5) in the middle of, connecting electrode, connecting electrode and/or the second electrode have single or multiple lift structure: the material of every one deck is to select from one group of material, this group material comprises, conductive oxide material, metal material, nano silver wire, carbon nano-tube, Graphene; Described conductive oxide material comprises: ITO (tin indium oxide), IZO (indium zinc oxide), CTO (cadmium tin), ZnO:Al, AuAlO2, LaCuOS, CuGaO, SrCuO2, ZnGa2O4, SnO2:Sb, Ga2O3:Sn, In2O3:Zn, NiO, MnO, CuO, SnO, GaO, FTO; Described metal material comprises: Al, Ag, Au, Ni/Au, Ni/Pt, Ni/Pd, Ni/Co, Pd/Au, Pt/Au, Ti/Au, Cr/Au, Sn/Au, Zr, Hf, V, Nb.
In the middle of (6) first, connecting electrode and the second middle connecting electrode be not on same unit chip.
(7) support that substrate is to support to select substrate from one group, this group supports that substrate comprises: substrate is supported in insulation, conductive support substrate, and substrate, through hole conductive support substrate are supported in through hole insulation; Wherein, (a) substrate is supported in insulation; On the first surface of insulation support substrate, form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad.(b) conductive support substrate; On the first surface of conductive support substrate, form a layer insulating, on insulating barrier, form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad.(c) substrate is supported in through hole insulation; Through hole insulation is supported to form at least one first through hole and second through hole in substrate, in the first through hole and the second through hole, form respectively the first filler plug of conduction and the second filler plug of conduction, on the first surface of through hole insulation support substrate, form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad; On the second surface of through hole insulation support substrate, form discrete the first power pad and second source pad mutually; The first power pad and second source pad are formed and are electrically connected by the first electrode pad on the first filler plug and the second filler plug of conduction and the first surface of through hole insulation support substrate that conduct electricity and the second electrode pad respectively.(d) through hole conductive support substrate; On the first surface of through hole conductive support substrate and second surface, form respectively the first insulating barrier and the second insulating barrier; In through hole conductive support substrate and the first insulating barrier and the second insulating barrier, form at least one first through hole and at least one second through hole, in first through hole and the second through hole, form respectively the first filler plug of insulation and the second filler plug of insulation, in the first filler plug of insulation and the second filler plug of insulation, form respectively the first filler plug of conduction and the second filler plug of conduction, the first filler plug of conduction and the second filler plug of conduction and the mutual electric insulation of through hole conductive support substrate; On the first insulating barrier on the first surface of through hole conductive support substrate, form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad; On the second insulating barrier on the second surface of through hole conductive support substrate, form mutually discrete the first power pad and second source pad, the first power pad and second source pad are formed and are electrically connected with the first electrode pad on the first surface of through hole conductive support substrate and the second electrode pad respectively by the first filler plug of conduction and the second filler plug of conduction.
(8) in the middle of, p-n-connecting electrode couples together connecting electrode in the middle of the first middle connecting electrode and second, connected mode comprises: (a) two adjacent unit chips are formed to the electrical connection of series connection form,, the second connecting electrode of an elemental semiconductor epitaxial film is connected with the middle pad of an adjacent unit chip, makes two adjacent elemental semiconductor epitaxial films form the electrical connection of series connection forms; (b) connecting electrode in the middle of first on an elemental semiconductor epitaxial film is connected with the second centre connecting electrode of middle the pad of adjacent two unit chips, makes the electrical connection of a node of three adjacent elemental semiconductor epitaxial films formation bridge circuits; (c) the middle pad of a unit chip second in the middle of connecting electrode be connected with connecting electrode in the middle of first on adjacent two elemental semiconductor epitaxial films, make the electrical connection of another node of three adjacent elemental semiconductor epitaxial films formation bridge circuits; (d) the electrical connection of the unit chip formation reverse parallel connection form of two unit chips or two string series connection,, the second middle connecting electrode of a unit chip is connected with the first electrode pad of another unit chip, the first middle connecting electrode of a unit chip is connected with the second electrode pad.
(9) for a chip, the first electrode pad only has one, will be connected with an electrode of extraneous power supply; The second electrode pad only has one, will be connected with another electrode of extraneous power supply; Middle pad has at least one.Some embodiment has the second electrode pad, and some embodiment does not have the second electrode pad, but has the second electrode (the second electrode is connected with extraneous power supply by beating gold thread).The first electrode pad comprises with the connected mode of extraneous power supply respectively with the second electrode pad: (a) directly the first electrode pad and the second electrode pad are connected with the positive and negative electrode of extraneous power supply respectively by beating gold thread, (b) the first electrode pad is connected with second source pad with the first power pad respectively by the first and second filler plugs of conduction with the second electrode pad, the first power pad is connected with the positive and negative electrode of extraneous power supply respectively with second source pad.
(10) growth substrates comprises, Sapphire Substrate, silicon carbide substrates, gallium nitride substrate, glass substrate, and graphite substrate, gallium arsenide substrate, silicon substrate, etc.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 e shows respectively the sectional view of some embodiments of the support substrate of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.
Fig. 2 a to Fig. 2 c shows the sectional view of an embodiment of the part manufacturing process of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.
Fig. 2 d, Fig. 2 e show respectively the sectional view of the different embodiments of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.
Fig. 3 a, Fig. 3 b show the sectional view of an embodiment of the part manufacturing process of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.
Fig. 4 a, Fig. 4 b show the sectional view of an embodiment of the part manufacturing process of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.
Fig. 5 a, Fig. 5 b, Fig. 5 c show respectively the high voltage direct current and the equivalent circuit diagram that exchanges chip of inverted structure of the present invention.
The implication of the numerical chracter representative in figure is as follows:
101a represents insulation support substrate;
101b represents conductive support substrate;
101c represents through hole insulation support substrate;
101d represents through hole conductive support substrate;
102a, 102b, 102c respectively presentation layer are stacked in the first electrode pad, the second electrode pad, the middle pad supported on substrate first surface;
103a presentation layer is stacked in the insulating barrier on conductive support substrate first surface;
103b, 103c respectively presentation layer are stacked in the first insulating barrier and the second insulating barrier on through hole conductive support substrate first surface and second surface;
104a, 104b respectively presentation layer are stacked in through hole insulation and support the first power pad and the second source pad on the second surface of substrate and through hole conductive support substrate; 104a, 104b will be connected with two electrodes of extraneous power supply respectively;
104c presentation layer is stacked in through hole insulation and supports the heat conducting disk on the second surface of substrate and through hole conductive support substrate;
110a, 110b represent to be respectively formed on through hole insulation and support the first filler plug of conduction and the second filler plug of conduction in substrate;
111a, 111b represent to be respectively formed on the first filler plug of insulation and the second filler plug of insulation in the first through hole and the second through hole in through hole conductive support substrate;
112a, 112b represent to be respectively formed on the first filler plug of conduction and the second filler plug of conduction in the first filler plug of insulation and the second filler plug 111a, the 111b of insulation;
120 represent growth substrates;
130a, 130b represent to be respectively formed on the elemental semiconductor epitaxial film in growth substrates;
140 represent passivation layer;
150a, 150b, 150c, 150d, 150e are illustrated respectively in the Second Type limiting layer of the first electrode pad of supporting on substrate first surface, the Second Type limiting layer of elemental semiconductor epitaxial film, middle pad, adjacent elemental semiconductor epitaxial film, the window forming in passivation layer of the second electrode pad top, in window, the Second Type limiting layer of the Second Type limiting layer of corresponding the first electrode pad, elemental semiconductor epitaxial film, middle pad, adjacent elemental semiconductor epitaxial film, the surface of the second electrode pad expose;
160a, 160b, 160c represent respectively the first middle connecting electrode, the second middle connecting electrode, middle p-n-connecting electrode; Be layered in connecting electrode 160a in the middle of first on the first kind limiting layer 130a of exposure of an elemental semiconductor epitaxial film, the the lip-deep second middle connecting electrode 160b that is layered in the exposure of the middle pad of another adjacent unit chip, forms with connecting electrode 160a in the middle of first the middle p-n-connecting electrode 160c being electrically connected the second middle connecting electrode 160b;
161a, 161b, 161c represent respectively the first connecting electrode, the second connecting electrode, p-n-connecting electrode; The second connecting electrode is layered on the second electrode pad;
170 represent the second electrode;
180a, 180b represent respectively the gold thread being connected with extraneous power supply;
501,502,503 represent respectively to form the multiple unit chip being connected in series;
504 and 505 represent respectively to form the multiple unit chip being connected in series;
506 and 507 represent respectively to form the multiple unit chip being connected in series;
504 of series connection is connected with 506 and 507 reverse parallel connections of series connection with 505;
510,511,512,513,514,515 represent respectively to form multiple unit chip that rectifying bridge type connects;
520 and 521 represent respectively two nodes of rectifier bridge.
Embodiment
For making object, technical scheme and the advantage of embodiment of the present invention clearer, below in conjunction with the accompanying drawing in embodiment of the present invention, technical scheme in embodiment of the present invention is clearly and completely described, obviously, described embodiment is a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Attention: below in all embodiments, although the LED high pressure chip of the vertical stratification without metal electrode of showing in figure only includes two unit chips, but the LED high pressure chip of the vertical stratification without metal electrode of the present invention can comprise more than two unit chips.
Fig. 1 a to Fig. 1 e shows respectively the sectional view of the different embodiments of the support substrate of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.
Fig. 1 a shows insulation support substrate 101a, being layered in insulation and supporting the first discrete electrode pad 102a, the middle pad 102c on the first surface of substrate 101a.
Fig. 1 b shows conductive support substrate 101b, is layered in the insulating barrier 103a on the first surface of conductive support substrate 101b, is layered in the first discrete electrode pad 102a on insulating barrier 103a, middle pad 102c.
Fig. 1 c shows through hole insulation support substrate 101c, be formed at least one first through hole wherein and at least one second through hole and be formed on the first through hole and the second through hole in the first filler plug of conduction and the second filler plug 110a and 110b of conduction, be layered in through hole insulation and support the first discrete electrode pad 102a, middle pad 102c, the second electrode pad 102b on the first surface of substrate 101c, be layered in through hole insulation and support the first discrete power pad 104a, second source pad 104b, the heat conducting disk 104c on the second surface of substrate 101c.
Attention: in Fig. 1 c, the first through hole comprises two through holes, and the second through hole comprises two through holes, and in order to dispel the heat, through hole can have multiple.
The first electrode pad 102a and the first power pad 104a form electrical connection by the first filler plug 110a of conduction; The second electrode pad 102b and second source pad 104b form electrical connection by the second filler plug 110b of conduction.
It is basic identical that the through hole insulation of Fig. 1 d displaying supports that substrate 101c and Fig. 1 c show, difference is there is no heat conducting disk on the second surface of through hole insulation support substrate 101c.
Fig. 1 e shows through hole conductive support substrate 101d, comprise, be respectively formed at the first insulating barrier 103b and the second insulating barrier 103c on its first and second surface, through through hole conductive support substrate 101d, at least one first through hole of the first insulating barrier 103b and the second insulating barrier 103c and at least one second through hole, in the first through hole and the second through hole, form the first filler plug 111a of insulation and the second filler plug 111b of insulation, in the first filler plug 111a of insulation and the second filler plug 111b of insulation, form the first filler plug 112a of conduction and the second filler plug 112b of conduction, be layered in the first discrete electrode pad 102a on the first insulating barrier 103b, middle pad 102c, the second electrode pad 102b, be layered in the first discrete power pad 104a on the second insulating barrier 103c, second source pad 104b.
The first electrode pad 102a and the first power pad 104a form electrical connection by the first filler plug 112a of conduction; The second electrode pad 102b and second source pad 104b form electrical connection by the second filler plug 112b of conduction.
The first through hole can have one or more, and the second through hole can have one or more.
In some embodiments, through hole insulation supports that substrate has heat conducting disk, and in other embodiments, through hole insulation supports that substrate does not have heat conducting disk.
Fig. 2 a to Fig. 2 c shows the sectional view of an embodiment of the part manufacturing process of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.
First step, epitaxial semiconductor film comprises the Second Type limiting layer, luminescent layer, the first kind limiting layer that are formed on successively in growth substrates 120.Epitaxial semiconductor film is etched and forms multiple discrete elemental semiconductor epitaxial films, in order to simplify picture, only shows two elemental semiconductor epitaxial film 103a and 130b in Fig. 2 a to Fig. 2 c.
Form and support substrate and the pad being laminated thereon.What Fig. 2 a to 2c showed is that substrate 101a and the first electrode pad 102a and the middle pad 102c that are laminated thereon are supported in insulation.
Fig. 2 b shows second step, and the first kind limiting layer of elemental semiconductor epitaxial film 130a and 130b is bonded in respectively on the first electrode pad 102a and middle pad 102c, then peels off growth substrates 120.
(in Fig. 2 b, do not show the second electrode pad at unit chip and/or the second electrode pad, in Fig. 2 d, show) upper stacked passivation layer 140, pass through etching, passivation layer 140 is respectively at the first electrode pad 102a, elemental semiconductor epitaxial film 130a, middle pad 102c, on the preposition of the top of elemental semiconductor epitaxial film 130b, form the window 150a of reservation shape, 150b, 150c, 150d, make part the first electrode pad 102a, elemental semiconductor epitaxial film 130a, middle pad 102c, elemental semiconductor epitaxial film 130b is respectively at window 150a, 150b, 150c, in 150d, expose.
Attention: the shape and size of window 150a and 150c can be different, also can be identical.The shape and size of window 150b and 150d can be different, also can be identical.
Fig. 2 c shows third step, connecting electrode 160a in the middle of forming first in the part of the exposure of the elemental semiconductor epitaxial film 130a in window 150b, connecting electrode 160b in the middle of forming second in the part of the exposure on the middle pad 102c in window 150c, the middle p-n-connecting electrode 160c simultaneously forming is connected the first middle connecting electrode 160a with connecting electrode 160b in the middle of second.The second electrode 170 is formed on the elemental semiconductor epitaxial film 130b of the exposure in window 150d.
In chip package process, the gold thread 180a being connected with the positive and negative electrode of extraneous power supply respectively and 180b will be electrically connected with part and second electrode 170 of the exposure of the first electrode pad 102a in window 150a respectively.
Fig. 2 d shows the sectional view of an embodiment of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.This embodiment comprises, insulation support substrate 101a; The the first discrete electrode pad 102a being laminated thereon, middle pad 102c and the second electrode pad 102b; Be bonded in respectively elemental semiconductor epitaxial film 130a and 130b on the first electrode pad 102a and middle pad 102c; In the middle of connecting electrode 160a and second, connecting electrode 160b is respectively formed in the part of exposure of the middle pad 102c in the part of exposure of elemental semiconductor epitaxial film 130a and in window 150c in the middle of first; Middle p-n-connecting electrode 160c is connecting electrode 160b electrical connection in the middle of the first middle connecting electrode 160a and second; In the middle of connecting electrode 161a and second, connecting electrode 161b is respectively formed in the part of exposure of elemental semiconductor epitaxial film 130b and in the part of the exposure of the second electrode pad 102b in the middle of first; Middle p-n-connecting electrode 161c is connecting electrode 161b electrical connection in the middle of the first middle connecting electrode 161a and second.
In chip package process, the gold thread 180a being connected with the positive and negative electrode of extraneous power supply respectively and 180b will be electrically connected with the part of exposure of the first electrode pad 102a in window 150a and the part of the exposure of the second electrode pad 102b respectively.
Fig. 2 e shows the sectional view of the different embodiments of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.It is basic identical that the embodiment that Fig. 2 e shows and Fig. 2 d show, difference is: the support substrate of the embodiment in Fig. 2 e is conductive support substrate 101b, and insulating barrier 103a is layered on conductive support substrate 101b.The first electrode pad 102a, middle pad 102c and the second electrode pad 102b are layered on insulating barrier 103a.
Fig. 3 a, Fig. 3 b show the sectional view of an embodiment of the part manufacturing process of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.
The technique that Fig. 3 a shows is from growth substrates is stripped from, stacked passivation layer 140 on unit chip, pass through etching, passivation layer 140 is respectively at the first electrode pad 102a, elemental semiconductor epitaxial film 130a, middle pad 102c, elemental semiconductor epitaxial film 130b, on the preposition of the top of the second electrode pad 102b, form respectively the window 150a of reservation shape, 150b, 150c, 150d, 150e, make the first electrode pad 102a, elemental semiconductor epitaxial film 130a, middle pad 102c, elemental semiconductor epitaxial film 130b, a part of the second electrode pad 102b is respectively at window 150a, 150b, 150c, 150d, in 150e, expose.
Attention: the shape and size of window 150a and 150c and 150e can be different, also can be identical.The shape and size of window 150b and 150d can be different, also can be identical.
Fig. 3 b shows next step, connecting electrode 160a in the middle of forming first on the elemental semiconductor epitaxial film 130a of the exposure in window 150b, connecting electrode 160b in the middle of forming second on the middle pad 102c of the exposure in window 150c, the middle p-n-connecting electrode 160c simultaneously forming is connected the first middle connecting electrode 160a with connecting electrode 160b in the middle of second.The first connecting electrode 161a and the second connecting electrode 161b are respectively formed in the part of exposure of elemental semiconductor epitaxial film 130b and the second electrode pad 102b; P-n-connecting electrode 161c is the first connecting electrode 161a and the second connecting electrode 161b electrical connection.
The first electrode pad 102a and the second electrode pad 102b are insulated and are supported the first and second filler plug 110a and the 110b of the conduction in substrate 101c to be electrically connected with the first power pad 104a and second source pad 104b by through hole respectively.
Attention: in chip package process, have two kinds of methods to be connected with extraneous power supply, (1) first power pad 104a will be connected with two electrodes of extraneous power supply respectively with second source pad 104b; (2) by beating gold thread at the first electrode pad 102a and the second electrode pad 102b.
Fig. 4 a and Fig. 4 b show the sectional view of an embodiment of the part manufacturing process of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.The embodiment of the part manufacturing process that Fig. 4 a and Fig. 4 b show and Fig. 3 a and Fig. 3 b are basic identical, different, and the embodiment of Fig. 4 a and Fig. 4 b adopts through hole conductive support substrate 101d to replace the through hole insulation that Fig. 3 a and Fig. 3 b adopt to support substrate 101c.Therefore, in the time preparing to support substrate, first stacked the first insulating barrier 103b of difference and the second insulating barrier 103c on the first and second surfaces of conductive substrates 101d, pass conductive support substrate 101d and the first insulating barrier 103b and the second insulating barrier 103c and form at least one first through hole and at least one second through hole, and the first filler plug 111a that formation is insulated in the first through hole and the second through hole respectively and the second filler plug 111b of insulation, in the first filler plug 111a of insulation and the second filler plug 111b of insulation, form again through hole, and the first filler plug 112a that formation is conducted electricity in through hole and the second filler plug 112b of conduction.On the first insulating barrier 103b, form respectively the first electrode pad 102a, the second electrode pad 102b, middle pad 102c; On the second insulating barrier 103c, forming respectively the first power pad 104a and second source pad 104b, make the first electrode pad 102a and the first power pad 104a by the first filler plug 112a electrical connection of conduction, the second electrode pad 102b and second source pad 104b are by the second filler plug 112b electrical connection of conduction.
Fig. 5 a, Fig. 5 b, Fig. 5 c show respectively the equivalent circuit diagram of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.
Fig. 5 a shows the equivalent circuit diagram of an embodiment of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.
There is the unit chip 501,502,503 of at least two without the LED high pressure chip of the vertical stratification of metal electrode and form and be electrically connected in series, therefore, form the LED high voltage direct current chip without the vertical stratification of metal electrode.Dotted line in figure represents the unit chip of multiple units in series.
Attention: two or more than forming high voltage direct current chip after the unit chip series connection of two.
Fig. 5 b shows the equivalent circuit diagram of an embodiment of the high-voltage alternating chip of the Opposite direction connection formula of the LED high pressure chip of the vertical stratification without metal electrode of the present invention.
At least two unit chips 504,505 form and are electrically connected in series, and at least two unit chips 506,507 form and are electrically connected in series.The unit chip Opposite direction connection of two string series connection, forms the LED high-voltage alternating chip without the vertical stratification of metal electrode.Dotted line in figure represents the unit chip of multiple series connection.
Attention: the unit chip Opposite direction connection of at least two, forms high-voltage alternating chip.
Fig. 5 c shows the equivalent circuit diagram of an embodiment of the LED high-voltage alternating chip of the vertical stratification without metal electrode of the present invention.
Multiple unit chip 510,511,512,513,514,515 forms rectifying bridge type and connects.Between unit chip 514 and 515, can there is multiple unit chip, the dotted line in figure represents the unit xp of multiple series connection.Unit chip 510,511 and 514 is in node 520 places electrical connection.Unit chip 512,513 and 515 is in node 521 places electrical connection.
Finally it should be noted that: above embodiment only, in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to aforementioned embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned embodiment is modified, or part technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the spirit and scope of the each embodiment technical scheme of the present invention.
Claims (10)
1. without a LED high pressure chip for the vertical stratification of metal electrode, comprising:
-support substrate;
The pad of-discrete conduction; Described pad comprises, first electrode pad, pad in the middle of at least one, second electrode pad; Described the first electrode pad, described the second electrode pad and described middle pad are formed on described support substrate; Described the first electrode pad, described the second electrode pad and described middle pad and described support substrate electric insulation;
-at least two discrete elemental semiconductor epitaxial films: described elemental semiconductor epitaxial film comprises: first kind limiting layer, active layer and Second Type limiting layer; The described first kind limiting layer of described elemental semiconductor epitaxial film be bonded in respectively on the precalculated position of described the first electrode pad and middle pad and make described the first electrode pad and described in the middle of the part of pad expose; On described the second electrode pad, there is no elemental semiconductor epitaxial film described in bonding;
-each described pad and bonding described elemental semiconductor epitaxial film forming unit chip thereon;
-passivation layer: described passivation layer is layered on the surface and side of each described unit chip and described the second electrode pad; Described passivation layer has the window of reservation shape above the preposition of the Second Type limiting layer of described elemental semiconductor epitaxial film, and a part for described Second Type limiting layer exposes in described window; Described passivation layer has respectively the window of reservation shape above the preposition of the part of the exposure of described the first electrode pad and described middle pad, and a part for a part for described the first electrode pad and described middle pad exposes in described window; Described passivation layer has the window of reservation shape above the preposition of described the second electrode pad, and a part for described the second electrode pad exposes in described window;
-at least one transparent middle connecting electrode: described transparent middle connecting electrode comprises the first transparent middle connecting electrode, the second transparent middle connecting electrode, transparent middle p-n-connecting electrode; Wherein, the described first middle connecting electrode, by the described window of described passivation layer above the described Second Type limiting layer of a described elemental semiconductor epitaxial film, is layered on described Second Type limiting layer; Described in the middle of second connecting electrode by described passivation layer in the middle of a stacked described elemental semiconductor epitaxial film on it described pad above described window, be layered in described in the middle of on pad; In the middle of described, p-n-connecting electrode couples together the first middle connecting electrode described at least one and the second middle connecting electrode described at least one;
-mono-transparent connecting electrode: described transparent connecting electrode comprises the first transparent connecting electrode, the second transparent connecting electrode, transparent p-n-connecting electrode; Wherein, described the first connecting electrode, by the described window of described passivation layer above the described Second Type limiting layer of a described elemental semiconductor epitaxial film, is layered on described Second Type limiting layer; Described the second connecting electrode, by the described window of described passivation layer above described the second electrode pad, is layered on described the second electrode pad; Described p-n-connecting electrode couples together described the first connecting electrode and described the second connecting electrode.
2. according to the LED high pressure chip of the vertical stratification without metal electrode of claim 1, it is characterized in that, described support substrate is that substrate is supported in insulation; On the first surface of described insulation support substrate, form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad.
3. according to the LED high pressure chip of the vertical stratification without metal electrode of claim 1, it is characterized in that, described support substrate is conductive support substrate; On the first surface of described conductive support substrate, form a layer insulating, on described insulating barrier, form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad.
4. according to the LED high pressure chip of the vertical stratification without metal electrode of claim 1, it is characterized in that, described support substrate is that substrate is supported in through hole insulation; Described through hole insulation is supported to form at least one first through hole and second through hole in substrate, in described the first through hole and described the second through hole, form respectively the first filler plug of conduction and the second filler plug of conduction, on the first surface of described through hole insulation support substrate, form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad; On the second surface of described through hole insulation support substrate, form discrete the first power pad and second source pad mutually; Described the first power pad and described second source pad are supported described the first electrode pad on the first surface of substrate and described the second electrode pad to form by the first filler plug of described conduction and the second filler plug of described conduction and described through hole insulation to be respectively electrically connected.
5. according to the LED high pressure chip of the vertical stratification without metal electrode of claim 1, it is characterized in that, described support substrate is through hole conductive support substrate; On the first surface of described through hole conductive support substrate and second surface, form respectively the first insulating barrier and the second insulating barrier; In described through hole conductive support substrate and described the first insulating barrier and described the second insulating barrier, form at least one first through hole and at least one second through hole, in described first through hole and the second through hole, form respectively the first filler plug of insulation and the second filler plug of insulation, in the first filler plug of described insulation and the second filler plug of described insulation, form respectively the first filler plug of conduction and the second filler plug of conduction, the first filler plug of described conduction and the second filler plug of conduction and the mutual electric insulation of described through hole conductive support substrate; On described the first insulating barrier on the first surface of described through hole conductive support substrate, form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad; On described the second insulating barrier on the second surface of described through hole conductive support substrate, form mutually discrete the first power pad and second source pad, described the first power pad and second source pad are electrically connected with described the first electrode pad and described the second electrode pad formation on the first insulating barrier of described through hole conductive support substrate respectively by the first filler plug of described conduction and the second filler plug of described conduction.
6. without a LED high pressure chip for the vertical stratification of metal electrode, comprising:
-support substrate; Described support substrate comprises, insulation support substrate; With the conductive support substrate of insulating barrier;
The pad of-discrete conduction; Described pad comprises, first electrode pad, pad in the middle of at least one; Described the first electrode pad and described middle pad are formed on described support substrate; Described the first electrode pad and described middle pad and described support substrate electric insulation;
-at least two discrete elemental semiconductor epitaxial films: described elemental semiconductor epitaxial film comprises: first kind limiting layer, active layer and Second Type limiting layer; The described first kind limiting layer of described elemental semiconductor epitaxial film be bonded in respectively on the precalculated position of described the first electrode pad and middle pad and make described the first electrode pad and described in the middle of the part of pad expose;
-each described pad and bonding described elemental semiconductor epitaxial film forming unit chip thereon;
-passivation layer: described passivation layer is layered on the surface and side of each described unit chip; Described passivation layer has the window of reservation shape above the preposition of the Second Type limiting layer of described elemental semiconductor epitaxial film, and a part for described Second Type limiting layer exposes in described window; Described passivation layer respectively described the first electrode pad and described in the middle of there is the window of reservation shape above the preposition of part of exposure of pad, described the first electrode pad and described in the middle of the part of pad in described window, expose respectively;
-at least one transparent middle connecting electrode: described transparent middle connecting electrode comprises the first transparent middle connecting electrode, the second transparent middle connecting electrode, transparent middle p-n-connecting electrode; Wherein, the described first middle connecting electrode, by the described window of described passivation layer above the described Second Type limiting layer of a described elemental semiconductor epitaxial film, is layered on described Second Type limiting layer; Described in the middle of second connecting electrode by described passivation layer on another its in the middle of stacked described elemental semiconductor epitaxial film described pad above described window, be layered in described in the middle of on pad; In the middle of described, p-n-connecting electrode couples together the first middle connecting electrode described at least one and the second middle connecting electrode described at least one;
-the second transparent electrode: described the second electrode, by the described window of described passivation layer above the described Second Type limiting layer of a described elemental semiconductor epitaxial film, is layered on described Second Type limiting layer.
7. according to the LED high pressure chip of the vertical stratification without metal electrode of claim 1 or claim 6, it is characterized in that, in the middle of described, p-n-connecting electrode is to select from one group of connected mode the first middle connecting electrode described at least one with the connected mode that described at least one, the second middle connecting electrode couples together, this group connected mode comprises: in the middle of (1), p-n-connecting electrode forms the described first middle connecting electrode on the described Second Type limiting layer of a described elemental semiconductor epitaxial film and the described second middle connecting electrode on the middle pad of adjacent described unit chip the electrical connection of series connection form, (2) in the middle of, p-n-connecting electrode forms electrical connection the described first middle connecting electrode on the described Second Type limiting layer of a described elemental semiconductor epitaxial film and two the described second middle connecting electrodes on the described middle pad of two other adjacent described unit chip, (3) in the middle of, p-n-connecting electrode forms electrical connection two the described first middle connecting electrodes on the described second middle connecting electrode on the described middle pad of a described unit chip and the described Second Type limiting layer at two other adjacent described elemental semiconductor epitaxial film.
8. according to the LED high pressure chip of the vertical stratification without metal electrode of claim 1 or claim 6, it is characterized in that, whole described unit chip connects with series system, forms the LED high voltage direct current chip without the vertical stratification of metal electrode.
9. according to the LED high pressure chip of the vertical stratification without metal electrode of claim 1 or claim 6, it is characterized in that, whole described unit chip, with the electrical connection of rectifier bridge form, forms the LED high-voltage alternating chip without the vertical stratification of metal electrode.
10. according to the LED high pressure chip of the vertical stratification without metal electrode of claim 1 or claim 6, it is characterized in that, whole described unit chip, with series connection and the electrical connection of reverse parallel connection form, forms the LED high-voltage alternating chip without the vertical stratification of metal electrode.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210452506.7A CN103811650A (en) | 2012-11-13 | 2012-11-13 | Vertical structure LED high-voltage chip free of metal electrodes |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104167485A (en) * | 2014-08-21 | 2014-11-26 | 中国科学院半导体研究所 | Self-supported LED array light source structure |
| CN104953012A (en) * | 2015-06-29 | 2015-09-30 | 广东德力光电有限公司 | AC-LED (alternating current-light emitting diode) chip and application thereof |
| CN105226075A (en) * | 2015-10-22 | 2016-01-06 | 江苏新广联半导体有限公司 | The manufacture method of high-voltage LED transparency conducting layer |
-
2012
- 2012-11-13 CN CN201210452506.7A patent/CN103811650A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104167485A (en) * | 2014-08-21 | 2014-11-26 | 中国科学院半导体研究所 | Self-supported LED array light source structure |
| CN104953012A (en) * | 2015-06-29 | 2015-09-30 | 广东德力光电有限公司 | AC-LED (alternating current-light emitting diode) chip and application thereof |
| CN105226075A (en) * | 2015-10-22 | 2016-01-06 | 江苏新广联半导体有限公司 | The manufacture method of high-voltage LED transparency conducting layer |
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