CN202930431U - Vertical structure LED high voltage chip without metal electrodes - Google Patents
Vertical structure LED high voltage chip without metal electrodes Download PDFInfo
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- CN202930431U CN202930431U CN2012205953147U CN201220595314U CN202930431U CN 202930431 U CN202930431 U CN 202930431U CN 2012205953147 U CN2012205953147 U CN 2012205953147U CN 201220595314 U CN201220595314 U CN 201220595314U CN 202930431 U CN202930431 U CN 202930431U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
Abstract
The utility model discloses a vertical structure LED high voltage chip without metal electrodes, comprising support substrates and at least two unit semiconductor epitaxial films, wherein the support substrates comprise an insulation support substrate, a conductive support substrate, a through hole insulation support substrate and a through hole conductive support substrate. The unit semiconductor epitaxial films are bonded on the support substrates and are stripped from a growth substrate. Adjacent unit semiconductor epitaxial films are in electric connection through a transparent intermediate connection electrode. All unit chips are in series connection to form a vertical structure LED high voltage direct current chip without metal electrodes. All unit chips are in connection in a rectifier bridge mode or in a mixed mode of series and parallel connection to form a vertical structure LED high voltage alternating current chip without metal electrodes.
Description
Technical field
The utility model relates to without the LED high voltage direct current of the vertical stratification of metal electrode or exchanges chip.
Background technology
Patent application 2008101694391 discloses the LED high voltage direct current chip of positive assembling structure.One of method of fast reducing lighting cost is to adopt high current density to drive, and still, the chip of positive assembling structure can face the problem of poor heat radiation when high current density drives.In order to solve heat dissipation problem, patent 2010105840892 discloses the LED high voltage direct current chip of vertical stratification.But the price of gold and other metals improves increasingly, and the cost of metal electrode also improves thereupon.In addition, the LED communication day by day develops, need to be than the LED chip of high switching speed.
In order to make LED enter faster huge general illumination field, still need further to improve positive assembling structure and vertical stratification LED high voltage direct current chip performance and reduce production costs.The little improvement of product structure and any point on production technology of the LED high voltage direct current chip of positive assembling structure and vertical stratification and the raising of the chip performance that brings and the reduction of production cost, the speed that LED enters general illumination market is accelerated in the capital, produces huge economic benefit.
Therefore, need a kind ofly to solve heat dissipation problem, can adopt large driven current density, production cost is lower, can reduce LED light fixture cost, have the LED high voltage direct current of high switching speed or exchange chip.
The utility model content
The purpose of this utility model is to provide and a kind ofly solves heat dissipation problem, large driven current density, reduces production costs, reduces the LED high pressure chip without the vertical stratification of metal electrode of LED light fixture cost, high switching speed.Preferably, provide a kind of LED high pressure chip without the vertical stratification of metal electrode that need not to beat gold thread.
In context of the present utility model, LED high pressure chip without the vertical stratification of metal electrode comprises, LED high voltage direct current chip without the vertical stratification of metal electrode, LED high-voltage alternating chip without the vertical stratification of metal electrode, need not to beat the LED high voltage direct current chip without the vertical stratification of metal electrode of gold thread, need not to beat the LED high-voltage alternating chip without the vertical stratification of metal electrode of gold thread.
An embodiment without the LED high pressure chip of the vertical stratification of metal electrode comprises:
(1) support substrate;
(2) pad of discrete conduction; Pad comprises, first electrode pad, pad in the middle of at least one, second electrode pad; The first electrode pad, the second electrode pad and middle pad are formed on to be supported on substrate; The first electrode pad, the second electrode pad and middle pad and support substrate electric insulation;
(3) at least two discrete elemental semiconductor epitaxial films: the elemental semiconductor epitaxial film comprises: first kind limiting layer, active layer and Second Type limiting layer; The first kind limiting layer of elemental semiconductor epitaxial film is bonded in respectively on the precalculated position of the first electrode pad and middle pad and makes the part of the first electrode pad and middle pad expose; There is no bonding elemental semiconductor epitaxial film on the second electrode pad;
(4) quantity of pad is Duoed one than the quantity of elemental semiconductor epitaxial film, on the second electrode pad, there is no bonding elemental semiconductor epitaxial film.
(5) each pad and bonding elemental semiconductor epitaxial film Component units chip thereon;
(6) passivation layer: passivation layer is layered on the surface and side of each unit chip and the second electrode pad; Passivation layer has the window of reservation shape above the preposition of the Second Type limiting layer of elemental semiconductor epitaxial film, the part of Second Type limiting layer exposes in window; Passivation layer has respectively the window of reservation shape above the preposition of the part of the exposure of the first electrode pad and middle pad, the part of the first electrode pad and the part of middle pad expose in window; Passivation layer has the window of reservation shape above the preposition of the second electrode pad, the part of the second electrode pad exposes in window;
(7) at least one transparent middle connecting electrode: transparent middle connecting electrode comprises the first transparent middle connecting electrode, the second transparent middle connecting electrode, transparent middle p-n-connecting electrode; Wherein, the first middle connecting electrode is layered on the Second Type limiting layer by the window of passivation layer above the Second Type limiting layer of an elemental semiconductor epitaxial film; Connecting electrode by the window of passivation layer above middle the pad of a stacked elemental semiconductor epitaxial film on it, is layered on the pad of centre in the middle of second; Middle p-n-connecting electrode couples together at least one first middle connecting electrode and at least one second middle connecting electrode;
(8) transparent connecting electrodes: transparent connecting electrode comprises the first transparent connecting electrode, the second transparent connecting electrode, transparent p-n-connecting electrode; Wherein, the first connecting electrode is layered on the Second Type limiting layer by the window of passivation layer above the Second Type limiting layer of an elemental semiconductor epitaxial film; The second connecting electrode is layered on the second electrode pad by the window of passivation layer above the second electrode pad; The p-n-connecting electrode couples together the first connecting electrode and the second connecting electrode.
The support substrate comprises: substrate is supported in (1) insulation; Form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad on the first surface of insulation support substrate.(2) conductive support substrate; Form a layer insulating on the first surface of conductive support substrate, form discrete first electrode pad mutually on insulating barrier, pad in the middle of at least one, second electrode pad.(3) substrate is supported in the through hole insulation; The through hole insulation supports to form in substrate at least one first through hole and second through hole, form respectively the first filler plug of conduction and the second filler plug of conduction in the first through hole and the second through hole, form discrete first electrode pad mutually on the first surface of through hole insulation support substrate, pad in the middle of at least one, second electrode pad; Form discrete the first power pad and second source pad mutually on the second surface of through hole insulation support substrate; The first power pad and second source pad the first filler plug by conduction and the second filler plug of conduction and through hole insulation respectively support the first electrode pad and the formation of the second electrode pad on the first surface of substrate to be electrically connected to.(4) through hole conductive support substrate; Form respectively the first insulating barrier and the second insulating barrier on the first surface of through hole conductive support substrate and second surface; Form at least one first through hole and at least one second through hole in through hole conductive support substrate and the first insulating barrier and the second insulating barrier, form respectively the first filler plug of insulation and the second filler plug of insulation in first through hole and the second through hole, form respectively the first filler plug of conduction and the second filler plug of conduction, the first filler plug of conduction and the second filler plug of conduction and the mutual electric insulation of through hole conductive support substrate in the second filler plug of first filler plug of insulating and insulation; Form discrete first electrode pad mutually on the first insulating barrier on the first surface of through hole conductive support substrate, pad in the middle of at least one, second electrode pad; Form discrete the first power pad and second source pad mutually on the second insulating barrier on the second surface of through hole conductive support substrate, the first power pad and second source pad by conduction the first filler plug and the second filler plug of conduction respectively with the first surface of through hole conductive support substrate on the first electrode pad and the second electrode pad form and be electrically connected to.
Another embodiment without the LED high pressure chip of the vertical stratification of metal electrode comprises:
(1) support substrate; The support substrate comprises, insulation support substrate; Conductive support substrate with insulating barrier;
(2) pad of discrete conduction; Pad comprises, first electrode pad, pad in the middle of at least one; The first electrode pad and middle pad are formed on to be supported on substrate; The first electrode pad and middle pad and support substrate electric insulation;
(3) at least two discrete elemental semiconductor epitaxial films: the elemental semiconductor epitaxial film comprises: first kind limiting layer, active layer and Second Type limiting layer; The described first kind limiting layer of elemental semiconductor epitaxial film is bonded in respectively on the precalculated position of the first electrode pad and middle pad and makes the part of the first electrode pad and middle pad expose;
(4) quantity of pad is identical with the quantity of elemental semiconductor epitaxial film, elemental semiconductor epitaxial film of the surface bond of each pad.
(5) each elemental semiconductor epitaxial film and its bonding pad thereon forms the unit chip;
(6) passivation layer: passivation layer is layered on the surface and side of each unit chip; Passivation layer has the window of reservation shape above the preposition of the Second Type limiting layer of elemental semiconductor epitaxial film, the part of Second Type limiting layer exposes in window; Passivation layer has respectively the window of reservation shape above the preposition of the part of the exposure of the first electrode pad and middle pad, the part of the first electrode pad and middle pad exposes in window respectively;
(7) at least one transparent middle connecting electrode: transparent middle connecting electrode comprises the first transparent middle connecting electrode, the second transparent middle connecting electrode, transparent middle p-n-connecting electrode; Wherein, the first middle connecting electrode is layered on the Second Type limiting layer by the window of passivation layer above the Second Type limiting layer of an elemental semiconductor epitaxial film; Connecting electrode by the window of passivation layer above middle the pad of a stacked elemental semiconductor epitaxial film on it, is layered on the pad of centre in the middle of second; Middle p-n-connecting electrode couples together at least one first middle connecting electrode and at least one second middle connecting electrode;
(8) the second transparent electrode: the second electrode is layered on the Second Type limiting layer by the window of passivation layer above the Second Type limiting layer of an elemental semiconductor epitaxial film.
The LED high pressure chip of the vertical stratification without metal electrode of the present utility model, middle p-n-connecting electrode is the connected mode that connecting electrode in the middle of connecting electrode and second in the middle of first couples together to select from one group of connected mode, this group connected mode comprises:
in the middle of (1) first in the middle of connecting electrode and second connecting electrode respectively by the window of passivation layer above the middle pad of the exposure of the window above the Second Type limiting layer of an elemental semiconductor epitaxial film and adjacent unit chip, be layered on the middle pad of exposure of the Second Type limiting layer of an elemental semiconductor epitaxial film and adjacent unit chip, middle p-n-connecting electrode forms the first middle connecting electrode and the second middle connecting electrode on the middle pad of adjacent unit chip the electrical connection of series connection form, all the unit chip connects with series system, formation is without the LED high voltage direct current chip of the vertical stratification of metal electrode.
(2) in the middle of, the p-n-connecting electrode is electrically connected to node of formation to connecting electrode in the middle of first on the Second Type limiting layer of an elemental semiconductor epitaxial film and two second middle connecting electrodes formation on the middle pad of two other adjacent unit chip, middle p-n-connecting electrode is electrically connected to another node of formation to connecting electrode in the middle of second on the middle pad of a unit chip and two first middle connecting electrodes formation on the Second Type limiting layer of two other adjacent elemental semiconductor epitaxial film, namely, rectifier bridge comprises at least two nodes, at Nodes, connecting electrode the limiting layer of the same type of two elemental semiconductor epitaxial films be connected the dissimilar limiting layer of elemental semiconductor epitaxial film and connect, all the unit chip is electrically connected to the rectifier bridge form, formation is without the LED high-voltage alternating chip of the vertical stratification of metal electrode.
The unit chip of (3) two groups of equal numbers is electrically connected to the series connection form respectively, the unit chip of two groups of series connection is electrically connected to the reverse parallel connection form, namely, connecting electrode connects whole unit chip in the mode that series and parallel connections mixes, form the LED high-voltage alternating chip without the vertical stratification of metal electrode.
Transparent middle connecting electrode, transparent connecting electrode, the second transparent electrode have single-layer electrodes structure or multi-layer electrode structure, and every layer of electrode is to select from one group of electrode, and this group electrode comprises, the metal oxide of conduction, thin metal film.
An embodiment: transparent middle connecting electrode, transparent connecting electrode and/or the second transparent electrode have the single-layer electrodes structure, and this monolayer material is thin metal film, and its thickness is in nanometer scale, and is less 10 times than the thickness of metal electrode, reduces production costs.
An embodiment: middle connecting electrode, connecting electrode, the second electrode have the structure of individual layer, and this monolayer material is the metal oxide of transparent conduction, as ITO, etc.
An embodiment: middle connecting electrode, connecting electrode, the second electrode have two-layer structure, and this materials at two layers is: one deck is the metal oxide (as ITO) of transparent conduction, and another layer is thin metal film etc.
Preferred embodiment: middle connecting electrode, connecting electrode, the second electrode have identical structure.
Insulation supports that substrate comprises, aluminium oxide ceramics is supported substrate, and aluminium nitride ceramics is supported substrate, etc.Conductive support substrate comprises, tungsten copper support substrate, etc.The through hole insulation supports that substrate comprises, the low-temperature oxidation aluminium pottery that forms through hole supports substrate or aluminium nitride ceramics to support substrate, and the high temperature alumina pottery that forms through hole supports substrate or aluminium nitride ceramics to support substrate.The through hole conductive support substrate comprises, forms the tungsten copper support substrate of through hole, etc.
Therefore, have high heat-sinking capability without the LED high pressure chip of the vertical stratification of metal electrode, the density of high drive current, low production cost reduces the cost of LED light fixture.
Following description is applicable to all embodiments of the present utility model.
(1) in figure, the ratio of each several part does not represent the ratio of actual products.
(2) in Fig. 2 to Fig. 4, the LED high pressure chip without the vertical stratification of metal electrode includes only two unit chips, and still, the LED high pressure chip of the vertical stratification without metal electrode of the present utility model can comprise more than two unit chips.
(3) material of elemental semiconductor epitaxial film is to select from one group of material, and this group material comprises: (a) gallium nitride-based material; Described gallium nitride-based material comprises, GaN, AlGaN, GaInN, AlGaInN; (b) gallium phosphide sill; Described gallium phosphide sill comprises, GaP, AlGaP, GaInP, AlGaInP; (c) nitrogen phosphorus gallium sill; Described nitrogen phosphorus gallium material comprises, GaNP, AlGaNP, GaInNP, AlGaInNP; (d) the Zinc oxide-base material, comprise, ZnO.
(4) material of passivation layer and insulating barrier is to select from one group of material, this group material comprises, silica gel (silicone), resin (epoxy), silica (SiO2), silicon nitride, silicon-on-glass (SOG), polyimides (polyimide), glass, polymethyl methacrylate (polymethylmethacrylate), acrylic acid (acrylic), etc.
(5) in the middle of, connecting electrode, connecting electrode and/or the second electrode have the single or multiple lift structure: the material of every one deck is to select from one group of material, and this group material comprises, conductive oxide material, metal material, nano silver wire, carbon nano-tube, Graphene; Described conductive oxide material comprises: ITO (tin indium oxide), IZO (indium zinc oxide), CTO (cadmium tin), ZnO:Al, AuAlO2, LaCuOS, CuGaO, SrCuO2, ZnGa2O4, SnO2:Sb, Ga2O3:Sn, In2O3:Zn, NiO, MnO, CuO, SnO, GaO, FTO; Described metal material comprises: Al, Ag, Au, Ni/Au, Ni/Pt, Ni/Pd, Ni/Co, Pd/Au, Pt/Au, Ti/Au, Cr/Au, Sn/Au, Zr, Hf, V, Nb.
In the middle of (6) first, connecting electrode and the second middle connecting electrode be not on same unit chip.
(7) support that substrate is to support to select substrate from one group, this group supports that substrate comprises: substrate is supported in insulation, conductive support substrate, and substrate, through hole conductive support substrate are supported in the through hole insulation; Wherein, (a) substrate is supported in insulation; Form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad on the first surface of insulation support substrate.(b) conductive support substrate; Form a layer insulating on the first surface of conductive support substrate, form discrete first electrode pad mutually on insulating barrier, pad in the middle of at least one, second electrode pad.(c) substrate is supported in the through hole insulation; The through hole insulation supports to form in substrate at least one first through hole and second through hole, form respectively the first filler plug of conduction and the second filler plug of conduction in the first through hole and the second through hole, form discrete first electrode pad mutually on the first surface of through hole insulation support substrate, pad in the middle of at least one, second electrode pad; Form discrete the first power pad and second source pad mutually on the second surface of through hole insulation support substrate; The first power pad and second source pad the first filler plug by conduction and the second filler plug of conduction and through hole insulation respectively support the first electrode pad and the formation of the second electrode pad on the first surface of substrate to be electrically connected to.(d) through hole conductive support substrate; Form respectively the first insulating barrier and the second insulating barrier on the first surface of through hole conductive support substrate and second surface; Form at least one first through hole and at least one second through hole in through hole conductive support substrate and the first insulating barrier and the second insulating barrier, form respectively the first filler plug of insulation and the second filler plug of insulation in first through hole and the second through hole, form respectively the first filler plug of conduction and the second filler plug of conduction, the first filler plug of conduction and the second filler plug of conduction and the mutual electric insulation of through hole conductive support substrate in the second filler plug of first filler plug of insulating and insulation; Form discrete first electrode pad mutually on the first insulating barrier on the first surface of through hole conductive support substrate, pad in the middle of at least one, second electrode pad; Form discrete the first power pad and second source pad mutually on the second insulating barrier on the second surface of through hole conductive support substrate, the first power pad and second source pad by conduction the first filler plug and the second filler plug of conduction respectively with the first surface of through hole conductive support substrate on the first electrode pad and the second electrode pad form and be electrically connected to.
(8) in the middle of, the p-n-connecting electrode couples together connecting electrode in the middle of the first middle connecting electrode and second, connected mode comprises: (a) two adjacent unit chips are formed the electrical connection of series connection form, namely, the second connecting electrode of an elemental semiconductor epitaxial film is connected with the middle pad of an adjacent unit chip, makes two adjacent elemental semiconductor epitaxial films form the electrical connection of series connection forms; (b) the second centre connecting electrode of connecting electrode in the middle of first on an elemental semiconductor epitaxial film with middle the pad of adjacent two unit chips is connected, makes the electrical connection of a node of three adjacent elemental semiconductor epitaxial films formation bridge circuits; (c) the middle pad of a unit chip second in the middle of in the middle of first on connecting electrode and adjacent two elemental semiconductor epitaxial films connecting electrode be connected, make the electrical connection of another node of three adjacent elemental semiconductor epitaxial films formation bridge circuits; (d) the unit chip of two unit chips or two string series connection is formed the electrical connection of reverse parallel connection form, namely, the second middle connecting electrode of a unit chip is connected with the first electrode pad of another unit chip, the first middle connecting electrode of a unit chip is connected with the second electrode pad.
(9) for a chip, the first electrode pad only has one, will be connected with an electrode of extraneous power supply; The second electrode pad only has one, will be connected with another electrode of extraneous power supply; Middle pad has at least one.Some embodiment has the second electrode pad, and some embodiment does not have the second electrode pad, but the second electrode (the second electrode is connected with extraneous power supply by beating gold thread) is arranged.The first electrode pad be connected electrode pad and comprise with the connected mode of extraneous power supply respectively: (a) by beat gold thread directly the first electrode pad be connected electrode pad and be connected with the positive and negative electrode of extraneous power supply respectively, (b) the first and second filler plugs by conduction of the first electrode pad and the second electrode pad are connected with the second source pad with the first power pad respectively, the first power pad is connected with the positive and negative electrode of extraneous power supply with the second source pad and is connected.
(10) growth substrates comprises, Sapphire Substrate, silicon carbide substrates, gallium nitride substrate, glass substrate, and graphite substrate, gallium arsenide substrate, silicon substrate, etc.
Description of drawings
Fig. 1 a to Fig. 1 e shows respectively the sectional view of some embodiments of support substrate of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.
Fig. 2 a to Fig. 2 c shows the sectional view of an embodiment of part manufacturing process of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.
Fig. 2 d, Fig. 2 e show respectively the sectional view of different embodiments of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.
Fig. 3 a, Fig. 3 b show the sectional view of an embodiment of part manufacturing process of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.
Fig. 4 a, Fig. 4 b show the sectional view of an embodiment of part manufacturing process of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.
Fig. 5 a, Fig. 5 b, Fig. 5 c show respectively the high voltage direct current and the equivalent circuit diagram that exchanges chip of inverted structure of the present utility model.
The implication of the numerical chracter representative in figure is as follows:
101a represents insulation support substrate;
101b represents conductive support substrate;
101c represents through hole insulation support substrate;
101d represents the through hole conductive support substrate;
102a, 102b, 102c presentation layer respectively are stacked in the first electrode pad, the second electrode pad, the middle pad of supporting on the substrate first surface;
The 103a presentation layer is stacked in the insulating barrier on the conductive support substrate first surface;
103b, 103c presentation layer respectively are stacked in the first insulating barrier and the second insulating barrier on through hole conductive support substrate first surface and second surface;
104a, 104b presentation layer respectively are stacked in through hole insulation and support the first power pad and second source pad on the second surface of substrate and through hole conductive support substrate; 104a, 104b will be connected with two electrodes of extraneous power supply respectively;
The 104c presentation layer is stacked in through hole insulation and supports heat conducting disk on the second surface of substrate and through hole conductive support substrate;
110a, 110b represent respectively to be formed on the through hole insulation and support the first filler plug of the conduction in substrate and the second filler plug of conduction;
111a, 111b represent respectively to be formed on the first through hole and the first filler plug of the insulation in the second through hole and the second filler plug of insulation in the through hole conductive support substrate;
112a, 112b represent respectively to be formed on the first filler plug of the conduction in the second filler plug 111a, the 111b of the first filler plug of insulation and insulation and the second filler plug of conduction;
120 expression growth substrates;
130a, 130b represent respectively to be formed on the elemental semiconductor epitaxial film on growth substrates;
140 expression passivation layers;
150a, 150b, 150c, 150d, 150e are illustrated respectively in the Second Type limiting layer of the first electrode pad of supporting on the substrate first surface, the Second Type limiting layer of elemental semiconductor epitaxial film, middle pad, adjacent elemental semiconductor epitaxial film, the window that forms of the second electrode pad top in passivation layer, in window, the Second Type limiting layer of the Second Type limiting layer of corresponding the first electrode pad, elemental semiconductor epitaxial film, middle pad, adjacent elemental semiconductor epitaxial film, the surface of the second electrode pad expose;
Connecting electrode, the second middle connecting electrode, middle p-n-connecting electrode in the middle of 160a, 160b, 160c represent respectively first; Be layered in connecting electrode 160a in the middle of first on the first kind limiting layer 130a of exposure of an elemental semiconductor epitaxial film, exposure lip-deep of middle pad that is layered in another adjacent unit chip connecting electrode 160b in the middle of second, the middle p-n-connecting electrode 160c that connecting electrode 160b in the middle of second is electrically connected to the first middle connecting electrode 160a formation;
161a, 161b, 161c represent respectively the first connecting electrode, the second connecting electrode, p-n-connecting electrode; The second connecting electrode is layered on the second electrode pad;
170 expression the second electrodes;
180a, 180b represent respectively the gold thread that is connected with extraneous power supply;
501,502,503 represent respectively to form a plurality of unit chip that is connected in series;
504 and 505 represent respectively to form a plurality of unit chip that is connected in series;
506 and 507 represent respectively to form a plurality of unit chip that is connected in series;
510,511,512,513,514,515 represent respectively to form a plurality of unit chip that rectifying bridge type connects;
520 and 521 represent respectively two nodes of rectifier bridge.
Embodiment
For the purpose, technical scheme and the advantage that make embodiment of the present utility model clearer, below in conjunction with the accompanying drawing in embodiment of the present utility model, technical scheme in embodiment of the present utility model is clearly and completely described, obviously, described embodiment is a part of embodiment of the present utility model, rather than whole embodiments.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all belong to the scope of the utility model protection.
Attention: below in all embodiments, although the LED high pressure chip without the vertical stratification of metal electrode of showing in figure includes only two unit chips, but the LED high pressure chip of the vertical stratification without metal electrode of the present utility model can comprise more than two unit chips.
Fig. 1 a to Fig. 1 e shows respectively the sectional view of different embodiments of support substrate of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.
Fig. 1 a shows insulation support substrate 101a, is layered in the first discrete electrode pad 102a, middle pad 102c on the first surface of supporting substrate 101a that insulate.
Fig. 1 b shows conductive support substrate 101b, is layered in the insulating barrier 103a on the first surface of conductive support substrate 101b, is layered in the first discrete electrode pad 102a on insulating barrier 103a, middle pad 102c.
Fig. 1 c shows through hole insulation support substrate 101c, be formed at least one first through hole and at least one second through hole wherein and be formed on the first through hole and the second through hole in the first filler plug of conduction and the second filler plug 110a and 110b of conduction, be layered in through hole insulation and support the first discrete electrode pad 102a, middle pad 102c, the second electrode pad 102b on the first surface of substrate 101c, be layered in the through hole insulation and support the first discrete power pad 104a, second source pad 104b, heat conducting disk 104c on the second surface of substrate 101c.
Attention: in Fig. 1 c, the first through hole comprises two through holes, and the second through hole comprises two through holes, and in order to dispel the heat, through hole can have a plurality of.
The first electrode pad 102a and the first power pad 104a form electrical connection by the first filler plug 110a of conduction; The second electrode pad 102b and second source pad 104b form electrical connection by the second filler plug 110b of conduction.
It is basic identical that the through hole insulation of Fig. 1 d displaying supports that substrate 101c and Fig. 1 c show, difference is there is no heat conducting disk on the second surface of through hole insulation support substrate 101c.
Fig. 1 e shows through hole conductive support substrate 101d, comprise, be respectively formed at the first insulating barrier 103b and the second insulating barrier 103c on its first and second surface, pass through hole conductive support substrate 101d, at least one first through hole of the first insulating barrier 103b and the second insulating barrier 103c and at least one second through hole, form the first filler plug 111a of insulation and the second filler plug 111b of insulation in the first through hole and the second through hole, form the first filler plug 112a of conduction and the second filler plug 112b of conduction in the second filler plug 111b of the first filler plug 111a that insulate and insulation, be layered in the first discrete electrode pad 102a on the first insulating barrier 103b, middle pad 102c, the second electrode pad 102b, be layered in the first discrete power pad 104a on the second insulating barrier 103c, second source pad 104b.
The first electrode pad 102a and the first power pad 104a form electrical connection by the first filler plug 112a of conduction; The second electrode pad 102b and second source pad 104b form electrical connection by the second filler plug 112b of conduction.
The first through hole can have one or more, and the second through hole can have one or more.
In some embodiments, the through hole insulation supports that substrate has heat conducting disk, and in other embodiments, the through hole insulation supports that substrate does not have heat conducting disk.
Fig. 2 a to Fig. 2 c shows the sectional view of an embodiment of part manufacturing process of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.
First step, epitaxial semiconductor film comprise Second Type limiting layer, luminescent layer, the first kind limiting layer that is formed on successively on growth substrates 120.Epitaxial semiconductor film is etched and forms a plurality of discrete elemental semiconductor epitaxial films, in order to simplify picture, only shows two elemental semiconductor epitaxial film 103a and 130b in Fig. 2 a to Fig. 2 c.
Form and support substrate and the pad that is laminated thereon.What Fig. 2 a to 2c showed is that substrate 101a and the first electrode pad 102a and the middle pad 102c that are laminated thereon are supported in insulation.
Fig. 2 b shows second step, and the first kind limiting layer of elemental semiconductor epitaxial film 130a and 130b is bonded in respectively on the first electrode pad 102a and middle pad 102c, then peels off growth substrates 120.
(do not show the second electrode pad in Fig. 2 b at unit chip and/or the second electrode pad, showed in Fig. 2 d) upper stacked passivation layer 140, pass through etching, passivation layer 140 is respectively at the first electrode pad 102a, elemental semiconductor epitaxial film 130a, middle pad 102c, form the window 150a of reservation shape on the preposition of the top of elemental semiconductor epitaxial film 130b, 150b, 150c, 150d, make part the first electrode pad 102a, elemental semiconductor epitaxial film 130a, middle pad 102c, elemental semiconductor epitaxial film 130b is respectively at window 150a, 150b, 150c, expose in 150d.
Attention: the shape and size of window 150a and 150c can be different, also can be identical.The shape and size of window 150b and 150d can be different, also can be identical.
Fig. 2 c shows third step, connecting electrode 160a in the middle of forming first on the part of the exposure of the elemental semiconductor epitaxial film 130a in window 150b, connecting electrode 160b in the middle of forming second on the part of the exposure on the middle pad 102c in window 150c, middle the p-n-connecting electrode 160c that forms simultaneously connecting electrode 160a in the middle of first be connected middle connecting electrode 160b connection.The second electrode 170 is formed on the elemental semiconductor epitaxial film 130b of the exposure in window 150d.
In chip package process, the gold thread 180a that is connected with the positive and negative electrode of extraneous power supply respectively and 180b will be respectively be electrically connected to part and second electrode 170 of exposure of the first electrode pad 102a in window 150a.
Fig. 2 d shows the sectional view of an embodiment of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.This embodiment comprises, insulation support substrate 101a; The the first discrete electrode pad 102a that is laminated thereon, middle pad 102c and the second electrode pad 102b; Be bonded in respectively elemental semiconductor epitaxial film 130a and 130b on the first electrode pad 102a and middle pad 102c; In the middle of first in the middle of connecting electrode 160a and second connecting electrode 160b be respectively formed on the part of exposure of elemental semiconductor epitaxial film 130a and on the part of the exposure of the middle pad 102c in window 150c; Middle p-n-connecting electrode 160c is electrically connected to connecting electrode 160b in the middle of the first middle connecting electrode 160a and second; In the middle of first in the middle of connecting electrode 161a and second connecting electrode 161b be respectively formed on the part of exposure of elemental semiconductor epitaxial film 130b and on the part of the exposure of the second electrode pad 102b; Middle p-n-connecting electrode 161c is electrically connected to connecting electrode 161b in the middle of the first middle connecting electrode 161a and second.
In chip package process, the gold thread 180a that is connected with the positive and negative electrode of extraneous power supply respectively and 180b will be respectively with window 150a in the part of exposure of the first electrode pad 102a and the part of the exposure of the second electrode pad 102b be electrically connected to.
Fig. 2 e shows the sectional view of different embodiments of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.It is basic identical that the embodiment that Fig. 2 e shows and Fig. 2 d show, difference is: the support substrate of the embodiment in Fig. 2 e is conductive support substrate 101b, and insulating barrier 103a is layered on conductive support substrate 101b.The first electrode pad 102a, middle pad 102c and the second electrode pad 102b are layered on insulating barrier 103a.
Fig. 3 a, Fig. 3 b show the sectional view of an embodiment of part manufacturing process of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.
after the technique that Fig. 3 a shows is stripped from from growth substrates, stacked passivation layer 140 on the unit chip, pass through etching, passivation layer 140 is respectively at the first electrode pad 102a, elemental semiconductor epitaxial film 130a, middle pad 102c, elemental semiconductor epitaxial film 130b, form respectively the window 150a of reservation shape on the preposition of the top of the second electrode pad 102b, 150b, 150c, 150d, 150e, make the first electrode pad 102a, elemental semiconductor epitaxial film 130a, middle pad 102c, elemental semiconductor epitaxial film 130b, the part of the second electrode pad 102b is respectively at window 150a, 150b, 150c, 150d, expose in 150e.
Attention: the shape and size of window 150a and 150c and 150e can be different, also can be identical.The shape and size of window 150b and 150d can be different, also can be identical.
Fig. 3 b shows next step, connecting electrode 160a in the middle of forming first on the elemental semiconductor epitaxial film 130a of the exposure in window 150b, connecting electrode 160b in the middle of forming second on the middle pad 102c of the exposure in window 150c, middle the p-n-connecting electrode 160c that forms simultaneously connecting electrode 160a in the middle of first be connected middle connecting electrode 160b connection.The first connecting electrode 161a and the second connecting electrode 161b are respectively formed on the part of exposure of elemental semiconductor epitaxial film 130b and the second electrode pad 102b; P-n-connecting electrode 161c is electrically connected to the first connecting electrode 161a and the second connecting electrode 161b.
The first electrode pad 102a and the second electrode pad 102b insulate by through hole respectively and support the first and second filler plug 110a and the 110b of the conduction in substrate 101c to be electrically connected to the first power pad 104a and second source pad 104b.
Attention: in chip package process, have two kinds of methods to be connected with extraneous power supply, (1) first power pad 104a will be connected with two electrodes of extraneous power supply respectively with second source pad 104b; (2) by beating gold thread at the first electrode pad 102a and the second electrode pad 102b.
Fig. 4 a and Fig. 4 b show the sectional view of an embodiment of part manufacturing process of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.The embodiment of the part manufacturing process that Fig. 4 a and Fig. 4 b show and Fig. 3 a and Fig. 3 b are basic identical, and different is that the embodiment of Fig. 4 a and Fig. 4 b adopts through hole conductive support substrate 101d to replace the through hole insulation that Fig. 3 a and Fig. 3 b adopt to support substrate 101c.therefore, when preparing to support substrate, to at first distinguish stacked the first insulating barrier 103b and the second insulating barrier 103c on the first and second surfaces of conductive substrates 101d, pass conductive support substrate 101d and the first insulating barrier 103b and the second insulating barrier 103c and form at least one first through hole and at least one second through hole, and the first filler plug 111a that formation is insulated in the first through hole and the second through hole respectively and the second filler plug 111b of insulation, form again through hole in the second filler plug 111b of the first filler plug 111a that insulate and insulation, and the first filler plug 112a that formation is conducted electricity in through hole and the second filler plug 112b of conduction.Form respectively the first electrode pad 102a, the second electrode pad 102b, middle pad 102c on the first insulating barrier 103b; Forming respectively the first power pad 104a and second source pad 104b on the second insulating barrier 103c, make the first electrode pad 102a and the first power pad 104a be electrically connected to by the first filler plug 112a of conduction, the second electrode pad 102b and second source pad 104b are electrically connected to by the second filler plug 112b of conduction.
Fig. 5 a, Fig. 5 b, Fig. 5 c show respectively the equivalent circuit diagram of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.
Fig. 5 a shows the equivalent circuit diagram of an embodiment of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.
Have the unit chip 501,502,503 of at least two without the LED high pressure chip of the vertical stratification of metal electrode and form and be electrically connected in series, therefore, form the LED high voltage direct current chip without the vertical stratification of metal electrode.Dotted line in figure represents the unit chip of a plurality of units in series.
Attention: two or more than forming the high voltage direct current chip after the unit chip series connection of two.
Fig. 5 b shows the equivalent circuit diagram of an embodiment of high-voltage alternating chip of Opposite direction connection formula of the LED high pressure chip of the vertical stratification without metal electrode of the present utility model.
At least two unit chips 504,505 formation are electrically connected in series, and at least two unit chips 506,507 formation are electrically connected in series.The unit chip Opposite direction connection of two string series connection forms the LED high-voltage alternating chip without the vertical stratification of metal electrode.Dotted line in figure represents the unit chip of a plurality of series connection.
Attention: the unit chip Opposite direction connection of at least two forms the high-voltage alternating chip.
Fig. 5 c shows the equivalent circuit diagram of an embodiment of the LED high-voltage alternating chip of the vertical stratification without metal electrode of the present utility model.
A plurality of unit chip 510,511,512,513,514,515 consists of rectifying bridge type and connects.Between unit chip 514 and 515, a plurality of unit chip can be arranged, the dotted line in figure represents the unit xp of a plurality of series connection.Unit chip 510,511 and 514 is in node 520 places electrical connection.Unit chip 512,513 and 515 is in node 521 places electrical connection.
It should be noted that at last: above embodiment only in order to the technical solution of the utility model to be described, is not intended to limit; Although with reference to aforementioned embodiment, the utility model is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme that aforementioned embodiment is put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of each embodiment technical scheme of the utility model.
Claims (10)
1. LED high pressure chip without the vertical stratification of metal electrode comprises:
-support substrate;
The pad of-discrete conduction; Described pad comprises, first electrode pad, pad in the middle of at least one, second electrode pad; Described the first electrode pad, described the second electrode pad and described middle pad are formed on described support substrate; Described the first electrode pad, described the second electrode pad and described middle pad and described support substrate electric insulation;
-at least two discrete elemental semiconductor epitaxial films: described elemental semiconductor epitaxial film comprises: first kind limiting layer, active layer and Second Type limiting layer; The described first kind limiting layer of described elemental semiconductor epitaxial film be bonded in respectively on the precalculated position of described the first electrode pad and middle pad and make described the first electrode pad and described in the middle of the part of pad expose; There is no the described elemental semiconductor epitaxial film of bonding on described the second electrode pad;
-each described pad and bonding described elemental semiconductor epitaxial film thereon forms the unit chip;
-passivation layer: described passivation layer is layered on the surface and side of each described unit chip and described the second electrode pad; Described passivation layer has the window of reservation shape above the preposition of the Second Type limiting layer of described elemental semiconductor epitaxial film, the part of described Second Type limiting layer exposes in described window; Described passivation layer has respectively the window of reservation shape above the preposition of the part of the exposure of described the first electrode pad and described middle pad, the part of the part of described the first electrode pad and described middle pad exposes in described window; Described passivation layer has the window of reservation shape above the preposition of described the second electrode pad, the part of described the second electrode pad exposes in described window;
-at least one transparent middle connecting electrode: described transparent middle connecting electrode comprises the first transparent middle connecting electrode, the second transparent middle connecting electrode, transparent middle p-n-connecting electrode; Wherein, the described first middle connecting electrode is layered on described Second Type limiting layer by the described window of described passivation layer above the described Second Type limiting layer of a described elemental semiconductor epitaxial film; Described in the middle of second connecting electrode by the described window of described passivation layer above pad in the middle of a stacked described elemental semiconductor epitaxial film on it described, be layered in described in the middle of on pad; In the middle of described, the p-n-connecting electrode couples together at least one described first middle connecting electrode and at least one described second middle connecting electrode;
-one transparent connecting electrode: described transparent connecting electrode comprises the first transparent connecting electrode, the second transparent connecting electrode, transparent p-n-connecting electrode; Wherein, described the first connecting electrode is layered on described Second Type limiting layer by the described window of described passivation layer above the described Second Type limiting layer of a described elemental semiconductor epitaxial film; Described the second connecting electrode is layered on described the second electrode pad by the described window of described passivation layer above described the second electrode pad; Described p-n-connecting electrode couples together described the first connecting electrode and described the second connecting electrode.
2. according to claim 1 the LED high pressure chip without the vertical stratification of metal electrode, is characterized in that, described support substrate is that substrate is supported in insulation; Form discrete first electrode pad mutually, pad in the middle of at least one, second electrode pad on the first surface of described insulation support substrate.
3. according to claim 1 the LED high pressure chip without the vertical stratification of metal electrode, is characterized in that, described support substrate is conductive support substrate; Form a layer insulating on the first surface of described conductive support substrate, form discrete first electrode pad mutually on described insulating barrier, pad in the middle of at least one, second electrode pad.
4. according to claim 1 the LED high pressure chip without the vertical stratification of metal electrode, is characterized in that, described support substrate is that substrate is supported in the through hole insulation; Described through hole insulation supports to form in substrate at least one first through hole and second through hole, form respectively the first filler plug of conduction and the second filler plug of conduction in described the first through hole and described the second through hole, form discrete first electrode pad mutually on the first surface of described through hole insulation support substrate, pad in the middle of at least one, second electrode pad; Form discrete the first power pad and second source pad mutually on the second surface of described through hole insulation support substrate; Described the first power pad and described second source pad the second filler plug and the described through hole insulation of the first filler plug by described conduction and described conduction are respectively supported described the first electrode pad on the first surface of substrate and described the second electrode pad to form to be electrically connected to.
5. according to claim 1 the LED high pressure chip without the vertical stratification of metal electrode, is characterized in that, described support substrate is the through hole conductive support substrate; Form respectively the first insulating barrier and the second insulating barrier on the first surface of described through hole conductive support substrate and second surface; Form at least one first through hole and at least one second through hole in described through hole conductive support substrate and described the first insulating barrier and described the second insulating barrier, form respectively the first filler plug of insulation and the second filler plug of insulation in described first through hole and the second through hole, form respectively the first filler plug of conduction and the second filler plug of conduction, the first filler plug of described conduction and the second filler plug of conduction and the mutual electric insulation of described through hole conductive support substrate in the second filler plug of the first filler plug of described insulation and described insulation; Form discrete first electrode pad mutually on described the first insulating barrier on the first surface of described through hole conductive support substrate, pad in the middle of at least one, second electrode pad; Form discrete the first power pad and second source pad mutually on described the second insulating barrier on the second surface of described through hole conductive support substrate, the first filler plug and the second filler plug of described conduction by described conduction of described the first power pad and second source pad is electrically connected to described the first electrode pad and described the second electrode pad formation on the first insulating barrier of described through hole conductive support substrate respectively.
6. LED high pressure chip without the vertical stratification of metal electrode comprises:
-support substrate; Described support substrate comprises, insulation support substrate; Conductive support substrate with insulating barrier;
The pad of-discrete conduction; Described pad comprises, first electrode pad, pad in the middle of at least one; Described the first electrode pad and described middle pad are formed on described support substrate; Described the first electrode pad and described middle pad and described support substrate electric insulation;
-at least two discrete elemental semiconductor epitaxial films: described elemental semiconductor epitaxial film comprises: first kind limiting layer, active layer and Second Type limiting layer; The described first kind limiting layer of described elemental semiconductor epitaxial film be bonded in respectively on the precalculated position of described the first electrode pad and middle pad and make described the first electrode pad and described in the middle of the part of pad expose;
-each described pad and bonding described elemental semiconductor epitaxial film thereon forms the unit chip;
-passivation layer: described passivation layer is layered on the surface and side of each described unit chip; Described passivation layer has the window of reservation shape above the preposition of the Second Type limiting layer of described elemental semiconductor epitaxial film, the part of described Second Type limiting layer exposes in described window; Described passivation layer respectively described the first electrode pad and described in the middle of have the window of reservation shape above the preposition of part of exposure of pad, described the first electrode pad and described in the middle of the part of pad expose in described window respectively;
-at least one transparent middle connecting electrode: described transparent middle connecting electrode comprises the first transparent middle connecting electrode, the second transparent middle connecting electrode, transparent middle p-n-connecting electrode; Wherein, the described first middle connecting electrode is layered on described Second Type limiting layer by the described window of described passivation layer above the described Second Type limiting layer of a described elemental semiconductor epitaxial film; Described in the middle of second connecting electrode by described passivation layer on another its in the middle of stacked described elemental semiconductor epitaxial film described pad above described window, be layered in described in the middle of on pad; In the middle of described, the p-n-connecting electrode couples together at least one described first middle connecting electrode and at least one described second middle connecting electrode;
-the second transparent electrode: described the second electrode is layered on described Second Type limiting layer by the described window of described passivation layer above the described Second Type limiting layer of a described elemental semiconductor epitaxial film.
7. according to claim 1 or the LED high pressure chip without the vertical stratification of metal electrode of claim 6, it is characterized in that, in the middle of described, the p-n-connecting electrode is at least one described first middle connecting electrode to select from one group of connected mode with the connected mode that at least one described second middle connecting electrode couples together, this group connected mode comprises: in the middle of (1), the p-n-connecting electrode forms connecting electrode in the middle of described first on the described Second Type limiting layer of a described elemental semiconductor epitaxial film and the described second middle connecting electrode on the middle pad of adjacent described unit chip the electrical connection of series connection form, (2) in the middle of, the p-n-connecting electrode forms connecting electrodes in the middle of two described second on connecting electrode in the middle of described first on the described Second Type limiting layer of a described elemental semiconductor epitaxial film and the described middle pad at two other adjacent described unit chip and is electrically connected to, (3) in the middle of, the p-n-connecting electrode forms connecting electrodes in the middle of two described first on connecting electrode and the described Second Type limiting layer at two other adjacent described elemental semiconductor epitaxial film in the middle of described second on the described middle pad of a described unit chip and is electrically connected to.
8. according to claim 1 or the LED high pressure chip without the vertical stratification of metal electrode of claim 6, it is characterized in that, whole described unit chip connects with series system, forms the LED high voltage direct current chip without the vertical stratification of metal electrode.
9. according to claim 1 or the LED high pressure chip without the vertical stratification of metal electrode of claim 6, it is characterized in that, whole described unit chip is electrically connected to the rectifier bridge form, forms the LED high-voltage alternating chip without the vertical stratification of metal electrode.
10. according to claim 1 or the LED high pressure chip without the vertical stratification of metal electrode of claim 6, it is characterized in that, whole described unit chip is electrically connected to series connection and reverse parallel connection form, forms the LED high-voltage alternating chip without the vertical stratification of metal electrode.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012205953147U CN202930431U (en) | 2012-11-13 | 2012-11-13 | Vertical structure LED high voltage chip without metal electrodes |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012205953147U CN202930431U (en) | 2012-11-13 | 2012-11-13 | Vertical structure LED high voltage chip without metal electrodes |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014187164A1 (en) * | 2013-05-24 | 2014-11-27 | 厦门市三安光电科技有限公司 | Integrated led light-emitting component and manufacturing method therefor |
| CN104183580A (en) * | 2013-05-20 | 2014-12-03 | 新灯源科技有限公司 | Integrated LED element with epitaxial structure and packaging substrate which are integrated, and manufacturing method thereof |
-
2012
- 2012-11-13 CN CN2012205953147U patent/CN202930431U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104183580A (en) * | 2013-05-20 | 2014-12-03 | 新灯源科技有限公司 | Integrated LED element with epitaxial structure and packaging substrate which are integrated, and manufacturing method thereof |
| WO2014187164A1 (en) * | 2013-05-24 | 2014-11-27 | 厦门市三安光电科技有限公司 | Integrated led light-emitting component and manufacturing method therefor |
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