CN103809105B - There is the chip of low-and high-frequency clock handoff functionality - Google Patents
There is the chip of low-and high-frequency clock handoff functionality Download PDFInfo
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- CN103809105B CN103809105B CN201210453776.XA CN201210453776A CN103809105B CN 103809105 B CN103809105 B CN 103809105B CN 201210453776 A CN201210453776 A CN 201210453776A CN 103809105 B CN103809105 B CN 103809105B
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- clock signal
- frequency clock
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Abstract
The invention discloses a kind of chip with low-and high-frequency clock handoff functionality, including chip sequence circuit, low-frequency clock signal pad, the outfan of low-frequency clock signal pad connects the input of low-frequency clock signal line, the input of the outfan connection system master clock signal line of low-frequency clock signal line, the outfan of system master clock holding wire connects chip sequence circuit；It is provided with special circuit between outfan and the input of system master clock holding wire of low-frequency clock signal line.The high frequency clock signal produced by crystal oscillator can be transferred to chip sequence circuit by the present invention, and enable signal tester occurred by Enable Pin signal pads is effectively controlled, realize by high frequency clock signal produced by crystal oscillator with by the switching of the produced low-frequency clock signal of tester itself, thus enrich the function of tester.
Description
Technical field
The present invention relates to a kind of test chip, be specifically related to a kind of chip with low-and high-frequency clock handoff functionality.
Background technology
Large scale integrated circuit, when testing, often occurs that the clock that tester itself produces can not meet the feelings of test needs
Condition.In order to preferably meet the needs of test, existing method is: shake to the plug-in signal generator of tester or crystal
Swing device, but this plug-in signal is difficult to effectively control and switch.
Existing test chip is as it is shown in figure 1, include chip sequence circuit, low-frequency clock signal pad, low-frequency clock signal pad
Low-frequency clock signal is transmitted to system master clock holding wire by sheet by low-frequency clock signal line, and system master clock holding wire is low by this
Frequently clock signal transmission is to chip sequence circuit, thus tests.
This chip can only transmit low-frequency clock signal, it is impossible to the high frequency clock signal produced by crystal oscillator is transferred to chip sequential electricity
Road.
Summary of the invention
The technical problem to be solved is to provide a kind of chip with low-and high-frequency clock handoff functionality, and it can be by by crystalline substance
The high frequency clock signal produced that shakes is transferred to chip sequence circuit.
For solving above-mentioned technical problem, the technical solution of the chip that the present invention has low-and high-frequency clock handoff functionality is:
Including chip sequence circuit, low-frequency clock signal pad, the outfan of low-frequency clock signal pad connects low-frequency clock signal
The input of line, the input of the outfan connection system master clock signal line of low-frequency clock signal line, system master clock holding wire
Outfan connect chip sequence circuit；Set between outfan and the input of system master clock holding wire of low-frequency clock signal line
It is equipped with special circuit；Described special circuit includes Enable Pin signal pads, high frequency clock signal pad, latch, NAND gate electricity
Road, AND circuit, Enable Pin signal pads connects the first input end of latch by holding wire, and the outfan of latch connects
The first input end of NAND gate circuit；Enable Pin signal pads output low level signal or high level signal；High frequency clock signal
The outfan of pad connects the second input of latch and the second input of NAND gate circuit respectively；High frequency clock signal pad
The high frequency clock signal of crystal oscillator is come from for transmission；The outfan of NAND gate circuit is connected and door electricity by high frequency clock signal line
The first input end on road, the second input of AND circuit connects the outfan of low-frequency clock signal line, the outfan of AND circuit
Connect the input of master clock signal line.
The outfan of described Enable Pin signal pads is parallel with resistance.
When described Enable Pin signal pads output low level signal, by the produced low-frequency clock signal of tester itself from low frequency
Clock signal pad enters chip, and low-frequency clock signal passes through AND circuit through low-frequency clock signal line, when the system that is then passed through is main
Clock holding wire arrives chip sequence circuit, and now chip uses by the produced low-frequency clock signal of tester itself；Make when described
During energy end signal pad output high level signal, enter from high frequency clock signal pad high frequency clock signal produced by plug-in crystal oscillator
Entering chip, high frequency clock signal by AND circuit, is then passed through system master clock through NAND gate circuit, high frequency clock signal line
Holding wire arrives chip sequence circuit, and now chip uses by high frequency clock signal produced by plug-in crystal oscillator.
What the present invention can reach has the technical effect that
The high frequency clock signal produced by crystal oscillator can be transferred to chip sequence circuit by the present invention, and by Enable Pin signal pad
The enable signal that tester is occurred by sheet effectively controls, it is achieved to by high frequency clock signal produced by crystal oscillator with by testing
The switching of the produced low-frequency clock signal of instrument itself, thus the function of abundant tester.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is the schematic diagram of existing test chip；
Fig. 2 is the schematic diagram that the present invention has the chip of low-and high-frequency clock handoff functionality；
Fig. 3 is the oscillogram of the operation principle of the present invention.
Detailed description of the invention
As in figure 2 it is shown, the present invention has the chip of low-and high-frequency clock handoff functionality, including chip sequence circuit, low-frequency clock letter
Number pad, the outfan of low-frequency clock signal pad connects the input of low-frequency clock signal line, the output of low-frequency clock signal line
The input of end connection system master clock signal line, the outfan of system master clock holding wire connects chip sequence circuit；
It is provided with special circuit between outfan and the input of system master clock holding wire of low-frequency clock signal line；Special circuit
Including Enable Pin signal pads EN, high frequency clock signal pad, latch, NAND gate circuit, AND circuit, Enable Pin signal
Pad EN connects the first input end of latch by holding wire, and the outfan of latch connects the first input of NAND gate circuit
End；
The outfan of Enable Pin signal pads EN is parallel with resistance；Enable Pin signal pads EN can with output low level signal or
High level signal, the signal of Enable Pin signal pads EN is for controlling high frequency clock signal and two clock letters of low-frequency clock signal
Number switching signal；
The outfan of high frequency clock signal pad connects the second input of latch and the second input of NAND gate circuit respectively；
High frequency clock signal pad comes from the high frequency clock signal of crystal oscillator for transmission；
The outfan of NAND gate circuit connects the first input end of AND circuit by high frequency clock signal line EN1, AND circuit
Second input connects the outfan of low-frequency clock signal line, and the outfan of AND circuit connects the input of master clock signal line.
Resistance is hung with, so not affecting the normal of the low-frequency clock signal pad of chip outside in Enable Pin signal pads EN of the present invention
Work.
The test philosophy of the present invention is as follows:
To the plug-in signal generator of tester or crystal oscillator, it is used for producing high frequency clock signal；
To all of pad, make including low-frequency clock signal pad, high frequency clock signal pad and Enable Pin signal pads EN simultaneously
Probe；
As it is shown on figure 3, when Enable Pin signal pads EN output low level signal, by the produced low-frequency clock of tester itself
Signal enters chip from low-frequency clock signal pad, and low-frequency clock signal passes through AND circuit, then warp through low-frequency clock signal line
Crossing system master clock holding wire and arrive chip sequence circuit, now chip uses by the produced low-frequency clock signal of tester itself；
When Enable Pin signal pads EN output high level signal, by high frequency clock signal produced by plug-in crystal oscillator from high frequency clock
Signal pads enters chip, and high frequency clock signal passes through AND circuit, then through NAND gate circuit, high frequency clock signal line EN1
Arriving chip sequence circuit through system master clock holding wire, now chip uses by high frequency clock signal produced by plug-in crystal oscillator.
Enable Pin signal pads EN in the present invention and the signal on low-frequency clock signal pad are produced by tester, the most permissible
Preferably control the switching of required clock.
The operational approach of the present invention is as follows:
System has just been opened and has been used the clock produced by tester itself when powering on；When flash memory is tested by needs, pass through Enable Pin
The real-time control of signal pads EN, is in time switched to the 32M clock that crystal oscillator provides；After being completed, then Enable Pin signal
Pad EN is attributed to low level, then be switched to the 10M clock that tester provides, to carry out the test of sundry item.
Claims (3)
1. a chip with low-and high-frequency clock handoff functionality, it is characterised in that: include chip sequence circuit, low-frequency clock
Signal pads, the outfan of low-frequency clock signal pad connects the input of low-frequency clock signal line, low-frequency clock signal line defeated
Going out to hold the input of connection system master clock signal line, the outfan of system master clock holding wire connects chip sequence circuit；Low frequency
It is provided with special circuit between outfan and the input of system master clock holding wire of clock cable；
Described special circuit includes Enable Pin signal pads, high frequency clock signal pad, latch, NAND gate circuit and door electricity
Road, Enable Pin signal pads connects the first input end of latch by holding wire, and the outfan of latch connects NAND gate circuit
First input end；Enable Pin signal pads output low level signal or high level signal；
The outfan of high frequency clock signal pad connects the second input of latch and the second input of NAND gate circuit respectively；
High frequency clock signal pad comes from the high frequency clock signal of crystal oscillator for transmission；
The outfan of NAND gate circuit connects the first input end of AND circuit, the second of AND circuit by high frequency clock signal line
Input connects the outfan of low-frequency clock signal line, the input of the outfan connection system master clock signal line of AND circuit.
The chip with low-and high-frequency clock handoff functionality the most according to claim 1, it is characterised in that: described Enable Pin
The outfan of signal pads is parallel with resistance.
The chip with low-and high-frequency clock handoff functionality the most according to claim 1, it is characterised in that: when described enable
During end signal pad output low level signal, enter from low-frequency clock signal pad the produced low-frequency clock signal of tester itself
Entering chip, low-frequency clock signal by AND circuit through low-frequency clock signal line, is then passed through system master clock holding wire and arrives core
Sheet sequence circuit, now chip uses by the produced low-frequency clock signal of tester itself；
When described Enable Pin signal pads output high level signal time, by high frequency clock signal produced by plug-in crystal oscillator from high frequency time
Clock signal pads enters chip, and high frequency clock signal passes through AND circuit, then warp through NAND gate circuit, high frequency clock signal line
Crossing system master clock holding wire and arrive chip sequence circuit, now chip uses by high frequency clock signal produced by plug-in crystal oscillator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210453776.XA CN103809105B (en) | 2012-11-13 | 2012-11-13 | There is the chip of low-and high-frequency clock handoff functionality |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210453776.XA CN103809105B (en) | 2012-11-13 | 2012-11-13 | There is the chip of low-and high-frequency clock handoff functionality |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103809105A CN103809105A (en) | 2014-05-21 |
| CN103809105B true CN103809105B (en) | 2016-08-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210453776.XA Active CN103809105B (en) | 2012-11-13 | 2012-11-13 | There is the chip of low-and high-frequency clock handoff functionality |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101369452A (en) * | 2008-09-16 | 2009-02-18 | 北京中星微电子有限公司 | Circuit and method for reducing SRAM power consumption |
| CN101526829A (en) * | 2008-03-06 | 2009-09-09 | 中兴通讯股份有限公司 | Burr-free clock switching circuit |
| CN102183721A (en) * | 2010-12-14 | 2011-09-14 | 青岛海信信芯科技有限公司 | Method and circuit for testing multi-clock domain |
| CN102377425A (en) * | 2010-08-09 | 2012-03-14 | 瑞昱半导体股份有限公司 | Multi-phase clock switch device and method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07202690A (en) * | 1993-12-28 | 1995-08-04 | Toshiba Corp | Clock signal generation circuit |
-
2012
- 2012-11-13 CN CN201210453776.XA patent/CN103809105B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101526829A (en) * | 2008-03-06 | 2009-09-09 | 中兴通讯股份有限公司 | Burr-free clock switching circuit |
| CN101369452A (en) * | 2008-09-16 | 2009-02-18 | 北京中星微电子有限公司 | Circuit and method for reducing SRAM power consumption |
| CN102377425A (en) * | 2010-08-09 | 2012-03-14 | 瑞昱半导体股份有限公司 | Multi-phase clock switch device and method thereof |
| CN102183721A (en) * | 2010-12-14 | 2011-09-14 | 青岛海信信芯科技有限公司 | Method and circuit for testing multi-clock domain |
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| Publication number | Publication date |
|---|---|
| CN103809105A (en) | 2014-05-21 |
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