CN103797732B - Communication means, peripheral component interconnection PCIE chip and PCIE device - Google Patents
Communication means, peripheral component interconnection PCIE chip and PCIE device Download PDFInfo
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Abstract
Embodiments provide a kind of communication means, peripheral component interconnection PCIE chip and PCIE device.The method is applied in the interconnected PCIE system of quick peripheral component supporting optical cable transmission.Described PCIE system comprises transmitting terminal PCIE device, optical transmission apparatus and receiving terminal PCIE device.The method comprises: when described transmitting terminal PCIE device needs and described receiving terminal PCIE device establish a communications link, the detected state position of described transmitting terminal PCIE device determination control register comprises the first mark, and described first mark is used for expression and forbids that described transmitting terminal PCIE device performs load detecting; Described transmitting terminal PCIE device performs the link negotiation flow process with described receiving terminal PCIE device, to set up described communication connection with described receiving terminal PCIE device by described optical transmission apparatus.In the application scenarios supporting optical cable transmission, the method that the embodiment of the present invention provides can make transmitting terminal PCIE device and receiving terminal PCIE device establish a communications link smoothly.
Description
Technical field
The present invention relates to optical communication field, particularly a kind of communication means, peripheral component interconnection PCIE chip and PCIE device.
Background technology
Peripheral component interconnection (PeripheralComponentInterconnectExpress, PCIE) standard is the bussing technique of new generation proposed by Intel company.PCIE technology is widely used in the PCIE device such as PC, server and data center.Because electrical transmission range is short, and loss is comparatively large, significantly limit the application of PCIE device.Because optical cable transmission has the little and advantage of long transmission distance of loss, therefore, PCIE standard is progressively applied in the application scenarios of optical cable transmission.
In PICE standard, define a kind of detected state (Detectstate), this state refers to link reset or the initial condition after powering up.In detected state, require that the test section in the transmitter in PCIE chip is detected link receiving terminal and whether be there is a receiver.In detected state, if transmitter detects receiver, then this link enters polling status, and wherein, polling status is the next state of detected state.From polling status, transmitter starts to carry out link negotiation with receiver, to establish a communications link.If in detected state, transmitter does not detect receiver, and transmitter by every 12ms duplicate detection once, cannot enter polling status.Realizing in the system of cable transmission according to PCIE, transmitting terminal PCIE device can to achieve a butt joint the detection of receiving end PCIE device by sending common-mode voltage.
Summary of the invention
Embodiments provide a kind of communication means, peripheral component interconnection PCIE chip and PCIE device, under the scene realizing optical cable transmission according to PCIE, the normal negotiations of transmitting terminal PCIE device and receiving terminal PCIE device can be realized.
First aspect, embodiments provide a kind of communication means, the method is applied in the interconnected PCIE system of quick peripheral component supporting optical cable transmission, described PCIE system comprises transmitting terminal PCIE device, optical transmission apparatus and receiving terminal PCIE device, described method comprises: when described transmitting terminal PCIE device needs and described receiving terminal PCIE device establish a communications link, the detected state position of described transmitting terminal PCIE device determination control register comprises the first mark, and described first mark is used for expression and forbids that described transmitting terminal PCIE device performs load detecting; Described transmitting terminal PCIE device performs the link negotiation flow process with described receiving terminal PCIE device, to set up described communication connection with described receiving terminal PCIE device by described optical transmission apparatus.
In the first possible execution mode of first aspect, described method also comprises: when the message transmission rate that described transmitting terminal PCIE device and described receiving terminal PCIE device are consulted in described link negotiation flow process reaches threshold value, described transmitting terminal PCIE device determines that the balanced indicating bit of described control register comprises the second mark, and described second mark is used for expression and forbids described transmitting terminal PCIE device and described receiving terminal PCIE device negotiation signal parameter; Described transmitting terminal PCIE device transmits data by described communication connection to described receiving terminal PCIE device according to the described signal parameter of configuration.
In conjunction with the first possible execution mode of first aspect, in the execution mode that the second is possible, described method also comprises: in system initialization process, and described transmitting terminal PCIE device configures described signal parameter.
In conjunction with the execution mode that the first or the second of first aspect are possible, in the execution mode that the third is possible, described signal parameter comprises at least one item in following parameter: transmitting terminal signal adjustment parameter or receiving end signal adjustment parameter.
Second aspect, embodiments provide a kind of interconnected PCIE chip of peripheral component fast, described PCIE chip supports optical cable transmission, this PCIE chip comprises link state machine and transceiver, wherein, described link state machine is used for when needs and receiving terminal PCIE chip establish a communications link, and determines that the detected state position of control register comprises the first mark, and described first mark is used for expression and forbids that described PCIE chip performs load detecting.Described transceiver is used for performing the link negotiation flow process with described receiving terminal PCIE chip, to set up described communication connection with described receiving terminal PCIE chip by optical transmission apparatus.
In the first execution mode of second aspect, described link state machine is also for when the message transmission rate that described PCIE chip and described receiving terminal PCIE chip are consulted in described link negotiation flow process reaches threshold value, determine that the balanced indicating bit of described control register comprises the second mark, wherein, described second mark is used for expression and forbids described PCIE chip and described receiving terminal PCIE chip negotiation signal parameter.Described transceiver also for according to configuration signal parameter by described communication connection to described receiving terminal PCIE chip transmission of data.
In conjunction with the first execution mode of second aspect, in the second execution mode of second aspect, described PCIE chip also comprises manager, and described manager is used in system initialization process, configures described signal parameter.
In conjunction with the first or the second execution mode of second aspect, in the third execution mode of second aspect, described signal parameter comprises at least one item in following parameter: transmitting terminal signal adjustment parameter or receiving end signal adjustment parameter.
The third aspect, embodiments provides a kind of interconnected PCIE device of peripheral component fast, comprises the various possible PCIE chip described in execution mode of above-mentioned second aspect or second aspect.
In the communication means that the embodiment of the present invention provides, when transmitting terminal PCIE device needs to establish a communications link with receiving terminal PCIE device, transmitting terminal PCIE device can not perform load detecting according to the first mark pre-set in control register, the initial condition of link is orientated polling status, so as can directly and receiving terminal PCIE device carry out link negotiation.The method can avoid the existence because of optical transmission apparatus to cause transmitting terminal PCIE device to detect, and receiving terminal PCIE device is in place and cannot carry out the problem of link negotiation with receiving terminal PCIE device.In the application scenarios supporting optical cable transmission, the method that the embodiment of the present invention provides can make transmitting terminal PCIE device and receiving terminal PCIE device establish a communications link smoothly.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described.
A kind of PCIE device communication connection schematic diagram that Fig. 1 provides for the embodiment of the present invention;
The application scenarios schematic diagram of a kind of PCIE device that Fig. 2 provides for the embodiment of the present invention;
The structural representation of a kind of PCIE chip that Fig. 3 provides for the embodiment of the present invention;
A kind of communication means flow chart that Fig. 4 provides for the embodiment of the present invention;
Another communication means flow chart that Fig. 5 provides for the embodiment of the present invention.
Embodiment
The present invention program is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the embodiment of a part of the present invention, instead of whole embodiments.
For the ease of understanding this programme, the embodiment of the present invention is first to according to quick peripheral component interconnection (PeripheralComponentInterconnectExpress, PCIE) realize in the PCIE system of cable transmission, the process how transmitting terminal PCIE device and receiving terminal PCIE device establish a communications link is done one and is simply introduced.As shown in Figure 1, in this communication system, comprise the first PCIE device 10 and the second PCIE device 20.Wherein, include in the first PCIE device 10 in PCIE chip 14, second PCIE device 20 and include the 2nd PCIE chip 24.Be connected by cable between first PCIE device 10 with the second PCIE device 20.
Be described for the process established a communications link as the first PCIE device 10 and second PCIE device 20 as receiving terminal PCIE device of transmitting terminal PCIE device below.According to the regulation of PCIE standard, when start or after resetting,---poll (Polling) state---configuration (Configuration) state---L0 state that control link enters by link state machine in the one PCIE chip 14 successively: detected state, normally establish a communications link to make the first PCIE device 10 and the second receiving terminal PCIE device 20, and during L0 state, first PCIE device 10 and the second PCIE device 20 can carry out processing layer packet (TransactionLayerPocket, TLP), data link layer packets (DataLinkLayerPocket, and physical layer data bag (PhysicalLayerPocket DLLP), PLP) transmission and reception.Wherein, physical layer data bag is also referred to as ordered set.It is appreciated of course that the first PCIE device 10 also can as receiving terminal PCIE device, and the second PCIE device 20 also can as transmitting terminal PCIE device.
In the process that above-mentioned first PCIE device 10 and the second PCIE device 20 establish a communications link, first a PCIE chip 14 needs to enter detected state and whether there is the 2nd PCIE chip 24 to detect link receiving terminal.In embodiments of the present invention, also transmitter in detected state can be detected link receiving terminal and whether there is the process of receiver referred to as execution load detecting.In order to be described clearly, simply introduce doing one to the process of load detecting below.In the communication system shown in Fig. 1, two differential lines of the transmitter 2082 of a PCIE chip 14 are respectively by coupling capacitance C
tXbe connected with two differential lines of the receiver 2084 of the 2nd PCIE chip 24.Further, two differential lines of receiver 2084 respectively with two terminating resistor Z
rXone end be connected, two terminating resistor Z
rXthe equal ground connection of the other end.When link enters detected state, the transmitter 2082 in a PCIE chip 14 drives a common-mode voltage different from initial voltage from two terminal D+ with D-of self.For convenience, in embodiments of the present invention, initial voltage is called the first voltage, the common-mode voltage different from initial voltage that transmitter drives at detected state is called the second voltage.Wherein, initial voltage can be V
dD(3.6V) (Ground) or V,
dDand any one common-mode voltage between ground (Ground).Second voltage is a common-mode voltage different from initial voltage.Become in the process of the second voltage from the first voltage, if transmitter 2082 is connected with receiver 2084, then coupling capacitance C
tX, parasitic capacitance in transmitter 2082 differential lines and receiving terminal terminating resistor Z
rXa RC charging circuit can be formed.Owing to having larger coupling capacitance C
tX, the charging interval of this RC charging circuit is longer.If transmitter 2082 is not connected with receiver 2084, then coupling capacitance C
tXdo not work, the charging interval is just shorter.Thus a PCIE chip 14 can judge whether to be connected with the 2nd PCIE chip 24 according to the length in charging interval.Or change a kind of expression way, according to the length in charging interval, a PCIE chip 14 can judge that whether the 2nd PCIE chip 24 is in place.According to the regulation of PCIE, after a PCIE chip 14 detects that the 2nd PCIE chip 24 is in place, can polling status be entered, start link negotiation.Through link negotiation flow process, the communication link between a PCIE chip 14 with the 2nd PCIE chip 24 can normally be connected (Linkup).
It should be noted that, in order to clearly describe the load detecting process of PCIE chip, only the receiver 2084 in the transmitter 2082 in a PCIE chip 14 and the 2nd PCIE chip 24 being illustrated in Fig. 1.Be understandable that, in a PCIE chip 14, also can comprise receiver 2084, in the 2nd PCIE chip 24, also can comprise transmitter 2082.
A kind of application scenarios of the communication means provided the embodiment of the present invention is done one below simply to introduce.The communication means that the embodiment of the present invention provides can be applied to and realize in the communication system of optical cable transmission according to PCIE.As shown in Figure 2, what provide in the embodiment of the present invention a kind ofly realizes in the communication system of optical cable transmission according to PCIE, between the first PCIE device 10 and the second PCIE device 20, be connected with the first optical module (OpticalModule) 12 and the second optical module 22.Be connected by cable between first PCIE device 10 with the first optical module 12.Be connected by cable between second optical module 22 with the second PCIE device 20.Connected by optical fiber 30 between first optical module 12 and the second optical module 22.Wherein, the first optical module 12 and the second optical module 22 are for carrying out the conversion of the signal of telecommunication and light signal.
Still be that transmitting terminal PCIE device, the second PCIE device 20 are for receiving terminal PCIE device for the first PCIE device 10.After the first PCIE device 10 and the second PCIE device 20 establish a communications link, such as, when link is in L0 operating state, if the first PCIE device 10 sends data to the second PCIE device 20, the signal of telecommunication that one PCIE chip 14 sends can be converted to light signal by the first optical module 12 be connected with the first PCIE device 10, and is transferred to the second optical module 22 be connected with second communication node 20 by optical fiber 30.After the light signal of reception is converted to the signal of telecommunication by the second optical module 22, gives the 2nd PCIE chip 24 in the second PCIE device 20 by electric signal transmission, thus the communication between the first PCIE device 10 and the second PCIE device 20 can be realized.Be understandable that, owing to being connected by optical fiber 30 between the first optical module 12 and the second optical module 22, therefore, even if the first PCIE device 10 and the second PCIE device 20 is distant, also can complete communication each other by optical fiber 30.
It should be noted that, the first PCIE device 10 and the first optical module 12 can independently be arranged.Such as, the first PCIE device 10 can be a veneer, and the first optical module 12 can be connected to the edge of the first PCIE device 10 by corresponding connector.First PCIE device 10 and the first optical module 12 also can be integrated in same communication equipment, and such as, if the first PCIE device 10 is veneers, the first optical module 12 also can be arranged in the first PCIE device 10 by corresponding connector.Similar, the second PCIE device 20 and the second optical module 22 can independently be arranged, and the second PCIE device 20 and the second optical module 22 also can be integrated in same communication equipment.Do not limit at this.Further, the first PCIE device 10 and the second PCIE device 20 can lay respectively in distinct device, also can be arranged in same equipment.Such as, the first PCIE device 10 and the second PCIE device 20 can be arranged in different main frames, also can be arranged in same main frame.Also do not limit at this.
For convenience, in embodiments of the present invention, the first optical module 12, optical fiber 30 and the second optical module 22 can be referred to as optical transmission apparatus, for realizing the Signal transmissions between the first PCIE device 10 and the second PCIE device 20.In the process of optical transmission apparatus signal transmission, optical transmission apparatus may be used for the conversion realized between the signal of telecommunication and light signal.How optical transmission apparatus realizes Signal transmissions similarly to the prior art, therefore, in the embodiment of the present invention, to optical transmission apparatus how to realize light signal and the signal of telecommunication conversion and transmission be not described in detail.It should be noted that, in the embodiment of the present invention, the first PCIE device 10 of indication and the second PCIE device 20 all do not comprise the optical transmission apparatus such as optical module.
But, in the communication system shown in Fig. 2, be connected by optical transmission apparatus such as the first optical module (OpticalModule) 12, optical fiber 30 and the second optical modules 22 between the first PCIE device 10 with the second PCIE device 20.When link enters detected state, because the common mode voltage signal being used for detecting the 2nd PCIE chip 24 can not be converted to effective light signal and transfer to the 2nd PCIE chip 24 by optical module, therefore, when link is in detected state, a PCIE chip 10 cannot according to the in place detection of PCIE standard implementation to the 2nd PCIE chip 24.Make link cannot enter poll (Polling) state from detected state, the first PCIE device 10 second PCIE device 20 can not carry out link negotiation, causes link normally to connect.
The structural representation of a kind of PCIE chip that Fig. 3 provides for the embodiment of the present invention, the PCIE chip that the embodiment of the present invention provides can be applied to and realize in the scene of optical cable transmission according to PCIE.As shown in Figure 3, the PCIE chip 20 shown in Fig. 3 can be the PCIE chip 14 shown in Fig. 2 and the 2nd PCIE chip 24.As shown in Figure 3, PCIE chip 20 can comprise: communication interface 202, link state machine 204, manager 206 and transceiver 208.Wherein, transceiver 208 comprises transmitter 2082 and receiver 2084.Manager 206 comprises configuration module 2061 and supervisory circuit 2062.Realizing in the application scenarios of optical cable transmission according to PCIE, PCIE chip 20 can be connected with optical module by port connector 212.Such as, when PCIE chip 20 is for a PCIE chip 14 shown in Fig. 2, a PCIE chip 14 can be connected with the first optical module 12 by port connector 212.Wherein:
Communication interface 202 is specifically as follows the physical layer of PCIE chip 20 and the interface on upper strata.Wherein, upper strata refers to the upper strata of the physical layer of PCIE chip, can comprise data link layer (DataLinkLayer) or processing layer (TransactionLayer) etc.The module of physical layer can be communicated with the module on upper strata by communication interface 202.When PCIE chip sends data, data to be sent can be transferred to the transmitter 210 of physical layer by upper strata by communication interface 202, data sent by transmitter 210.When PCIE chip receives data, the data of reception can be transferred to upper strata by communication interface 202 and process by receiver 212.
Link state machine 204, link training and conditions state machine (LinkTrainingAndStatusStateMachine can be called again, LTSSM), link state machine 204 is subdivisions of PCIE chip 20 physical layer, be mainly used in realizing link initialization and orientation process, the linking status of control link and the power management states of link, make link can transmit packet normally.In practical application, link state machine 204 can receive the link information on upper strata by communication interface 202, according to the state of the link information control link of upper layer transport.Link state machine 204 can also determine the state of link by the transmission situation of monitoring transmitter 2082.Such as, if link state machine 204 monitors transmitter 2082 when not sending data, then can determine that link needs to enter electric free time (ElectricalIdle, EI) state.Link state machine 204 can also determine Link State according to the control register in configuration module 2061.
Manager 206 is for realizing the management function to PCIE chip.Manager 206 can comprise configuration module 2061 and supervisory circuit 2062.
Configuration module 2061 specifically can comprise the various register such as control register, status register.Wherein, control register is used for control link state and link practical function.Such as, link state machine 204 can carry out directional link state according to the control register in configuration module 2061, enter detected state, polling status or L0 state etc. according to control register control link.Status register can comprise Link Status register, and Link Status register may be used for showing Link State.Status register can also comprise the status register for representing PCIE chip 20 own bus state, such as, for representing the status register of cable situation in place.Wherein cable can comprise cable or optical cable.Be understandable that, link state machine 204 can come the control of practical function or the determination of link circuit condition according to the value of the corresponding bits position of each register in configuration module 2061.Such as, link state machine 204 can pass through the value reading corresponding bit in register, to obtain the state information of link or to understand cable situation in place.Be understandable that, control register or status register all can have multiple.
Supervisory circuit 2062 for monitoring the state in place of cable, and configures accordingly to the register in configuration module 2061.In practical application, supervisory circuit 2062 can by arranging the corresponding bits position in each register in configuration module 2061, to realize the setting to Link State.Supervisory circuit 2062 can also pass through the cable signal in place obtaining port connector 212, to judge whether port connector 212 is connected with cable.Usually, when port connector 212 does not have connection cable, cable signal in place is a high level, and when port connector 212 is connected with cable, this signal in place becomes low level from high level.By the change of monitoring cable signal in place, supervisory circuit 2062 can judge whether port connector 212 is connected with cable.When supervisory circuit 2062 judges that cable signal in place is effective, supervisory circuit 2062 further can go the non-volatile memories information reading cable inner, to obtain the type of this cable for cable or optical cable by outband management passage.Wherein, cable signal in place effectively refers to that port connector 212 is connected with cable, and the non-volatile memories packets of information of cable inner draws together the information such as cable type, length of cable.Such as, realizing in the application scenarios of optical cable transmission according to PCIE, PCIE chip 20, when obtaining cable signal in place and being effective, can obtain the cable type information of port connector 212 connection further according to outband management passage, be optical cable with what obtain port connector 212 connection.It should be noted that, optical cable here refers to the optical cable be connected with optical module.Change a kind of expression way, realizing in the application scenarios of optical cable transmission according to PCIE, PCIE chip 20 can obtain port connector 212 according to outband management passage and be connected with optical module.Wherein, outband management passage can comprise inner integrated circuit (Inter-IntegratedCircuit, I2C) passage.
Transceiver 208 for performing the negotiation flow process with opposite end PCIE device, and realizes the transfer of data with opposite end PCIE device.Wherein, described negotiation flow process sends negotiation signal by transmitter 2082 to opposite end PCIE device, and received by receiver 2084 that the response signal of described opposite end PCIE device realizes.Described transfer of data comprises the data transmitted to opposite end PCIE device transmission upper strata by communication interface 202 by transmitter 2082, also comprises the data being received opposite end PCIE device transmission by receiver 2084.It should be noted that, transceiver 208 can perform link negotiation flow process or send data to opposite end PCIE device under the control of link state machine 204 with receiving terminal PCIE device.Transceiver 208 specifically can comprise transmitter 2082 and receiver 2084.
Transmitter 2082 is for sending information.The transmitter 2082 of PCIE chip 20 is specifically as follows transmitter driving circuit.The information that transmitter 2082 sends sends in the mode of the signal of telecommunication.According to this mode, upper strata can be converted to electric pulse waveform by the data to be sent that communication interface 202 is transmitted and send by transmitter 2082.In the PCIE system supporting optical signal transmission, transmitter 2082 is connected with optical module by port connector 212 usually.Data can be sent to optical module by port connector 212 by transmitter 2082 as electronic signals, are sent to receiving terminal optical module after the signal of telecommunication that transmitter 2082 sends can be converted to light signal by optical module.In practical application, data to be sent can be carried out encoding, after parallel-serial conversion or the process such as to postemphasis, then the data after process be sent by transmitter 2082.Wherein, parallel-serial conversion refers to and the parallel data of upper layer transport is converted to serial data.Postemphasis and refer to that transmitting terminal PCIE chip sends signal, to compensate the decay of transmission line to radio-frequency component by the mode improving signal high frequency components amplitude in advance.Wherein, the concrete numerical value that signal high frequency components amplitude improves can adjust parameter (preset) according to signal and determine.
Those skilled in the art can know, due to according in the process of PCIE standard transmission data, pcb board material cheap in link and connector have very large decay to the radio-frequency component in signal.Further, when signal transmission rate is higher, the radio-frequency component in signal is more, decays more severe, cannot ensure signal quality.In order to improve the reliability of link transmission, improving the quality of Signal transmissions, usually can adopt at transmitting terminal PCIE chip and receiving terminal PCIE chip and postemphasising (De-emphasis) and balanced (Equalization) technology.
In PCIE1.0, have employed postemphasising of-3.5dB, in PCIE2.0, have employed postemphasising of-3.5dB and-6dB.In PCIE3.0, because signal rate is higher, have employed 2 more complicated rank to postemphasis technology, send except (De-emphasis) except increasing amplitude to the radio-frequency component in signal, also increase amplitude to the signal of front 1 bit of radio-frequency component to send, this amplitude increased is called preshoot (Preshoot) usually.In PCIE3.0, define the combination of multiple different Preshoot and De-emphasis.In embodiments of the present invention, the combination of Preshoot and De-emphasis is called signal adjustment parameter (preset).The Preset coding of transmitting terminal can as shown in Table 1:
Table one: transmitting terminal Preset encodes
Receiver 2084 for when PCIE chip 20 is as receiving terminal PCIE chip, the information that receiving end/sending end PCIE chip is sent by optical transmission apparatus.Be understandable that, receiver 2084 also can be receiving circuit usually.Be understandable that, in the PCIE system supporting optical signal transmission, receiver 2084 is connected with receiving terminal optical module by port connector 212 usually.The light signal of reception can be converted to the signal of telecommunication by receiving terminal optical module, and after processing accordingly, is transferred to receiver 2084.Such as, in the PCIE system described in Fig. 2, when a PCIE chip 14 sends data to the 2nd PCIE chip 24, the data that the transmitter 2082 that the receiver 2084 of the 2nd PCIE chip 24 can receive a PCIE chip 14 is sent by optical transmission apparatus.Wherein, optical transmission apparatus comprises the first optical module 12, optical fiber 30 and the second optical module 22.In practical application, the process such as serioparallel exchange, decoding or equilibrium (Equalization) can be carried out to the data that receiver 2084 receives, then the data after process are transferred to upper strata by communication interface 202 and carry out respective handling.Wherein, serioparallel exchange refers to and the serial data of reception is converted to parallel data.Equilibrium refers to and increases an equalizing circuit at receiving terminal PCIE chip internal, is raised the high fdrequency component in the signal received, realize further compensating the loss of circuit by this equalizing circuit.Wherein, the numerical value that signal is elevated can adjust parameter (Preset) according to receiving end signal and determine.Receiving terminal Preset encodes can as shown in following table two:
Table two: receiving terminal Preset encodes
It should be noted that, according to the regulation of existing PCIE, the concrete numerical value of transmitting terminal signal adjustment parameter (Preset) and the signal parameter such as receiving terminal Preset can by transmitting terminal PCIE chip and receiving terminal PCIE chip auto negotiation in equalization program (Equalizationprocedure), can find out optimum Preset from multiple Preset.The PCIE1.0 described in the embodiment of the present invention refers to 1st generation PCIE standard, and PCIE2.0 refers to 2nd generation PCIE standard, and PCIE3.0 refers to the 3rd generation PCIE standard.
Below by realizing in the scene of optical cable transmission according to PCIE, the method how adopting the PCIE chip 20 shown in Fig. 3 to establish a communications link is being described in detail.The method flow diagram of a kind of communication means that Fig. 4 provides for the embodiment of the present invention.Method described by Fig. 4 can be applied in the communication system shown in Fig. 2, and the method can perform by PCIE chip 20 as shown in Figure 3.Angle from transmitting terminal PCIE chip is described this communication means by the embodiment of the present invention.Be understandable that, as shown in Figure 2, when a PCIE chip 14 is transmitting terminal PCIE chip, the 2nd PCIE chip 24 is receiving terminal PCIE chip.It should be noted that, a PCIE chip 14 both can as transmitting terminal PCIE chip, also can as receiving terminal PCIE chip.When a PCIE chip 14 can as receiving terminal PCIE chip time, can using the 2nd PCIE chip 24 as transmitting terminal PCIE chip.The embodiment of the present invention using a PCIE chip 14 as shown in Figure 2 be transmitting terminal PCIE chip, the 2nd PCIE chip 24 to illustrate description as receiving terminal PCIE chip.Below in conjunction with Fig. 2 and Fig. 3, the method shown in Fig. 4 is described.As shown in Figure 4, the method comprises:
In step 405, when described transmitting terminal PCIE device needs to establish a communications link with described receiving terminal PCIE device, state-detection position in transmitting terminal PCIE device determination control register comprises the first mark, and described first mark is used for expression and forbids that described transmitting terminal PCIE device performs load detecting.As shown in Figure 2, after a PCIE chip 14 powers on, recovers or exit basic reset or Hot resets, a PCIE chip 14 needs to establish a communications link with the 2nd PCIE chip 24.According to the relevant regulations of PCIE standard, after a PCIE chip 14 powers on, recovers or exit basic reset or Hot resets, first state that link enters should be detection (Detect) state.In detected state, a PCIE chip 14 will perform load detecting, and whether the equipment connected in order to detect link far-end exists, to establish a communications link with the 2nd PCIE chip 24 of link far-end.Under the application scenarios shown in Fig. 2, the 2nd PCIE chip 24 of link far-end is receiving terminal PCIE device.In embodiments of the present invention, as shown in Figure 2, because a PCIE chip 14 is connected by optical transmission apparatus with the 2nd PCIE chip 24, in step 405, when a PCIE chip 14 needs to establish a communications link with the 2nd PCIE chip 24, if the link state machine 204 in a PCIE chip 14 determines that the state-detection position in control register comprises the first mark, then a PCIE chip 14 can't enter detected state to perform load detecting according to the regulation of PCIE standard.In practical application, link state machine 204 in one PCIE chip 14 can read the value of the control register in configuration module 2061, judge whether the detected state position in control register comprises the first mark, wherein, the first mark is used for expression and forbids that described transmitting terminal PCIE device performs load detecting.Change a kind of expression way, it is invalid that the first mark is used for label detection mode bit.
In embodiments of the present invention, control register can comprise multiple bit (bit) position, can represent different Link States with different bit fields, and can represent by different marks that whether this mode bit is effective.Wherein, Link State can comprise: detect the Link State that the PCIE standards such as (Detect) state, poll (Polling) state, configuration (Configuration) state, recovery (Recovery) or L0 specify.Mode bit effectively represents to be needed to enter this Link State, and mode bit invalid representation is prohibited from entering this Link State.Such as, the detected state of link can be represented with the bit of the 8th in controller register, represent that when the value of this bit is 1 detected state position is effective, represent that when the value of this bit is 0 detected state position is invalid.
In embodiments of the present invention, the mode bit in control register can be pre-configured.In practical application, in one case, in the system initialization process of a PCIE chip 14, supervisory circuit 2062 can be configured the control register in configuration module 2061 according to configuration file.In another scenario, in the system initialization process of a PCIE chip 14, supervisory circuit 2062 can also be configured control register according to the pin level of configuring chip.During concrete configuration, supervisory circuit 2062 can arrange the value of the corresponding state position in control register according to the pin level of configuration file or configuring chip.
Realize in the scene of optical cable transmission because the method shown in Fig. 4 is applied to according to PCIE, consider when link enters detected state, optical module 12 can not be converted to effective light signal by being used for detecting the 2nd PCIE chip 24 common mode voltage signal whether in place and transferring to the 2nd PCIE chip 24, therefore, in embodiments of the present invention, it is invalid to be set to the detected state position in control register in advance, makes a PCIE chip 14 not carry out load detecting.Such as, the detected state position in control register can be set to 0.Certainly, also can represent that detected state position is effective with 0, represent that detected state position is invalid with 1, do not limit at this.
In step 410, described transmitting terminal PCIE device performs the negotiation flow process with described receiving terminal PCIE device, to set up described communication connection with described receiving terminal PCIE device by described optical transmission apparatus.Due in step 405, link state machine 204 determines that control register comprises the first mark, and therefore, Link State can be directed to polling status according to the first mark by link state machine, and wherein, polling status is the next state of detected state.From polling status, a PCIE chip 14 will carry out link negotiation by the optical transmission apparatus such as the first optical module 12, optical fiber 30 and the second optical module 22 and the 2nd PCIE chip 24.Concrete, during polling status, the transmitter 2082 in a PCIE chip 14 can send TS1 ordered set and TS2 ordered set by optical transmission apparatus to the 2nd PCIE chip 24 and respond the TS1 ordered set sent by the 2nd PCIE chip 24 and TS2 ordered set that receiver 2084 receives.According to this mode, one PCIE chip 14 and the 2nd PCIE chip 24 notify the support situation of opposite end to higher rate by exchanging TS1 ordered set and TS2 ordered set and speed field, and the data rate on all passages are changed to the flank speed that both link ends supports.Wherein, TS1 ordered set and TS2 ordered set all belong to physical layer data bag (PhysicalLayerPocket, PLP).After the negotiations process completing polling status, link is directed to configuration status by link state machine 204, to perform the negotiation flow process in configuration status.In configuration status, a PCIE chip 14 can carry out the negotiation of link and passage with the 2nd PCIE chip 24.Such as can hold consultation to link No., channel number, bandwidth chahnel etc.By above-mentioned negotiation flow process, the communication connection between a PCIE chip 14 and the 2nd PCIE chip 24 can be set up.
In the embodiment of the method shown in Fig. 4, realizing in the PCIE system of optical cable transmission according to PCIE, when a PCIE chip 14 needs to establish a communications link with the 2nd PCIE chip 24, one PCIE chip 14 can not perform load detecting according to the first mark pre-set in control register, the initial condition of link is orientated polling status, directly link negotiation can be carried out with the 2nd PCIE chip 24.Method shown in Fig. 4 can avoid the existence because of optical transmission apparatus to cause a PCIE chip 14 to detect, and the 2nd PCIE chip is in place and cannot carry out the problem of link negotiation with the 2nd PCIE chip 14.A PCIE chip 14 and the 2nd PCIE chip 24 can be made to establish a communications link smoothly by the method for embodiment described in Fig. 4.
The method flow diagram of another communication means that Fig. 5 provides for the embodiment of the present invention.The method can be applied to and realize in the PCIE system of optical cable transmission according to PCIE, and the method can be performed by the PCIE device comprising PCIE chip.Such as, the first PCIE device 10 as shown in Figure 2 or the second PCIE device 20 can perform, or can a PCIE chip 14 as shown in Figure 2 or the 2nd PCIE chip 24 perform, the PCIE chip 20 that also can be shown by Fig. 3 performs.Fig. 5 is still for the PCIE chip 14 shown in Fig. 2.Below in conjunction with Fig. 2 and Fig. 3, the method shown in Fig. 5 is described in detail.As shown in Figure 5, the method can comprise:
In step 500, PCIE chip 14 power-up initializing.Fig. 5 is to need after PCIE chip 14 power-up initializing to establish a communications link with the 2nd PCIE chip 24.Be understandable that, a PCIE chip 14 except needing to establish a communications link with the 2nd PCIE chip after power-up initializing, can also receive reset command or exit return to form after re-establish communication connection with the 2nd PCIE chip.Wherein, reset comprises basic reset (cold reset or hot reset) and Hot reset.Hot resets the reset referring to and transmit in the band that triggered by software.Return to form also referred to as redirecting (Re-Training) state.According to the regulation of PCIE, after link exits and returns to form, detected state can be entered, so that transmitting terminal PCIE chip and receiving terminal PCIE chip re-establish communication connection.
In practical application, in the process of PCIE chip 14 power-up initializing, initial configuration can also be carried out to the control register in a PCIE chip 14 and status register.In initial configuration process, supervisory circuit 2062 in one PCIE chip 14 first can judge the cable type that port connector 212 connects, different configuration files is loaded again, to realize the configuration to control register and status register according to corresponding cable type.During concrete configuration, supervisory circuit 2062 can arrange the value of the corresponding state position in control register according to the pin level of configuration file or configuring chip.Such as, when the supervisory circuit 2062 in a PCIE chip 14 obtains after port connector 212 is connected with optical module, supervisory circuit 2062 can be configured the control register in configuration module 2061 according to the pin level of the configuration file preset or configuring chip.Detected state position in the control register of the one PCIE chip 14 can be set to the first mark by supervisory circuit 2062, and the balanced indicating bit in control register is set to the second mark.
In step 505, one PCIE chip 14 judges whether the detected state position of control register comprises the first mark, if do not comprise the first mark in the control register of a PCIE chip, then the method enters step 510, otherwise the method enters step 520.In practical application, when after PCIE chip 14 power-up initializing, the link state machine 204 in a PCIE chip 14 can judge whether the detected state position in the control register in configuration module 2061 comprises the first mark.Wherein, the first mark is prohibited from entering detected state for expression.Be understandable that, the detected state position in control register is not limited to a bit, can be one section of bit.First mark can represent with 0, also can represent with 1, can also represent by other marks such as 01 or 00.Do not limit at this.In embodiments of the present invention, if in step 505, link state machine 204 in one PCIE chip 14 detects that the detected state position in control register comprises the first mark, then the initial condition of link directly can be orientated polling status by link state machine 204, starts to carry out link negotiation with the 2nd PCIE chip 24.Wherein, polling status is the next state of detected state.
In step 510, a PCIE chip 14 performs load detecting.In practical application, if a PCIE chip 14 judges not comprise the first mark in the detected state position of control register in step 505, then a PCIE chip 14 link state machine 204 can according to the regulation of PCIE standard, link is directed to detected state, perform load detecting, whether be connected with the 2nd PCIE chip 24 with the far-end detecting link.Perform in the process of load detecting at a PCIE chip 14, a PCIE chip 14 can adopt the method described in Fig. 1, judges that whether the 2nd PCIE chip 24 is in place according to the length in charging interval.Whether the one PCIE chip 14 also can adopt additive method to detect the 2nd PCIE chip 24 in place, does not limit at this.
In step 515, a PCIE chip 14 judges whether the 2nd PCIE chip 24 to be detected, if the 2nd PCIE chip 24 detected, then the method enters step 520, otherwise returns execution step 510, continues to perform load detecting.In practical application, when a PCIE chip 14 detects the 2nd PCIE chip 24, then Link State can be directed to polling status by the link state machine 204 in a PCIE chip 14, and the method can enter step 520.
In step 520, a PCIE chip 14 carries out link negotiation by optical transmission apparatus and the 2nd PCIE chip 24.According to the regulation of PCIE standard, after link enters polling status, transmitting terminal PCIE chip starts to carry out link negotiation with receiving terminal PCIE chip.Negotiation flow process described in the embodiment of the present invention comprises the negotiations process of link at polling status and configuration status, and the negotiations process that this process and PCIE standard specify is similar, and the description of step 410 that specifically can be shown in Figure 4, does not repeat them here.
In step 525, a PCIE chip 14 judges whether to establish a communications link with the 2nd PCIE chip 24, if do not established a communications link with the 2nd PCIE chip 24, then return and perform step 505, otherwise the method enters step 530.In practical application, when a PCIE chip 14 and the 2nd PCIE chip 24 are consulted successfully, when normally establishing a communications link to make a PCIE chip 14 and the 2nd PCIE chip 24, link is directed to L0 operating state by the link state machine 204 in a PCIE chip 14.In L0 operating state, the transmitter 2082 of a PCIE chip 14 can transmit data by optical transmission apparatus to the 2nd PCIE chip 24 according to described communication connection.One PCIE chip 14 can be that upper strata is transferred to the data of physical layer by communication interface 202 to the data that the 2nd PCIE chip 24 transmits.Wherein, the data that upper strata is transferred to physical layer by communication interface 202 comprise processing layer packet (TransactionLayerPocket, TLP) and data link layer packets (DataLinkLayer, DLLP).
During link negotiation, the abnormal conditions such as the 2nd PCIE chip 24 is not in place also may occur and cause link negotiation failure, thus a PCIE chip 14 and the 2nd PCIE chip cannot establish a communications link.Can return to when consulting unsuccessfully and perform step 505, again determine whether to need detection the 2nd PCIE chip 24 whether in place or again determine that the 2nd PCIE chip 24 is in place, again to initiate the negotiation flow process with the 2nd PCIE chip 24.Certainly, in step 525, if link negotiation failure, also can adopt and directly exit the method flow process or return other processing modes such as performing step 520, the embodiment of the present invention does not limit.
In step 530, a PCIE chip 14 judges whether the message transmission rate of consulting reaches threshold value.If the message transmission rate of consulting does not reach threshold value, the method enters step 535, if the message transmission rate of consulting reaches threshold value, then the method enters step 540.According to the description of step 410 in Fig. 4, during polling status, one PCIE chip 14 and the 2nd PCIE chip 24 can notify the support situation of opposite end to more bit rate by exchanging TS1 ordered set and TS2 ordered set and speed field, and the message transmission rate on all passages are changed to the flank speed that both link ends supports.Therefore, in this step, a PCIE chip 14 can judge whether the message transmission rate of consulting reaches threshold value, and wherein, threshold value here can comprise the message transmission rate that PCIE3.0 supports, such as 8.0Gbps.Be understandable that, the message transmission rate that a PCIE chip 14 and the 2nd PCIE chip 24 are consulted is the maximum data transmission rate that a PCIE chip 14 and the 2nd PCIE chip 24 are supported.
In step 535, a PCIE chip 14 sends data according to the message transmission rate of consulting to the 2nd PCIE chip 24.Such as, if the message transmission rate of consulting is 5.0Gbps, then the transmitter 2082 of a PCIE chip 14 can send TLP or DLLP according to the message transmission rate of 5.0Gbps to the 2nd PCIE chip 24.Wherein, the data that a PCIE chip 14 sends can comprise TLP and DLLP.
In step 540, a PCIE chip 14 judges whether the balanced indicating bit in control register comprises the second mark, if the balanced indicating bit in control register comprises the second mark, enter step 545, otherwise the method enters step 550.As described in Figure 2, in the control register of a PCIE chip 14, the multiple flags such as detected state position, polling status position, configuration status position or balanced indicating bit can be represented by different bits.Wherein, whether balanced indicating bit performs equalization program (Equalizationprocedure) for control link.In equalization program, a PCIE chip 14 needs and the 2nd PCIE chip 24 negotiation signal parameter, and described signal parameter is for improving the quality of the signal of communication of a PCIE chip 14 and the 2nd PCIE chip 24.Signal parameter in the embodiment of the present invention comprises transmitting terminal signal adjustment parameter (Preset) and and receiving terminal preset.In order to ensure the signal quality of link, according to the regulation of PCIE standard, transmitting terminal PCIE device and receiving terminal PCIE device generally provide multiple Preset, and transmitting terminal PCIE device and receiving terminal PCIE device can find out optimum Preset value in equalization program.
In embodiments of the present invention, the second mark is used for expression and forbids described transmitting terminal PCIE device and described receiving terminal PCIE device negotiation signal parameter.Change a kind of expression way, the second mark is used for forbidding that described transmitting terminal PCIE device and described receiving terminal PCIE device perform equalization program (Equalizationprocedure).It should be noted that, the balanced indicating bit in the embodiment of the present invention is not limited to a bit, can be one section of bit.Second mark can represent with 0, also can represent with 1, can also represent, do not limit at this by other marks such as 01 or 11.Description about equalization program and signal parameter can see the associated description of Fig. 2.
In step 545, a PCIE chip 14 sends data by described communication connection to the 2nd PCIE chip 24 according to the signal parameter of configuration.In embodiments of the present invention, owing to being connected by optical transmission apparatus such as optical modules between a PCIE chip 14 with the 2nd PCIE chip 24.Due to the amplitude limiting characteristic of optical module, different range signals higher or lower than decision threshold may be exported according to the signal of same amplitude, Preset information dropout in the signal that transmitting terminal PCIE chip therefore may be caused to send, receiving terminal PCIE chip " can't see " the Preset information of signal, cause in equalization program, the Preset value possibility also non-optimal that transmitting terminal PCIE chip and receiving terminal PCIE chip are consulted.In order to improve signal quality, in embodiments of the present invention, can in the process of PCIE chip 14 power-up initializing, be a PCIE chip 14 configuration signal parameter according to configuration file, wherein, the signal parameter of configuration comprises Preset.It should be noted that, the signal parameter of configuration specifically can comprise transmitting terminal Preset and receiving terminal Preset.One PCIE chip 14 can send data according to the transmitting terminal Preset of configuration to the 2nd PCIE chip 14.When a PCIE chip 14 receives the data of the 2nd PCIE chip 24 transmission, equilibrium treatment can be carried out according to the receiving terminal Preset of configuration to the signal received.In this way, the quality of the signal of communication between a PCIE chip 14 and the 2nd PCIE chip 24 is improved.
In step 550, a PCIE chip 14 and the 2nd PCIE chip negotiation signal parameter.Concrete, when in step 540, when a PCIE chip 14 judges not comprise the second mark in control register, control link can enter equalization program, with the 2nd PCIE chip negotiation signal parameter.
In step 555, a PCIE chip 14 sends data by described communication connection to the 2nd PCIE chip 24 according to the signal parameter consulted.In practical application, a PCIE chip 14 can send data according to the signal parameter consulted in step 550 to the 2nd PCIE chip.The data that one PCIE chip 14 sends can comprise TLP and DLLP.
The communication means realizing optical cable transmission according to PCIE shown in Fig. 5, on the basis of the embodiment shown in Fig. 4, after a PCIE chip 14 and the 2nd PCIE chip 24 establish a communications link, when the message transmission rate that described transmitting terminal PCIE device and described receiving terminal PCIE device are consulted reaches threshold value, if a PCIE chip 14 is determined to comprise the second mark in the balanced indicating bit of control register further, then a PCIE chip 14 is without the need to entering equalization program and the 2nd PCIE chip 24 negotiation signal adjusts parameter, one PCIE chip 14 directly can send data according to the signal adjustment parameter of configuration to the 2nd PCIE chip 24, improve the quality of Signal transmissions.
One of ordinary skill in the art will appreciate that all or part of step realizing above-described embodiment can have been come by hardware, the hardware that also can carry out instruction relevant by program completes.Described program comprises computer-managed instruction, can be stored in a kind of computer-readable recording medium.The above-mentioned storage medium mentioned can be random asccess memory (Random-AccessMemory, RAM), magnetic disc, hard disk, CD, solid state hard disc (SolidStateDisk, SSD) or nonvolatile memory (non-volatilememory) etc. various can be program code stored (non-transitory) machine readable media of non-transience, do not limit at this.
It should be noted that, the embodiment that the application provides is only schematic.Those skilled in the art can be well understood to, and for convenience of description and succinctly, in the above-described embodiments, all emphasizes particularly on different fields to the description of each embodiment.The part described in detail is not had in certain embodiment, can see the associated description of other embodiments.The feature disclosed in the embodiment of the present invention, claim and accompanying drawing can independently exist also can combine existence.The feature described in the form of hardware in embodiments of the present invention can be performed by software, and vice versa.Do not limit at this.
Claims (9)
1. one kind is applied to the communication means in quick peripheral component interconnected (PCIE) system supporting optical cable transmission, described PCIE system comprises transmitting terminal PCIE device, optical transmission apparatus and receiving terminal PCIE device, it is characterized in that, described method comprises:
When described transmitting terminal PCIE device needs to establish a communications link with described receiving terminal PCIE device, the detected state position of described transmitting terminal PCIE device determination control register comprises the first mark, and described first mark is used for expression and forbids that described transmitting terminal PCIE device performs load detecting;
Described transmitting terminal PCIE device performs the link negotiation flow process with described receiving terminal PCIE device, to set up described communication connection with described receiving terminal PCIE device by described optical transmission apparatus.
2. communication means according to claim 1, is characterized in that, also comprises:
When the message transmission rate that described transmitting terminal PCIE device and described receiving terminal PCIE device are consulted in described link negotiation flow process reaches threshold value, described transmitting terminal PCIE device determines that the balanced indicating bit of described control register comprises the second mark, and described second mark is used for expression and forbids described transmitting terminal PCIE device and described receiving terminal PCIE device negotiation signal parameter;
Described transmitting terminal PCIE device transmits data by described communication connection to described receiving terminal PCIE device according to the described signal parameter of configuration.
3. communication means according to claim 2, is characterized in that, described method also comprises:
In system initialization process, described transmitting terminal PCIE device configures described signal parameter.
4. the communication means according to Claims 2 or 3, is characterized in that, described signal parameter comprises at least one item in following parameter: transmitting terminal signal adjustment parameter or receiving end signal adjustment parameter.
5. quick peripheral component interconnected (PCIE) chip, described PCIE chip supports optical cable transmission, it is characterized in that, comprising:
Link state machine, for when needs and receiving terminal PCIE chip establish a communications link, determines that the detected state position of control register comprises the first mark, and described first mark is used for expression and forbids that described PCIE chip performs load detecting;
Transceiver, for performing the link negotiation flow process with described receiving terminal PCIE chip by optical transmission apparatus, to set up described communication connection with described receiving terminal PCIE chip.
6. PCIE chip according to claim 5, is characterized in that:
Described link state machine, also for when the message transmission rate that described PCIE chip and described receiving terminal PCIE chip are consulted in described link negotiation flow process reaches threshold value, determine that the balanced indicating bit of described control register comprises the second mark, wherein, described second mark is used for expression and forbids described PCIE chip and described receiving terminal PCIE chip negotiation signal parameter;
Described transceiver, also for according to configuration signal parameter by described communication connection to described receiving terminal PCIE chip transmission of data.
7. PCIE chip according to claim 6, is characterized in that, also comprise:
Manager, in system initialization process, configures described signal parameter.
8. the PCIE chip according to claim 6 or 7, is characterized in that, described signal parameter comprises at least one item in following parameter: transmitting terminal signal adjustment parameter or receiving end signal adjustment parameter.
9. quick peripheral component interconnected (PCIE) equipment, is characterized in that, comprises the PCIE chip as described in claim 5-8 any one.
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| PCT/CN2013/086563 WO2015066842A1 (en) | 2013-11-05 | 2013-11-05 | Communication method, peripheral component interconnect express (pcie) chip and pcie device |
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| CN106330300B (en) * | 2015-06-30 | 2018-11-27 | 菲尼萨公司 | Idle state detection circuit, idle state detection method and active optical fiber cable |
| CN106817258A (en) * | 2017-01-13 | 2017-06-09 | 郑州云海信息技术有限公司 | A kind of method and device chosen and verify PCIE link equalization parameters |
| CN107147399B (en) * | 2017-05-10 | 2020-11-27 | 北京兆芯电子科技有限公司 | Driver |
| US20190121763A1 (en) * | 2017-10-23 | 2019-04-25 | Mediatek Inc. | Method for communicating with another electronic device and associated electronic device |
| CN108040301B (en) * | 2017-11-30 | 2021-02-19 | 上海联影医疗科技股份有限公司 | Optical communication system, method and storage medium |
| CN107957885B (en) * | 2017-12-01 | 2021-02-26 | 麒麟软件有限公司 | PCIE link equipment standby and recovery method based on Feiteng platform |
| CN109495463B (en) * | 2018-11-02 | 2021-06-29 | 郑州云海信息技术有限公司 | Link width negotiation method, device and computer readable storage medium |
| CN111371582B (en) * | 2018-12-26 | 2021-04-16 | 大唐移动通信设备有限公司 | PCIE link fault processing method and device |
| US11836059B1 (en) | 2020-12-14 | 2023-12-05 | Sanblaze Technology, Inc. | System and method for testing non-volatile memory express storage devices |
| CN112463461B (en) * | 2020-12-17 | 2023-12-22 | 北京浪潮数据技术有限公司 | Link communication method, device, equipment and computer readable storage medium |
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