CN108809719B - Gigabit Ethernet interface interconnection method, communication device and storage medium - Google Patents
Gigabit Ethernet interface interconnection method, communication device and storage medium Download PDFInfo
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- CN108809719B CN108809719B CN201810604322.5A CN201810604322A CN108809719B CN 108809719 B CN108809719 B CN 108809719B CN 201810604322 A CN201810604322 A CN 201810604322A CN 108809719 B CN108809719 B CN 108809719B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/12—Neutralising, balancing, or compensation arrangements
Abstract
The embodiment of the invention provides a gigabit Ethernet interface interconnection method, communication equipment and a storage medium, and relates to the technical field of data communication. The method comprises the steps that after a first gigabit Ethernet interface is initialized, a first gigabit Ethernet interface is closed, a second gigabit Ethernet interface connected with the first gigabit Ethernet interface is initialized, the second gigabit Ethernet interface is configured to be in a mode of sending a pseudo random binary sequence PRBS code stream mode, and then the first gigabit Ethernet interface is opened, so that the first gigabit Ethernet interface can receive PRBS gigabit signals sent by the second gigabit Ethernet interface. Therefore, the problem that the tera chip receiver equalizer is subjected to a large number of probabilistic error messages caused by unsteady waveforms when the tera Ethernet interface chips are interconnected or the tera chip cannot communicate directly under severe conditions is solved.
Description
Technical Field
The invention relates to the technical field of data communication, in particular to a gigabit Ethernet interface interconnection method, communication equipment and a storage medium.
Background
In recent years, due to the explosion of big data, devices adopting a gigabit interface chip interconnection scheme are rapidly growing in an extremely vigorous demand. People put higher demands on the stability and adaptability of the equipment.
In order to avoid the influence of implementation difference on interconnection of different tera interface chips on link signals, the tera interface needs to be configured with parameters such as pre-emphasis and amplitude in the transmitting and receiving direction for adjustment. For the transmit direction, the parameter adjustment is usually performed in a software configuration manner, and for the receive direction, because of the unknown and compatibility existing between the chip interconnection, such as the attenuation of transmission media such as printed circuit boards, the signal intensity received by the chip has difference, therefore, the receiving end usually adopts the receiving automatic equalization technology to adjust, the receiving automatic equalization technology is that after the signal sent by the transmitting end tera interface chip is transmitted by the transmission medium such as the printed circuit board and the like, the receiving-end gigabit interface chip obtains a signal intensity calculation (Continuous Linear Equalization) value through an algorithm (judging the eye height of an eye pattern of a signal received by the receiving-end gigabit interface chip, and taking a proper value), and compensates attenuation of a gigabit signal through a transmission medium such as a printed circuit board, so that stable and reliable transmission of a gigabit interface is achieved.
Various gigabit interface-related protocols specify waveforms for which the gigabit interface transmits signals in a steady state (hereinafter referred to as steady state waveforms) (steady state waveforms, indicating that the "0" and "1" levels of a digital signal can be correctly transmitted). But in some cases results in a non-steady state waveform (a non-steady state waveform, which is a condition in which the "0" and "1" levels of the digital signal are disturbed). The unstable waveform is not forced by the specification to be not allowed when the tera interface chip is interconnected, so that the unstable waveform is an inherent characteristic of the tera interface chip interconnection. The problem can cause that a great number of error messages occur on the gigabit interface with a high probability or serious conditions directly cause that the gigabit interface chips cannot communicate in the operating scene of the gigabit interface chip interconnection.
Disclosure of Invention
The invention aims to provide a gigabit Ethernet interface interconnection method, communication equipment and a storage medium. The technical scheme adopted by the invention is as follows:
in a first aspect, an embodiment of the present invention provides a method for interconnecting gigabit ethernet interfaces, where the method includes: after a first gigabit Ethernet interface is initialized, executing a closing operation on the first gigabit Ethernet interface; after a second gigabit Ethernet interface connected with the first gigabit Ethernet interface is initialized, configuring the second gigabit Ethernet interface into a PRBS code stream mode for sending a pseudo random binary sequence; and performing an opening operation on the first gigabit Ethernet interface so that the first gigabit Ethernet interface receives a PRBS gigabit signal sent by the second gigabit Ethernet interface.
In this embodiment of the present application, after a first gigabit ethernet interface is initialized, after the first gigabit ethernet interface is turned off, a second gigabit ethernet interface connected to the first gigabit ethernet interface is initialized, the second gigabit ethernet interface is configured to send a pseudo random binary sequence PRBS code stream mode, and then the first gigabit ethernet interface is turned on, so that the first gigabit ethernet interface receives a PRBS gigabit signal sent by the second gigabit ethernet interface. Therefore, the problem that the tera chip receiver equalizer is subjected to a large number of probabilistic error messages caused by unsteady waveforms when the tera Ethernet interface chips are interconnected or the tera chip cannot communicate directly under severe conditions is solved.
Optionally, after the first gigabit ethernet interface is turned on so that the first gigabit ethernet interface receives the PRBS gigabit signal sent by the second gigabit ethernet interface, the method further includes: delaying a first preset time to enable the first gigabit Ethernet interface to automatically complete continuous linear equalization (CTLE); executing a closing operation on the second gigabit Ethernet interface; configuring the first gigabit Ethernet interface into a PRBS code stream mode; and performing an opening operation on the second gigabit Ethernet interface so that the second gigabit Ethernet interface receives the PRBS gigabit signal sent by the first gigabit Ethernet interface.
In the embodiment of the application, the problem that the tera chip receiver equalizer is probabilistically provided with a large number of error messages or the tera chip cannot communicate directly under severe conditions caused by unsteady waveforms when the tera Ethernet interface chips are interconnected is solved.
Optionally, after the second gigabit ethernet interface is turned on so that the second gigabit ethernet interface receives the PRBS gigabit signal sent by the first gigabit ethernet interface, the method further includes: delaying a second preset time to enable the second gigabit Ethernet interface to automatically complete continuous linear equalization (CTLE); and the first gigabit Ethernet interface is configured to be in a normal mode by removing the PRBS code stream mode, and the second gigabit Ethernet interface is configured to be in a normal mode by removing the PRBS code stream mode, so as to carry out data communication.
In the embodiment of the application, after the configuration of the first gigabit ethernet interface and the second gigabit ethernet interface is completed, the first gigabit ethernet interface and the second gigabit ethernet interface are ensured to be in normal communication, and no error message or gigabit interface down occurs.
Optionally, the configuring the first gigabit ethernet interface to transmit a PRBS code stream mode includes: setting a reference clock of a PRBS code stream sent by the first gigabit Ethernet interface as a local clock of a first gigabit chip, and configuring the second gigabit Ethernet interface into a mode of sending a pseudo random binary sequence PRBS code stream comprises: and setting a reference clock of a pseudo random binary sequence PRBS code stream sent by the second gigabit Ethernet interface as a local clock of a second gigabit chip.
In the embodiment of the application, the local clock of the tera chip is set as the reference clock of the corresponding PRBS code stream, so that the operation is simplified.
In a second aspect, an embodiment of the present invention provides a communication device, which includes a first terachip and a second terachip. The first gigabit Ethernet interface of the first gigabit chip is connected with the second gigabit Ethernet interface of the second gigabit chip. The communication device is configured to perform: after a first gigabit Ethernet interface is initialized, executing a closing operation on the first gigabit Ethernet interface; after a second gigabit Ethernet interface connected with the first gigabit Ethernet interface is initialized, configuring the second gigabit Ethernet interface into a PRBS code stream mode for sending a pseudo random binary sequence; and performing an opening operation on the first gigabit Ethernet interface so that the first gigabit Ethernet interface receives a PRBS gigabit signal sent by the second gigabit Ethernet interface.
In a third aspect, an embodiment of the present invention provides a storage medium, which stores program code, and when the program code is read and executed by a processor, the storage medium executes the above method.
The invention provides a gigabit Ethernet interface interconnection method, communication equipment and a storage medium, wherein the method comprises the steps of initializing a first gigabit Ethernet interface, closing the first gigabit Ethernet interface, initializing a second gigabit Ethernet interface connected with the first gigabit Ethernet interface, configuring the second gigabit Ethernet interface into a mode of sending a Pseudo Random Binary Sequence (PRBS) code stream mode, and further executing opening operation on the first gigabit Ethernet interface, so that the first gigabit Ethernet interface receives a PRBS gigabit signal sent by the second gigabit Ethernet interface. Therefore, the problem that the tera chip receiver equalizer is subjected to a large number of probabilistic error messages caused by unsteady waveforms when the tera Ethernet interface chips are interconnected or the tera chip cannot communicate directly under severe conditions is solved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a prior art solution provided by an embodiment of the present invention;
FIG. 2 is a schematic diagram of a second prior art solution provided by an embodiment of the present invention;
fig. 3 is a flowchart of a gigabit ethernet interface interconnection method according to an embodiment of the present invention;
fig. 4 is a block diagram of a communication device according to an embodiment of the present invention.
In the figure: 100-a communication device; 110-first gigabit chip; 120-second terachip; 130-transmission medium.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
The inventor of the present application finds that the prior art is as follows in the process of the embodiment of the present invention: the ten-gigabit interface chip receives the unsteady-state signal in the following three conditions:
the tera interface chip receives an unsteady state signal, and the unsteady state signal exists in three cases: firstly, in the initial power-on stage of a sending end chip, because an internal controller is in an uncontrolled state, a trillion interface of the sending end chip sends an unsteady-state signal; the second is that the chip has only a gigabit interface chip of a PCS layer, signals sent by the gigabit interface of the sending end chip are sent by encoding and decoding after input gigabit signals are recovered through a line, but if the input gigabit signals are not available, the gigabit interface of the chip sends unstable signals; thirdly, when the noise of the system mainboard is high, even if the sending-end tera-interface chip does not send signals, unsteady signals can exist in the noise.
The non-steady state waveforms in these three cases are allowed by the specification and cannot be eliminated. After receivers of part of the tera interface chips receive the tera unsteady waveforms, the receivers cannot distinguish the unsteady waveforms from the steady waveforms, so that an internal equalization algorithm of the receivers is abnormal, and the equalization capability can be automatically developed to be strongest. When the chip gigabit interface enters a controlled state, a steady-state waveform is sent, and the waveform does not need strong balancing capability in a chip receiver, so that the strongest balancing capability causes the chip receiver of the gigabit interface to be abnormal, a large amount of error messages occur probabilistically or serious conditions directly cause the chip gigabit interface to be incapable of communication.
The first technical scheme is as follows: referring to fig. 1, the equalization algorithm of the selective chip receiver may be adaptive to a gigabit interface chip, such as a gigabit chip 1 and a gigabit chip 2, where the equalization algorithm may be adaptive to refer to: the equalization algorithm of the chip receiver can continuously adjust the equalization capacity according to the received unsteady-state waveform and steady-state waveform, and the equalization capacity obtained after the steady-state waveform is received can meet the eye height requirement of the eye pattern in the chip receiver.
The first defect of the prior art is as follows: the method has great limitation on the selection of the tera interface chip, and the equalization algorithm of more chips cannot be self-adaptive from the viewpoint of chip type selection. This may result in the failure to select a suitable gigabit interface chip, which has a significant impact on the design flexibility of the device.
The second prior art scheme is: referring to fig. 2, a chip with an adaptive equalization algorithm, such as a Retimer chip, is added between the interconnection of the terachip 1 and the terachip 2.
The second defect of the prior art scheme is as follows: the chip with the self-adaptive equalization algorithm is added, so that the cost is increased, the number of the tera channels of the chip with the self-adaptive equalization algorithm is limited, and for a system with more tera interfaces, more chip designs need to be added, so that the design complexity of equipment is increased, and the reliability is reduced.
Therefore, the inventor of the present application proposes a gigabit ethernet interface interconnection method, a communication device, and a storage medium, so as to solve the problem that a gigabit interface chip cannot communicate directly due to a large number of probabilistic error messages or severe conditions caused by unsteady waveforms when an equalizer of a gigabit interface chip receiver is interconnected by the gigabit interface chip in an application scenario of a gigabit interface chip interconnection scheme device under the condition that the gigabit chip does not support a self-adaptive receiving automatic equalization function.
Referring to fig. 3, an embodiment of the present invention provides a method for interconnecting gigabit ethernet interfaces, where the method includes: step S300, step S310, and step S320.
Step S300: after a first gigabit Ethernet interface is initialized, the first gigabit Ethernet interface is executed with a shutdown operation.
For example, after the first gigabit ethernet interface is initialized, the first gigabit ethernet interface is executed (Shut Down), that is, a shutdown operation is performed.
Step S310: after a second gigabit Ethernet interface connected with the first gigabit Ethernet interface is initialized, the second gigabit Ethernet interface is configured to send a pseudo random binary sequence PRBS code stream mode.
Step S320: and performing an opening operation on the first gigabit Ethernet interface so that the first gigabit Ethernet interface receives a PRBS gigabit signal sent by the second gigabit Ethernet interface.
For example, the first gigabit ethernet interface is subjected to (No Shut Down) operation, that is, an opening operation is performed, so that the first gigabit ethernet interface receives the PRBS gigabit signal sent by the second gigabit ethernet interface.
In the present embodiment, PRBS: Pseudo-Random Binary Sequence, which is referred to as a Pseudo-Random code for short, is a Pseudo-Random Binary Sequence. Chip testing mainly uses pseudo random codes such as PRBS (pseudo random binary sequence) to test high-speed serial channels, mainly to test the bit error rate. The PRBS code pattern rate is matched with the rate of a chip interface, such as a tera interface, and the PRBS code pattern rate is also ten trillion. The PRBS has a Generator and a Checker in each of the first and second mega chips, and in this embodiment, a specific PRBS pattern is transmitted using the Generator function of the PRBS in each of the first and second mega chips.
In this embodiment of the present application, after a first gigabit ethernet interface is initialized, after the first gigabit ethernet interface is turned off, a second gigabit ethernet interface connected to the first gigabit ethernet interface is initialized, the second gigabit ethernet interface is configured to send a pseudo random binary sequence PRBS code stream mode, and then the first gigabit ethernet interface is turned on, so that the first gigabit ethernet interface receives a PRBS gigabit signal sent by the second gigabit ethernet interface. Therefore, the problem that the tera chip receiver equalizer is subjected to a large number of probabilistic error messages caused by unsteady waveforms when the tera Ethernet interface chips are interconnected or the tera chip cannot communicate directly under severe conditions is solved.
Optionally, after step S320, the method further includes:
delaying a first preset time to enable the first gigabit Ethernet interface to automatically complete continuous linear equalization (CTLE); executing a closing operation on the second gigabit Ethernet interface; configuring the first gigabit Ethernet interface into a PRBS code stream mode; and performing an opening operation on the second gigabit Ethernet interface so that the second gigabit Ethernet interface receives the PRBS gigabit signal sent by the first gigabit Ethernet interface.
The first preset time may be a time period in the order of microseconds (us). The second gigabit Ethernet interface is turned off, that is, the second gigabit Ethernet interface is turned on to perform power down operation, and the automatic equalization of the first gigabit Ethernet interface is not self-adaptive, so that the automatic equalization of the first gigabit Ethernet interface is not affected. Performing power up operation, namely opening operation, on the second gigabit Ethernet interface, so that the second gigabit Ethernet interface receives the PRBS gigabit signal sent by the first gigabit Ethernet interface
In the embodiment of the application, the problem that the tera chip receiver equalizer is probabilistically provided with a large number of error messages or the tera chip cannot communicate directly under severe conditions caused by unsteady waveforms when the tera Ethernet interface chips are interconnected is solved.
Optionally, after the second gigabit ethernet interface is turned on so that the second gigabit ethernet interface receives the PRBS gigabit signal sent by the first gigabit ethernet interface, the method further includes:
delaying a second preset time to enable the second gigabit Ethernet interface to automatically complete continuous linear equalization (CTLE); and the first gigabit Ethernet interface is configured to be in a normal mode by removing the PRBS code stream mode, and the second gigabit Ethernet interface is configured to be in a normal mode by removing the PRBS code stream mode, so as to carry out data communication.
In this embodiment, the second preset time may be a time period in the order of microseconds (us).
In the embodiment of the application, after the configuration of the first gigabit ethernet interface and the second gigabit ethernet interface is completed, the first gigabit ethernet interface and the second gigabit ethernet interface are ensured to be in normal communication, and no error message or gigabit interface shutdown occurs.
Optionally, the configuring the first gigabit ethernet interface to transmit a PRBS code stream mode includes: setting a reference clock of a PRBS code stream sent by the first gigabit Ethernet interface as a local clock of a first gigabit chip, and configuring the second gigabit Ethernet interface into a mode of sending a pseudo random binary sequence PRBS code stream comprises: and setting a reference clock of a pseudo random binary sequence PRBS code stream sent by the second gigabit Ethernet interface as a local clock of a second gigabit chip.
In the embodiment of the application, the local clock of the tera chip is set as the reference clock of the corresponding PRBS code stream, so that the operation is simplified.
The invention provides a gigabit Ethernet interface interconnection method, which comprises the steps of initializing a first gigabit Ethernet interface, closing the first gigabit Ethernet interface, initializing a second gigabit Ethernet interface connected with the first gigabit Ethernet interface, configuring the second gigabit Ethernet interface into a mode of sending a Pseudo Random Binary Sequence (PRBS) code stream mode, and further opening the first gigabit Ethernet interface so that the first gigabit Ethernet interface receives a PRBS gigabit signal sent by the second gigabit Ethernet interface. Therefore, the problem that the tera chip receiver equalizer is subjected to a large number of probabilistic error messages caused by unsteady waveforms when the tera Ethernet interface chips are interconnected or the tera chip cannot communicate directly under severe conditions is solved.
Referring to fig. 4, an embodiment of the invention provides a communication device 100 including a first terachip 110 and a second terachip 120. The first gigabit ethernet interface of the first gigabit chip 110 is connected to the second gigabit ethernet interface of the second gigabit chip 120. The communication device is configured to perform: after a first gigabit Ethernet interface is initialized, executing a closing operation on the first gigabit Ethernet interface; after a second gigabit Ethernet interface connected with the first gigabit Ethernet interface is initialized, configuring the second gigabit Ethernet interface into a PRBS code stream mode for sending a pseudo random binary sequence; and performing an opening operation on the first gigabit Ethernet interface so that the first gigabit Ethernet interface receives a PRBS gigabit signal sent by the second gigabit Ethernet interface.
Optionally, the communication device is further configured to perform: delaying a first preset time to enable the first gigabit Ethernet interface to automatically complete continuous linear equalization (CTLE); executing a closing operation on the second gigabit Ethernet interface; configuring the first gigabit Ethernet interface into a PRBS code stream mode; and performing an opening operation on the second gigabit Ethernet interface so that the second gigabit Ethernet interface receives the PRBS gigabit signal sent by the first gigabit Ethernet interface.
Optionally, the communication device is further configured to perform: delaying a second preset time to enable the second gigabit Ethernet interface to automatically complete continuous linear equalization (CTLE); and the first gigabit Ethernet interface is configured to be in a normal mode by removing the PRBS code stream mode, and the second gigabit Ethernet interface is configured to be in a normal mode by removing the PRBS code stream mode, so as to carry out data communication.
Optionally, the communication device is further configured to perform: and setting a reference clock of the PRBS code stream sent by the first gigabit Ethernet interface as a local clock of a first gigabit chip and setting a reference clock of the PRBS code stream sent by the second gigabit Ethernet interface as a local clock of a second gigabit chip.
The communication device 100 may also include a transmission medium 130. The first terachip 110 is connected to the second terachip via the transmission medium 130.
Alternatively, the transmission medium 130 may include, but is not limited to, a printed circuit board and a high speed connector. Physical signal connections for interconnections between the first terachip 110 and the second terachip 120 are realized. The printed circuit board and the high-speed connector can select different types of boards and connectors according to different communication equipment designs, the dielectric loss and the conductor loss of the boards and the connectors of different types are different, so that the attenuation amount of physical signals between the first gigabit chip and the second gigabit chip passing through the printed circuit board and the connectors is different, intersymbol interference (ISI) is introduced into the attenuation of the physical signals, the jitter of the physical signals is increased, the bandwidth is reduced, and the reliable transmission of the whole signals is influenced.
In the present embodiment, the first terachip 110 and the second terachip 120 implement a terabus interconnection through the transmission medium 130. As an embodiment, the first terachip 110 and the second terachip 120 may be chips having a self-management function, for example, the first terachip and the second terachip are CPU chips integrated with a tera interface.
As another implementation, the first terachip 110 and the second terachip 120 may also be chips without self-management, for example, the first terachip and the second terachip may be switch chips, PHY chips, etc., the communication device includes an external management chip for assisting management, the external management chip is connected to both the first terachip and the second terachip, the external management chip is used for managing the first terachip and the second terachip, and the content of management includes the initialization of the terachip, the opening and closing (NO Shut Down or Shut Down) management of a gigabit ethernet interface, the code pattern transmission of the PRBS, the delay function, etc.
Optionally, referring to fig. 4, the first gigabit chip 110 includes a first gigabit interface bus. The second terachip 120 includes a second tera interface bus. The first terabyte interface bus is connected with the second terabyte interface bus through the transmission medium.
In this embodiment, the first gigabit interface bus and the second gigabit interface bus each include KR and KR4, but are not limited thereto. The first terabyte interface bus and the second terabyte interface bus can be buses with any rate of more than ten trillion.
Referring to fig. 4, the first terachip 110 includes a transmitter TX1, and the second terachip 120 includes a receiver RX 2. The transmitter TX1 of the first terachip 110 transmits a signal to the receiver RX2 of the second terachip 120 through the transmission medium 130, and the receiver RX2 of the second terachip 120 compensates attenuation of the signal through the transmission medium by an automatic equalizer, so that the signal meets a preset index. Similarly, the process of transmitting signals from the transmitter TX2 of the second terachip 120 to the receiver RX1 of the first terachip 110 through the transmission medium is similar. The preset indexes, namely technical indexes defined by specifications, which are required to be met by signals received by the ten-gigabit interface chip receiver, include: amplitude, eye height, eye width, jitter, etc.
Referring to fig. 4, the first terachip 110 and the second terachip 120 each include receive auto-equalization. Taking the automatic Equalization of the reception of the second terachip 120 as an example, after the signal sent by the first terachip 110 is transmitted to the second terachip 120 through the transmission medium 130, the second terachip 120, based on the received signal, uses an algorithm, for example, to determine the eye height of the eye diagram of the received signal, takes an appropriate value, obtains a signal strength Calculation (CTLE) value, and compensates for the attenuation of the signal through the transmission medium, so as to achieve the stable and reliable transmission of the tera interface. In the actual operation of the equipment, transceivers of different terachips have certain difference, different transmission medium material characteristics have difference, the temperature of the equipment and the power supply slightly fluctuate, and the value of receiving automatic equalization ensures that the actual equipment obtains the optimal equalization value. The receiving automatic equalization function is divided into two types, one type is that the receiving automatic equalization can achieve whole-process self-adaptation, and the type is not considered in the scope of the embodiment; the other type is that the receiving automatic balance can not make the whole process self-adaptation, and the invention ensures the normal communication of the trillion interface under the condition, and can not have the condition of error messages or the down of the trillion interface.
Compared with the first prior art scheme shown in fig. 1, the communication device provided by the embodiment of the invention has the following beneficial effects: the flexibility of the equipment design is improved: the selection of the tera interface chip is free from constraint, whether the receiving automatic balance of the chip receiver supports self-adaptation is no longer a bottleneck, and the design flexibility of the equipment is no longer constrained in the aspect; reduction of material business risk: the selection of the tera interface chip is unconstrained, the business selection scope of materials is increased, and the control on the business risk of the materials is more controlled.
Compared with the second prior art scheme shown in fig. 2, the communication device provided by the embodiment of the present invention: the complexity of system design is reduced: chips with the self-adaptive capacity of the receiver are not required to be added when the ten-gigabit interface chips are interconnected; the cost is reduced: the trillion channels of the chip which can be self-adapted by the equalization algorithm are limited, and if the chip design is saved in each channel, the cost saved by the system is objective; the device reliability increases, i.e., chips decrease, and the corresponding peripheral circuits do not exist, the device reliability increases.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the communication device described above may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
An embodiment of the present invention provides a communication device 100, which includes a first terachip 110 and a second terachip 120. The first gigabit ethernet interface of the first gigabit chip 110 is connected to the second gigabit ethernet interface of the second gigabit chip 120. The communication device is configured to perform: after a first gigabit Ethernet interface is initialized, executing a closing operation on the first gigabit Ethernet interface; after a second gigabit Ethernet interface connected with the first gigabit Ethernet interface is initialized, configuring the second gigabit Ethernet interface into a PRBS code stream mode for sending a pseudo random binary sequence; and performing an opening operation on the first gigabit Ethernet interface so that the first gigabit Ethernet interface receives a PRBS gigabit signal sent by the second gigabit Ethernet interface. The problem that the receiving automatic equalization algorithm of the ten-gigabit chip cannot be self-adaptive is solved, so that the first ten-gigabit chip and the second ten-gigabit chip are interconnected and further communicate with each other.
An embodiment of the present invention provides a storage medium, which stores a program code, and when the program code is read and executed by a processor, the program code performs the above method.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A gigabit Ethernet interface interconnection method is characterized by comprising the following steps:
after a first gigabit Ethernet interface is initialized, executing a closing operation on the first gigabit Ethernet interface;
after a second gigabit Ethernet interface connected with the first gigabit Ethernet interface is initialized, configuring the second gigabit Ethernet interface into a PRBS code stream mode for sending a pseudo random binary sequence;
the first gigabit Ethernet interface is opened so that the first gigabit Ethernet interface receives a PRBS gigabit signal sent by the second gigabit Ethernet interface;
delaying a first preset time to enable the first gigabit Ethernet interface to automatically complete continuous linear equalization (CTLE);
executing a closing operation on the second gigabit Ethernet interface;
configuring the first gigabit Ethernet interface into a PRBS code stream mode;
the second gigabit Ethernet interface is opened so that the second gigabit Ethernet interface receives the PRBS gigabit signal sent by the first gigabit Ethernet interface;
delaying a second preset time to enable the second gigabit Ethernet interface to automatically complete continuous linear equalization (CTLE);
and the first gigabit Ethernet interface is configured to be in a normal mode by removing the PRBS code stream mode, and the second gigabit Ethernet interface is configured to be in a normal mode by removing the PRBS code stream mode, so as to carry out data communication.
2. The method of claim 1, wherein the configuring the first gigabit ethernet interface to transmit a PRBS codestream mode comprises: setting a reference clock of the PRBS code stream sent by the first gigabit Ethernet interface as a local clock of a first gigabit chip,
configuring the second gigabit ethernet interface to send a pseudo random binary sequence PRBS code stream pattern comprises: and setting a reference clock of a pseudo random binary sequence PRBS code stream sent by the second gigabit Ethernet interface as a local clock of a second gigabit chip.
3. A communication device comprising a first gigabit chip and a second gigabit chip, a first gigabit ethernet interface of the first gigabit chip being connected to a second gigabit ethernet interface of the second gigabit chip, the communication device being configured to perform:
after a first gigabit Ethernet interface is initialized, executing a closing operation on the first gigabit Ethernet interface;
after a second gigabit Ethernet interface connected with the first gigabit Ethernet interface is initialized, configuring the second gigabit Ethernet interface into a PRBS code stream mode for sending a pseudo random binary sequence;
the first gigabit Ethernet interface is opened so that the first gigabit Ethernet interface receives a PRBS gigabit signal sent by the second gigabit Ethernet interface;
delaying a first preset time to enable the first gigabit Ethernet interface to automatically complete continuous linear equalization (CTLE);
executing a closing operation on the second gigabit Ethernet interface;
configuring the first gigabit Ethernet interface into a PRBS code stream mode;
the second gigabit Ethernet interface is opened so that the second gigabit Ethernet interface receives the PRBS gigabit signal sent by the first gigabit Ethernet interface;
delaying a second preset time to enable the second gigabit Ethernet interface to automatically complete continuous linear equalization (CTLE);
and the first gigabit Ethernet interface is configured to be in a normal mode by removing the PRBS code stream mode, and the second gigabit Ethernet interface is configured to be in a normal mode by removing the PRBS code stream mode, so as to carry out data communication.
4. The communications device of claim 3, wherein the communications device is further configured to perform:
and setting a reference clock of the PRBS code stream sent by the first gigabit Ethernet interface as a local clock of a first gigabit chip and setting a reference clock of the PRBS code stream sent by the second gigabit Ethernet interface as a local clock of a second gigabit chip.
5. The communication device according to claim 3, wherein the first terachip comprises a transmitter, the second terachip comprises a receiver, the transmitter of the first terachip transmits a signal to the receiver of the second terachip through a transmission medium, and the receiver of the second terachip internally compensates attenuation of the signal through the transmission medium through an automatic equalizer so that the signal meets a preset index.
6. A computer-readable storage medium, characterized in that it stores a program code, which, when read and executed by a processor, performs the method according to claim 1 or 2.
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