CN112463461B - Link communication method, device, equipment and computer readable storage medium - Google Patents
Link communication method, device, equipment and computer readable storage medium Download PDFInfo
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- CN112463461B CN112463461B CN202011496038.4A CN202011496038A CN112463461B CN 112463461 B CN112463461 B CN 112463461B CN 202011496038 A CN202011496038 A CN 202011496038A CN 112463461 B CN112463461 B CN 112463461B
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000004891 communication Methods 0.000 title claims abstract description 26
- 238000012549 training Methods 0.000 claims abstract description 55
- 238000004590 computer program Methods 0.000 claims description 9
- 230000001276 controlling effect Effects 0.000 abstract 2
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 230000008569 process Effects 0.000 description 11
- 238000011144 upstream manufacturing Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000002222 downregulating effect Effects 0.000 description 3
- 238000011160 research Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a link communication method, a device, equipment and a computer readable storage medium, which are researched and found that under the condition that PCIe equipment and computer equipment are normally communicated, training of all links can be rapidly and accurately completed by controlling the enabling mode after disabling an uplink port of the PCIe equipment so that all links are normally communicated, therefore, the application firstly reduces the uplink port link width to reduce the number of links required to be trained, and after the number of links which are rapidly and downwards regulated are trained, the PCIe equipment and the computer equipment are normally communicated, all links of the uplink port of the PCIe equipment are rapidly completed by controlling the enabling mode after disabling the uplink port of the PCIe equipment, so that the PCIe equipment is rapidly put into use, and user experience and working efficiency are improved.
Description
Technical Field
The present invention relates to the field of computers, and in particular, to a link connection method, and a link connection apparatus, device, and computer readable storage medium.
Background
PCIe devices are of various types and can be flexibly connected to a CPU to expand functions of the computer device, where the PCIe devices may need to Reset certain registers of the PCIe devices due to anomalies and other reasons during operation, at this time, the CPU may control the PCIe devices to Reset in a Hot Reset mode to achieve the purpose, after the PCIe devices Reset, link training needs to be performed again between the CPU and the PCIe devices to achieve normal data interaction, but in this case, link training often needs a long time, so that PCIe devices cannot be put into use in time, user experience is affected, and working efficiency is reduced.
Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.
Disclosure of Invention
The invention aims to provide a link communication method, which enables PCIe equipment to be quickly put into use, and improves user experience and work efficiency; another object of the present invention is to provide a link connection device, a device and a computer readable storage medium, so that PCIe devices are quickly put into use, and user experience and work efficiency are improved.
In order to solve the technical problems, the present invention provides a link connection method, which includes:
when a host Reset requirement exists on a target PCIe device, the link width of an uplink port of the target PCIe device is adjusted down to be a preset width;
controlling the target PCIe device to perform Hot Reset operation;
and when the link with the preset width of the target PCIe device is trained, controlling the uplink port to be enabled after the uplink port is disabled, so that the target PCIe device retrains all links of the uplink port.
Preferably, after the uplink port is disabled, the link connection method further includes:
when the link training of the target PCIe equipment is finished, judging whether the link width after the training is consistent with the preset total link width of the uplink port of the target PCIe equipment;
if yes, the control prompter prompts the Hot Reset to trigger successfully.
Preferably, after the determining whether the link width after training is consistent with the preset total link width of the uplink port of the target PCIe device, the link connection method further includes:
if not, adding one to the failure times with the initial value of 1;
judging whether the failure times reach a preset threshold value or not;
if not, executing the step of enabling after the control of the uplink port is disabled;
if so, controlling the prompter to prompt the Hot Reset triggering failure.
Preferably, the prompter is a display.
Preferably, the preset width is X1.
Preferably, when the training of the link with the preset width of the target PCIe device is finished, the uplink port is controlled to be enabled after disabling, so that the target PCIe device retrains all links of the own uplink port specifically includes:
judging whether the link training of the preset width of the target PCIe device is carried out to an L0 stage within a preset duration;
if yes, controlling the uplink port to be enabled after being disabled, so that the target PCIe equipment retrains all links of the own uplink port;
after the determining whether the link training with the preset width of the target PCIe device is performed to the L0 stage, the link communicating method further includes:
if not, the control prompter prompts the connection overtime.
Preferably, the preset duration is 1s.
In order to solve the technical problem, the present invention further provides a link connection device, including:
the downlink adjustment module is used for adjusting the link width of the uplink port of the target PCIe device to be a preset width when the Hot Reset requirement exists on the target PCIe device;
the first control module is used for controlling the target PCIe equipment to carry out Hot Reset operation;
and the second control module is used for controlling the uplink port to be enabled after the uplink port is disabled when the link with the preset width of the target PCIe device is trained, so that the target PCIe device retrains all links of the uplink port.
In order to solve the technical problem, the present invention further provides a link connection device, including:
a memory for storing a computer program;
a processor for implementing the steps of the link communication method as described above when executing the computer program.
To solve the above technical problem, the present invention further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the link communication method as described above.
The invention provides a link communication method, in the link training process automatically carried out after the host Reset is carried out on PCIe equipment, the training of any link has higher error probability, and any continuous training failure triggers all links to be retrained, through research, the training of all links can be rapidly and accurately completed by controlling the enabling mode after the uplink port of the PCIe equipment is disabled under the condition that the PCIe equipment is normally communicated with computer equipment, so that all links are normally communicated, therefore, the method firstly adjusts the uplink port link width downwards, thereby reducing the number of links required to be trained, and after the number of the links which are adjusted downwards are rapidly trained, the PCIe equipment is enabled to be normally communicated with the computer equipment, all links of the uplink port of the PCIe equipment are rapidly completed by controlling the enabling mode after the uplink port of the PCIe equipment is disabled, thereby enabling the PCIe equipment to be rapidly put into use, and improving the user experience and the working efficiency.
The invention also provides a link communication device, equipment and a computer readable storage medium, which have the same beneficial effects as the link communication method.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a link connection method provided by the present invention;
fig. 2 is a schematic structural diagram of a link connection device according to the present invention;
fig. 3 is a schematic structural diagram of a link connection device according to the present invention.
Detailed Description
The core of the invention is to provide a link communication method, which enables PCIe equipment to be rapidly put into use, thereby improving user experience and working efficiency; another core of the present invention is to provide a link connection device, a device and a computer readable storage medium, so that PCIe devices are quickly put into use, thereby improving user experience and work efficiency.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a flow chart of a link connection method provided by the present invention, where the link connection method includes:
step S1: when the host Reset requirement exists in the target PCIe device, the link width of the uplink port of the target PCIe device is adjusted down to be a preset width;
specifically, after the PCIe device is controlled to perform the Hot Reset, the CPU automatically performs link training with the PCIe device (where the link is typically 2 n The method comprises the steps of performing a test on a host Reset, wherein the test is performed by using a host Reset, and the host Reset is performed by using a host Reset, wherein the host Reset is performed by using a host Reset, and the host Reset is performed by using a host Reset.
In order to shorten the link training process after the Hot Reset, the applicant thinks that the number of links required to be trained by the link training process after the Hot Reset can be reduced by downregulating the link width of the uplink port of the PCIe device, so as to accelerate the link training time after the Hot Reset.
Step S2: controlling the target PCIe device to perform Hot Reset operation;
specifically, after the link width is adjusted down, the target PCIe device can be controlled to perform the Hot Reset operation, so that the target PCIe device autonomously performs the Hot Reset under control and naturally performs negotiation of the communication link with the CPU.
The method comprises the steps that a CPU Root Complex initiates a Control target PCIe device to perform a Hot Reset operation by writing 1 into a Bridge Control register of the CPU, and then writing 0 into the Bridge Control register of the CPU after a delay period (for example, 2 ms) is needed, so that the Hot Reset is solved.
Step S3: and after the link training of the preset width of the target PCIe device is finished, controlling the uplink port to be enabled after the uplink port is disabled, so that the target PCIe device retrains all links of the uplink port.
Specifically, since the host Reset is already controlled by the target PCIe device in the foregoing step, only the link training process after the host Reset needs to be ended, and then all links of the uplink port of the PCIe device can be trained in a manner of "enabling after disabling the uplink port of the PCIe device" so that, in this step, when the link training of the preset width of the target PCIe device is finished, enabling after disabling the uplink port of the target PCIe device is controlled, so that all links of the uplink port of the target PCIe device can be retrained.
The control of the disable of the upstream port of the PCIe device may specifically be control of disable of the upstream port of the PCIe device, and the control of the enable of the upstream port of the PCIe device specifically may be control of enable of the upstream port of the PCIe device.
The invention provides a link communication method, in the link training process automatically carried out after the host Reset is carried out on PCIe equipment, the training of any link has higher error probability, and any continuous training failure triggers all links to be retrained, through research, the training of all links can be rapidly and accurately completed by controlling the enabling mode after the uplink port of the PCIe equipment is disabled under the condition that the PCIe equipment is normally communicated with computer equipment, so that all links are normally communicated, therefore, the method firstly adjusts the uplink port link width downwards, thereby reducing the number of links required to be trained, and after the number of the links which are adjusted downwards are rapidly trained, the PCIe equipment is enabled to be normally communicated with the computer equipment, all links of the uplink port of the PCIe equipment are rapidly completed by controlling the enabling mode after the uplink port of the PCIe equipment is disabled, thereby enabling the PCIe equipment to be rapidly put into use, and improving the user experience and the working efficiency.
Based on the above embodiments:
as a preferred embodiment, after the control of enabling the upstream port after disabling, the link connection method further includes:
when the link training of the target PCIe equipment is finished, judging whether the link width after the training is consistent with the preset total link width of the uplink port of the target PCIe equipment;
if yes, the control prompter prompts the Hot Reset to trigger successfully.
Specifically, considering that although the error probability of the enabling mode after the uplink port of the PCIe device is disabled is low, the normal operation of the PCIe device and the computer device is affected because the training is likely to fail or the preset total link width is not reached, the embodiment of the invention can judge whether the link width after the training is completed is consistent with the preset total link width of the uplink port of the target PCIe device itself after the link training of all links is controlled, and only if the link width is consistent with the preset total link width of the uplink port of the target PCIe device itself, the prompter is controlled to prompt that the Hot Reset is successfully triggered, thereby being convenient for a worker to ensure that all links are normally trained, and corresponding measures can be taken under the condition that the prompt is not received for a long time.
As a preferred embodiment, after determining whether the trained link width is consistent with the preset total link width of the uplink port of the target PCIe device, the link connection method further includes:
if not, adding one to the failure times with the initial value of 1;
judging whether the failure times reach a preset threshold value or not;
if not, executing the step of enabling after the control of the uplink port is disabled;
if so, the control prompter prompts the Hot Reset trigger failure.
Specifically, in order to automatically retrain under the inconsistent condition, in the embodiment of the invention, the uplink port of the PCIe device can be controlled to be enabled after being disabled again under the inconsistent condition, and in consideration of that the link training can not be completed no matter how many times the computer device and/or the PCIe device are in failure, the embodiment of the invention sets the preset threshold value of the failure times, so long as the preset threshold value is reached, the attempt can not be repeated any more, and the prompter is controlled to prompt the Hot Reset to trigger the failure, so that the staff can take corresponding measures in time.
As a preferred embodiment, the prompter is a display.
Specifically, the display has the advantages of high popularity, durable prompting effect and the like.
Of course, besides the display, the prompter may be of various other types, such as a short message prompt or a voice prompt, and the embodiment of the present invention is not limited herein.
As a preferred embodiment, the preset width is X1.
Specifically, in order to transition the link training process after the Hot Reset as soon as possible, the embodiment of the invention adjusts the link width down to X1, that is, only one link, so that after the Hot Reset is performed, the connection between the CPU and the PCIe device can be established by training the only one link, thereby facilitating the subsequent efficient training of all links in a mode of "controlling the enabling after disabling the uplink port of the PCIe device" and realizing the data communication between the CPU and the target PCIe device.
Of course, in addition to X1, the preset width may be less than the preset total link width and conform to 2 n The embodiments of the present invention are not limited herein.
As a preferred embodiment, when the link training of the preset width of the target PCIe device is finished, the control uplink port is enabled after disabling, so that the target PCIe device retrains all links of the own uplink port specifically includes:
judging whether link training of a preset width of target PCIe equipment is carried out to an L0 stage within a preset duration;
if yes, enabling the uplink port after disabling is controlled, so that the target PCIe equipment retrains all links of the uplink port;
after judging whether the link training with the preset width of the target PCIe device is carried out to the L0 stage, the link communication method further comprises the following steps:
if not, the control prompter prompts the connection overtime.
Specifically, when the target PCIe device performs Link training with a preset width, whether Link training is finished or not can be accurately determined by determining whether Link training with a preset width of the target PCIe device is performed to the L0 stage within a preset duration, and four processes, detect, polling, configuration and L0, are included in the Link training, wherein an abnormality in any process results in retraining of the PCIe Link, and further a longer time from Link to L0 is caused.
In consideration of the possible faults of the computer equipment and/or the target PCIe equipment, the probability that the link training after the link width is adjusted downwards is unsuccessful, and in order to cope with the situation, the invention sets the preset duration, and if the link after the link width is adjusted downwards can not be trained within the preset duration, the prompter can be controlled to prompt the connection overtime, so that staff can take measures in time.
Of course, in addition to the above manner, the method for determining whether the link training is completed may be of other various types, and the embodiment of the present invention is not limited herein.
As a preferred embodiment, the preset time period is 1s.
Specifically, the preset time length is set to be 1s, so that the link training can be ensured not to be repeated excessively, and the link training can be accurately judged to be completely unsuccessful.
Of course, the preset duration may be other specific values besides 1s, and embodiments of the present invention are not limited herein.
For better illustrating an embodiment of the present invention, please refer to fig. 2, fig. 2 is a schematic structural diagram of a link communication device provided by the present invention, the link communication device includes:
the downregulating module 1 is used for downregulating the link width of the uplink port of the target PCIe equipment to be a preset width when the Hot Reset requirement exists on the target PCIe equipment;
the first control module 2 is used for controlling the target PCIe device to perform Hot Reset operation;
and the second control module 3 is used for controlling the uplink port to be enabled after the uplink port is disabled when the link training of the preset width of the target PCIe device is completed, so that the target PCIe device retrains all links of the uplink port.
For the description of the link connection device provided in the embodiment of the present invention, reference is made to the foregoing embodiment of the link connection method, and the embodiment of the present invention is not repeated here.
For better explaining the embodiments of the present invention, please refer to fig. 3, fig. 3 is a schematic structural diagram of a link-communicating device provided by the present invention, where the link-communicating device includes:
a memory 4 for storing a computer program;
a processor 5 for implementing the steps of the link communicating method in the previous embodiment when executing the computer program.
For the description of the link connection device provided in the embodiment of the present invention, reference is made to the foregoing embodiment of the link connection method, and the embodiment of the present invention is not repeated herein.
The invention also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the method of uplink communication.
For the description of the computer readable storage medium provided in the embodiment of the present invention, reference is made to the foregoing embodiments of the link connection method, and the embodiments of the present invention are not repeated here.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A method of link communication, comprising:
when a target PCIe device has a Hot Reset requirement, the link width of an uplink port of the target PCIe device is adjusted down to be a preset width;
controlling the target PCIe device to perform Hot Reset operation;
when the link with the preset width of the target PCIe device is trained, controlling the uplink port to be enabled after the uplink port is disabled, so that the target PCIe device retrains all links of the uplink port;
when the link training of the preset width of the target PCIe device is finished, controlling the uplink port to be enabled after disabling, so that the target PCIe device retrains all links of the own uplink port specifically includes:
judging whether the link training of the preset width of the target PCIe device is carried out to an L0 stage within a preset duration;
if yes, training of all links is completed rapidly by controlling the enabling mode after disabling of the uplink port of the PCIe device so that all links communicate normally;
after the determining whether the link training with the preset width of the target PCIe device is performed to the L0 stage, the link communicating method further includes:
if not, the control prompter prompts the connection overtime.
2. The link communication method according to claim 1, wherein after said controlling said enabling after said disabling of said uplink port, the link communication method further comprises:
when the link training of the target PCIe equipment is finished, judging whether the link width after the training is consistent with the preset total link width of the uplink port of the target PCIe equipment;
if yes, the control prompter prompts the Hot Reset to trigger successfully.
3. The link-down method according to claim 2, wherein after determining whether the trained link width is consistent with the preset total link width of the uplink port of the target PCIe device, the link-down method further comprises:
if not, adding one to the failure times with the initial value of 1;
judging whether the failure times reach a preset threshold value or not;
if not, executing the step of enabling after the control of the uplink port is disabled;
if so, controlling the prompter to prompt the Hot Reset triggering failure.
4. A method of link communication according to claim 3, wherein the prompter is a display.
5. The link communication method according to claim 1, wherein the preset width is X1.
6. The link communication method according to claim 1, wherein the preset duration is 1s.
7. A link communication device, comprising:
the downlink adjustment module is used for adjusting the link width of the uplink port of the target PCIe device to be a preset width when the Hot Reset requirement exists on the target PCIe device;
the first control module is used for controlling the target PCIe equipment to carry out Hot Reset operation;
the second control module is used for controlling the uplink port to be enabled after the uplink port is disabled when the link with the preset width of the target PCIe device is trained, so that the target PCIe device retrains all links of the uplink port;
when the link training of the preset width of the target PCIe device is finished, controlling the uplink port to be enabled after disabling, so that the target PCIe device retrains all links of the own uplink port specifically includes:
judging whether the link training of the preset width of the target PCIe device is carried out to an L0 stage within a preset duration;
if yes, training of all links is completed rapidly by controlling the enabling mode after disabling of the uplink port of the PCIe device so that all links communicate normally;
after the determining whether the link training with the preset width of the target PCIe device is performed to the L0 stage, the link communicating apparatus further includes:
if not, the control prompter prompts the connection overtime.
8. A link-communicating device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the link communication method according to any one of claims 1 to 6 when executing said computer program.
9. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the link communication method according to any of claims 1 to 6.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011496038.4A CN112463461B (en) | 2020-12-17 | 2020-12-17 | Link communication method, device, equipment and computer readable storage medium |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011496038.4A CN112463461B (en) | 2020-12-17 | 2020-12-17 | Link communication method, device, equipment and computer readable storage medium |
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| CN112463461B true CN112463461B (en) | 2023-12-22 |
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| CN103797732A (en) * | 2013-11-05 | 2014-05-14 | 华为技术有限公司 | Communication method, peripheral component interconnect express (PCIE) chip and PCIE devices |
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| CN109844725A (en) * | 2016-07-01 | 2019-06-04 | 英特尔公司 | Asymmetric channel in point-to-point interconnection |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105205021B (en) * | 2015-09-11 | 2018-02-13 | 华为技术有限公司 | Disconnect the method and apparatus linked between PCIe device and main frame |
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2020
- 2020-12-17 CN CN202011496038.4A patent/CN112463461B/en active Active
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| CN103797732A (en) * | 2013-11-05 | 2014-05-14 | 华为技术有限公司 | Communication method, peripheral component interconnect express (PCIE) chip and PCIE devices |
| CN105407025A (en) * | 2015-11-27 | 2016-03-16 | 苏州中晟宏芯信息科技有限公司 | Method and device used for managing channel resources of high-speed serial link |
| CN109844725A (en) * | 2016-07-01 | 2019-06-04 | 英特尔公司 | Asymmetric channel in point-to-point interconnection |
Non-Patent Citations (1)
| Title |
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| 一种SoC芯片中PCIe接口的FPGA平台验证;刘娟;田泽;黎小玉;牛少平;;数字通信世界(第04期);全文 * |
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