CN103796429B - The manufacture method of circuit board - Google Patents
The manufacture method of circuit board Download PDFInfo
- Publication number
- CN103796429B CN103796429B CN201210429680.XA CN201210429680A CN103796429B CN 103796429 B CN103796429 B CN 103796429B CN 201210429680 A CN201210429680 A CN 201210429680A CN 103796429 B CN103796429 B CN 103796429B
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- copper
- conductive
- conductive copper
- foil layer
- circuit board
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 168
- 239000010410 layer Substances 0.000 claims abstract description 100
- 239000011889 copper foil Substances 0.000 claims abstract description 58
- 238000012360 testing method Methods 0.000 claims abstract description 52
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 229910052802 copper Inorganic materials 0.000 claims description 107
- 239000010949 copper Substances 0.000 claims description 107
- 238000012856 packing Methods 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 238000007747 plating Methods 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 239000010931 gold Substances 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 241001124569 Lycaenidae Species 0.000 claims description 7
- 235000014987 copper Nutrition 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 5
- 238000012546 transfer Methods 0.000 claims description 2
- 238000000465 moulding Methods 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 5
- 230000000007 visual effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The present invention relates to a kind of manufacture method of circuit board, which comprises the following steps：A basal plate is provided, there is the basal plate the first copper foil layer, insulating barrier and the second copper foil layer, first copper foil layer and second copper foil layer to be located at two opposite surfaces of the insulating barrier respectively；The basal plate includes product zone and non-product area, product zone is mutually corresponding with circuit board unit to be formed, non-product area is after circuit board molding, need removed region at least one test section of non-product area definition, and at least one test section is used for the interlayer offset distance in test product area.
Description
Technical field
The present invention relates to a kind of manufacture method of circuit board.
Background technology
Existing printed circuit board (PCB) is generally multiple structure, and which is formed by the pressing of multiple printed circuit veneers, due to pressure
There is mismachining tolerance during conjunction, the problem of skew between each orifice ring of multi-layer sheet conductor layer or between idle loop, occurs.And in pressure
How detecting the situation of offset distance between each printed circuit veneer after conjunction, to be always those skilled in the art insoluble
A difficult problem.In prior art, for two-ply, interlayer skew could be observed using section and by microscope, process is loaded down with trivial details；For
Multi-layer sheet, typically need to be observed interlayer skew, but this equipment price is expensive by X-ray equipment, and inspection software design is multiple
Miscellaneous, it is unfavorable for saving production cost.
Content of the invention
In view of above-mentioned condition, it is necessary to provide a kind of circuit board manufacturing method that can overcome the problems referred to above.
A basal plate is provided, the basal plate has the first copper foil layer, insulating barrier and the second copper foil layer, first copper foil layer
And second copper foil layer is located at two opposite surfaces of the insulating barrier respectively, the basal plate includes product zone and at least one test
Area, at least one test section are used for the interlayer offset distance in test product area；By the first copper foil layer system in the product zone
Make the first conducting wire of formation, second copper foil layer to make to form the second conducting wire；By being somebody's turn to do at least one test section
First copper foil layer is fabricated to the multiple conductive copper packing of M N array arrangement, and by second Copper Foil at least one test section
Layer is fabricated to multiple conductive coppers of M N array arrangement, and the first row conductive copper in the M rows is electrically connected by copper metal line,
The copper metal line extends to the insulating barrier edge and forms plating wiring, and the plurality of conductive copper packing is with the plurality of conductive copper one by one
Corresponding, the diameter of the conductive copper packing is less than the diameter of corresponding conductive copper, along the direction of conductive copper array arrangement,
Constant amplitude increases the diameter of the conductive copper successively；First through hole is formed at each in the conductive copper packing, and each first through hole is passed through
Wear the corresponding conductive copper packing, the intermediate insulating layer and the conductive copper, the equal diameters of each first through hole；To this
First through hole carries out the filling of conductive material to form the first via；And electrolysis plating is carried out to the conductive copper packing of the test section
Gold, the number being gold-plated by estimating the first row conduction copper packing on the test section in M rows show that in the product zone second leads
Offset distance of the electric line relative to first conducting wire.
Compared with prior art, the circuit board that the circuit board manufacturing method that the technical program is provided is fabricated to, including product
Area and non-product area, by one test section of non-product area definition, the first copper foil layer of test section being made arranged into an array
Conductive copper packing, the second copper foil layer of test section is made conductive copper arranged into an array, by the conductive copper to test section
Pad is electroplated, the number that the conductive copper packing on visual test section surface is gold-plated draw the second conducting wire of product zone with respect to
Skew in first line.Detection is finished removes non-product area, only leaves the product zone of client's needs, and method is simple, section
About cost.
Description of the drawings
The schematic diagram of the internal substrate that Fig. 1 is provided for the present invention.
Fig. 2 is profiles of the Fig. 1 along II-II directions.
Fig. 3 is the structure chart of the product zone that a surface of the internal substrate of Fig. 1 is fabricated to and test section.
Fig. 4 is the structure chart of the product zone that another surface of the internal substrate of Fig. 1 is fabricated to and test section.
Fig. 5 is profiles of the Fig. 3 along V-V directions.
Fig. 6 is to form the schematic diagram of first through hole on test section surface.
The sectional view of the circuit board 100 that Fig. 7 is fabricated to for first embodiment of the invention.
The sectional view of the circuit board 200 that Fig. 8 is fabricated to for second embodiment of the invention.
Fig. 9-11 is that the circuit board provided in Fig. 8 carries out interlayer offset distance test schematic diagram.
Main element symbol description
Circuit board 100,200
Internal substrate 10
First copper foil layer 11
Second copper foil layer 13
Insulating barrier 12
Product zone 101
Non-product area 102
Test section 103,1031
Conductive copper packing 110
Conductive copper 130
First conducting wire 111
Second conducting wire 112
First through hole 1101
First via 1102
Conductive material 1103
Copper metal line 1301
Plating wiring 1302
The second conducting wire of B1 layers 1121
The second conducting wire of B2 layers 1122
The second conducting wire of B3 layers 1123
Following specific embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Specific embodiment
One concrete introduction is made to the present invention below in conjunction with accompanying drawing.
A kind of manufacture method of circuit board 100, its manufacture method include step：
The first step, refers to Fig. 1 and Fig. 2, there is provided an internal substrate 10.The internal substrate 10 be with both sides conductive layer and
The structure of the insulating barrier composition being located between two conductive layers.In the present embodiment, internal substrate 10 is double-sided copper-clad substrate, and which includes
First copper foil layer 11, insulating barrier 12 and the second copper foil layer 13, first copper foil layer 11 and second copper foil layer 13 are located at respectively
Two opposite surfaces of the insulating barrier 12.
The internal substrate 10 includes product zone 101 and non-product area 102.Product zone 101 and circuit board unit to be formed
Mutually corresponding, non-product area 102 is to need removed region after circuit board molding.In the present embodiment, internal substrate 10
For rectangle, which includes a product zone 101, defines a test section 103 in the non-product area 102 of internal substrate 10.Should
Test section 103 is used for the interlayer offset distance in test product area, it will be understood that the number and position that the test section 103 is arranged can
To be set according to actual needs, the number of the test section 103 can be multiple.
Second step, sees also Fig. 3-5, and first copper foil layer 11 in the product zone 101 is made to form first and lead
Electric line 111, and second copper foil layer 13 is made to form the second conducting wire 112.Wherein, first conducting wire 111
It is to set according to the pattern being actually needed with second conducting wire 112.By first copper foil layer in the test section 103
The 11 multiple conductive copper packings 110 for being fabricated to M N array arrangement；Second copper foil layer 13 in the test section 103 is fabricated to M
Multiple conductive coppers 130 of × N array arrangement.Along the direction of 130 array of conductive copper arrangement, the conductive copper 130 straight
Constant amplitude increases successively in footpath.Wherein M represents line number, M 1, and N represents columns, N ＞ 1, but if needing the base in the circuit board 100
Continue to make multilayer circuit board on plinth, then the numerical value of the M is determined by the quantity of second copper foil layer 13, and N is more than 1.This is more
Individual conductive copper packing 110 is corresponded with the plurality of conductive copper 130；The diameter of the conductive copper packing 110 is led less than corresponding
The diameter of electrolytic copper ring 130.
Electrically connected by copper metal line 1301 between the first row conductive copper 130 in the M rows, and the copper metal line 1301
Extend to 13 edge of the second copper foil layer and form plating wiring 1302.
3rd step, refers to Fig. 6, forms first through hole 1101 using laser at each in the conductive copper packing 110, and this first
Through hole 1101 runs through the conductive copper packing 110, the intermediate insulating layer 12 and the conductive copper 130.The circle of each conductive copper packing 110
The center of circle place straight line of the heart and each corresponding first through hole 1101 is perpendicular to the insulating barrier 12.Along the conductive copper
The direction of 130 arrays arrangement, the diameter of each first through hole 1101 are equal.Due to above-mentioned when conductive copper 130 is made,
Along the direction of 130 array of conductive copper arrangement, constant amplitude increases the diameter of the conductive copper 130 successively, thus herein this first
Constant amplitude increases the internal diameter of through hole 1101 and the conductive copper 130 successively.
In present embodiment, N=6.The value of N can be designed according to actual needs in other embodiments.Numerical value by N
It is set as 6, the columns for just representing conductive copper packing 110 and conductive copper 130 is 6 row.The ideally circuit shown in Fig. 6
Situation without skew between flaggy.Now, the first through hole 1101 and the distance between the internal ring of conductive copper 130 A1、A2、A3、
A4、A5、A6It is respectively set as 45mm, 50mm, 55mm, 60mm, 65mm, 70mm.In other embodiments, the first through hole
1101 can also be designed with size according to being actually needed for circuit board with the distance between 130 internal ring of conductive copper.
4th step, refers to Fig. 7, Fig. 7 be shown that to carry out the first through hole 1101 filling of conductive material 1103 with
Form the first via 1102.The conductive material 1103 is generally the conductive materials such as copper cream, gold, stannum.This is basically completed the electricity
The circuit Making programme of road plate 100.
5th step, is detected come the interlayer offset distance to circuit board 100 using test section 103, and specifically, detection should
Offset distance of second conducting wire 112 relative to first conducting wire 111.Need to provide electroplanting device herein to the test section
The conductive copper packing 110 on 103 surfaces is electroplated.Wherein, the plating wiring 1302 of the circuit board frontside edge is electroplanting device
Access point.By estimate that the first row conduction copper packing 110 on the test section 103 of the circuit board 100 in M rows is gold-plated
Number draws offset distance of second conducting wire 112 in the product zone 101 relative to first conducting wire 111.
Specifically, first assume that second conducting wire 112 is L relative to the offset distance of first conducting wire 111, when
L ＜ A1When, the first via 1102 of the first row will not contact conducting with the conductive copper 130 of same column, so as to this first
The conductive copper packing 110 of row will not be coated with gold；Work as A1＜ L ＜ A2When, this of the first via 1102 of the first row and same column is led
The contact conducting of electrolytic copper ring 130, so as to the conductive copper packing 110 of the first row can be gold-plated；Work as A2＜ L ＜ A3, the first of the first row
First via 1102 of via 1102 and the secondary series is contacted respectively and with the conductive copper 130 of its same column and is led
Logical, first row can be gold-plated with the conductive copper packing 110 of secondary series immediately, in the same manner, as L ＞ A6When, the conductive copper packing 110 of 6 row
Can plated with gold, then represent offset distance L more than 70mm.
So, conducting wire on the circuit board 100 can just be immediately arrived at according to the number that the conductive copper packing 110 is gold-plated
Interlayer offset distance.The offset distance detection of the circuit board 100 is finished, test section can be removed, and leave behind client's needs
Product zone 101, can be different grades according to offset distance by 100 points of circuit board in this approach.
The invention further relates to a kind of method for making multilayer circuit board 200 on the basis of the circuit board 100.Concrete bag
Include：One circuit board as above 100 is provided, and P layer insulatings 12 and P is sequentially formed on the surface of second conducting wire 112
The second copper foil layer 13 of layer, wherein, the insulating barrier 12 is with second copper foil layer 13 successively separately.Herein due to the conductive copper packing
110 is gold-plated for visual detection, it is impossible to is covered by insulating barrier or copper foil layer.So when needing to make multilayer circuit board, it should
Increase insulating barrier 12 and copper foil layer 13 and making conducting wire on copper foil layer 13 on the surface of second conducting wire 112.
The second copper foil layer of Pi layers in the product zone 101 is formed the second conducting channel of Pi layers 112, by the test section 103
In the second copper foil layer of Pi layers be fabricated to M N array arrangement multiple conductive coppers 130, wherein, M, N, i, P be natural number, M
=P+1；N 1, i 1.For second copper foil layer of Pi layers 13 in second copper foil layer of P layers 13, in the M row conductive coppers
Electrically connected by the copper metal line 1301 between the conductive copper of i+1 row, the copper metal line 1301 extend to the Pi layers this
Two copper foil layers, 13 edge and formed plating wiring 1302.
The above-mentioned first through hole 1101 is extended and extends through the internal substrate 10, the second bronze medal of P layer insulatings 12 and P layers
Layers of foil 13.The center of circle place straight line of the center of circle of each conductive copper packing 110 and each corresponding first through hole 1101 hangs down
Directly in the insulating barrier 12.In present embodiment, the conductive copper packing 110, the conductive copper 130, first conducting wire 111 with
And second conducting wire 112 is formed using image transfer technique and etch process simultaneously.Finally to the first through hole 1101
The filling of conductive material 1103 is carried out, to form first via 1102.
In order to briefly describe the structure of the multilayer circuit board 200, P=2 is made herein, in other embodiments, can be with root
According to being actually needed the number of plies of carrying out initialization circuit plate.
Fig. 8 be shown that P=2 in the case of circuit board 200, Fig. 9-11 is shown that the test section of the circuit board 200
1031 structure diagram.The test section 1301 eliminates conducting wire in order to be able to clearly show the concrete grammar of test, Fig. 9-11
Between insulating barrier 12, and in order to be able to clearly describe the skew between conducting wire, Fig. 9-11 is by each line of test section in Fig. 8
The conductive copper 130 of array arrangement that should be opposite with conductive copper packing 110 on the floor of road is all disposed within direction in the diagram should
The Copper Foil layer surface that conductive copper packing 110 is located.This has no effect on the description of test effect.
As, in the manufacturing process of specific boards 200, second conducting wire of each layer 112 of product zone 101 all exists
Test section is provided with the conductive ring 130 of the array arrangement for testing 112 offset distance of the second conducting wire of this layer.Here
The circuit board 200 for convenience of explanation, will be provided with the second conducting wire 112 that conductive ring 130 is located and is respectively designated as B1
The second conducting wire 1121 of layer, the second conducting wire of B2 layers 1122, the second conducting wire of B3 layers 1123.It is appreciated that the B1 layers
Second conducting wire 1121 is the second conducting wire 112 of the circuit board 100, second conducting wire of B2 layers 1122 and should
The second conducting wire of B3 layers 1123 is to press second copper foil layer 12 on the basis of circuit board 100 and design forming.
As previously mentioned, for second copper foil layer of Pi layers 13 in second copper foil layer of P layers 13, in the M row conductive coppers
I+1 row the conductive copper 130 between electrically connected by the copper metal line 1301.Incorporated by reference to Fig. 9-11, for the B1 layers
Second conducting wire 1121, is connected by copper metal line 1301 between the first row conductive ring 130 and extends to the circuit board
200 edges form plating wiring 1302；For passing through between the 1122, the 2nd row conductive ring 130 of the second conducting wire of B2 layers
Copper metal line 1301 connects and extends to 200 edge of circuit board formation plating wiring 1302；The 3rd row conductive ring 130
Between connected by copper metal line 1301 and extend to 200 edge of circuit board and form the plating wiring 1302.
When each layer of the skew of second conducting wire 112 is tested, the plating at 200 each layers of edge of circuit board
Wiring 1302 is the access point of electroplanting device, and then the conductive copper packing 110 on 200 surface of circuit board is electroplated, and observation should
The situation that the conductive copper packing 110 on 200 surface of circuit board is gold-plated can just learn that the second conducting wire of the circuit board 200 is relative
Skew in first conducting wire.
Compared with prior art, the circuit board that the circuit board manufacturing method that the technical program is provided is fabricated to, including product
Area and non-product area, by one test section of non-product area definition, the first copper foil layer of test section being made arranged into an array
Conductive copper packing, the second copper foil layer of test section is made conductive copper arranged into an array, by the conductive copper to test section
Pad is electroplated, the number that the conductive copper packing on visual test section surface is gold-plated draw the second conducting wire of product zone with respect to
Skew in first line.Method is simple, cost-effective.
In addition, those skilled in the art can also do other changes in spirit of the invention, certainly, these are according to present invention essence
The change done by god, should all be included in scope of the present invention.
Claims (9)
1. a kind of manufacture method of circuit board, including step：
One basal plate is provided, the basal plate have the first copper foil layer, insulating barrier and the second copper foil layer, first copper foil layer and should
Second copper foil layer is located at two opposite surfaces of the insulating barrier respectively, and the basal plate includes product zone and at least one test section, should
At least one test section is used for the interlayer offset distance in test product area；
First copper foil layer in the product zone is made and to be formed the first conducting wire, second copper foil layer and is made to form second and lead
Electric line；
The multiple conductive copper packing that first copper foil layer at least one test section is fabricated to M N array arrangement, and should
Second copper foil layer at least one test section is fabricated to multiple conductive coppers of M N array arrangement, first in the M rows
Row conductive copper is electrically connected by copper metal line, and the copper metal line extends to the insulating barrier edge and forms plating wiring, and this is more
Individual conductive copper packing is corresponded with the plurality of conductive copper, and the diameter of the conductive copper packing is straight less than corresponding conductive copper
Footpath, along the direction of the conductive copper array arrangement, constant amplitude increases the diameter of the conductive copper successively；
First through hole is formed at each in the conductive copper packing, and each first through hole runs through the corresponding conductive copper packing, is somebody's turn to do
Insulating barrier and the conductive copper, the equal diameters of each first through hole；The first through hole is carried out the filling of conductive material with
Form the first via；
And electrolytic gold plating is carried out to the conductive copper packing of the test section, by estimating the first row conductive copper on the test section in M rows
Offset distance of the second conducting wire that the number that pad is gold-plated is drawn in the product zone relative to first conducting wire.
2. circuit board manufacturing method as claimed in claim 1, it is characterised in that：Pressed in the side of second conducting wire successively
Conjunction forms the second copper foil layer of P layer insulatings and P layers, wherein, insulating barrier and the second copper foil layer successively separately, and by the product zone
In the second copper foil layer of P layers in each second copper foil layer Pi form second conducting channel, by the P at least one test section
Each second copper foil layer Pi in the second copper foil layer of layer is fabricated to multiple conductive coppers of M N array arrangement, the plurality of conductive pad
Correspond with the plurality of conductive copper, wherein, M, N, i, P are natural number；M=P+1；N 1, i 1.
3. circuit board manufacturing method as claimed in claim 2, it is characterised in that：Extending the first through hole passes through the first through hole
Wear the basal plate, P layer insulatings and P layer copper foil layers.
4. circuit board manufacturing method as claimed in claim 3, it is characterised in that：The first through hole filling conductive material is formed
First via.
5. the manufacture method of circuit board as claimed in claim 1 or 2, it is characterised in that：The conductive copper packing, conductive copper,
One conducting wire and the second conducting wire are formed simultaneously using image transfer technique and etch process.
6. the manufacture method of circuit board as claimed in claim 2, it is characterised in that：I+1 row on the Pi layers in M rows is led
Electrically connected by copper metal line between electrolytic copper ring, the copper metal line extends to the second copper foil layer edge and forms plating wiring.
7. the manufacture method of circuit board as claimed in claim 1, it is characterised in that：Side along the conductive copper pad array arrangement
To the diameter of the conductive copper packing is equal.
8. the manufacture method of circuit board as claimed in claim 1, it is characterised in that：The detection of the offset distance of the circuit board
Method is：Internal ring of the direction that along the conductive copper arrange, the first through hole and the conductive copper the distance between point is first set
Wei not A1、A2、A3、A4、A5、……、An、An+1, second conducting wire is L relative to the offset distance of first conducting wire；
As L ＜ A1When, M N array arrangement first row first via and conducting will not be contacted with the conductive copper of its same column,
So as to the conductive copper packing of the first row will not be coated with gold；Work as A1＜ L ＜ A2When, the first via of the first row and same column
The conductive copper contact conducting, the conductive copper inwall of the row can be coated with gold, so as to the conductive copper packing of the first row can be plated
Gold；Work as A2＜ L ＜ A3, first via of first via and secondary series of the first row respectively and with its same column should
Conductive copper contact conducting, so as to conductive copper packing of the first row with the secondary series can be gold-plated, in the same manner, as L ＞ An+1When, n+1
The conductive copper packing of row can plated with gold, then represent offset distance L more than An+1.
9. the manufacture method of circuit board as claimed in claim 8, it is characterised in that：An+1With AnBetween difference be certain value.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210429680.XA CN103796429B (en) | 2012-11-01 | 2012-11-01 | The manufacture method of circuit board |
| TW101142285A TW201419971A (en) | 2012-11-01 | 2012-11-13 | Method of manufacturing circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210429680.XA CN103796429B (en) | 2012-11-01 | 2012-11-01 | The manufacture method of circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103796429A CN103796429A (en) | 2014-05-14 |
| CN103796429B true CN103796429B (en) | 2017-03-15 |
Family
ID=50671558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210429680.XA Active CN103796429B (en) | 2012-11-01 | 2012-11-01 | The manufacture method of circuit board |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103796429B (en) |
| TW (1) | TW201419971A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108648639B (en) * | 2018-06-07 | 2024-05-24 | 江西兴泰科技股份有限公司 | COG segment code display substrate and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001358464A (en) * | 2000-06-15 | 2001-12-26 | Nippon Avionics Co Ltd | Build-up printed-wiring board and its manufacturing method |
| CN101212896A (en) * | 2006-12-27 | 2008-07-02 | 株式会社东芝 | Method of inspecting printed wiring board and printed wiring board |
| CN102098884A (en) * | 2010-12-29 | 2011-06-15 | 北大方正集团有限公司 | Standard laminated plate and manufacturing method thereof |
| CN102548249A (en) * | 2010-12-13 | 2012-07-04 | 富葵精密组件(深圳)有限公司 | Manufacturing method of circuit boards |
| CN102612266A (en) * | 2011-01-21 | 2012-07-25 | 富葵精密组件(深圳)有限公司 | Manufacturing method of circuit board |
-
2012
- 2012-11-01 CN CN201210429680.XA patent/CN103796429B/en active Active
- 2012-11-13 TW TW101142285A patent/TW201419971A/en unknown
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001358464A (en) * | 2000-06-15 | 2001-12-26 | Nippon Avionics Co Ltd | Build-up printed-wiring board and its manufacturing method |
| CN101212896A (en) * | 2006-12-27 | 2008-07-02 | 株式会社东芝 | Method of inspecting printed wiring board and printed wiring board |
| CN102548249A (en) * | 2010-12-13 | 2012-07-04 | 富葵精密组件(深圳)有限公司 | Manufacturing method of circuit boards |
| CN102098884A (en) * | 2010-12-29 | 2011-06-15 | 北大方正集团有限公司 | Standard laminated plate and manufacturing method thereof |
| CN102612266A (en) * | 2011-01-21 | 2012-07-25 | 富葵精密组件(深圳)有限公司 | Manufacturing method of circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103796429A (en) | 2014-05-14 |
| TW201419971A (en) | 2014-05-16 |
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