CN103796429A - Method for manufacturing circuit board - Google Patents
Method for manufacturing circuit board Download PDFInfo
- Publication number
- CN103796429A CN103796429A CN201210429680.XA CN201210429680A CN103796429A CN 103796429 A CN103796429 A CN 103796429A CN 201210429680 A CN201210429680 A CN 201210429680A CN 103796429 A CN103796429 A CN 103796429A
- Authority
- CN
- China
- Prior art keywords
- copper
- foil layer
- circuit board
- copper foil
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims abstract description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 172
- 239000010410 layer Substances 0.000 claims abstract description 106
- 239000011889 copper foil Substances 0.000 claims abstract description 62
- 238000012360 testing method Methods 0.000 claims abstract description 52
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 229910052802 copper Inorganic materials 0.000 claims description 118
- 239000010949 copper Substances 0.000 claims description 118
- 238000012856 packing Methods 0.000 claims description 46
- 239000002184 metal Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 14
- 238000007747 plating Methods 0.000 claims description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 9
- 150000001879 copper Chemical class 0.000 claims description 8
- 238000003825 pressing Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000001514 detection method Methods 0.000 claims description 3
- 238000012546 transfer Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 230000000007 visual effect Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Images
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention relates to a method for manufacturing a circuit board. The method comprises providing a base plate, wherein the base plate has a first copper foil layer, an insulation layer and a second copper foil layer. The first copper foil layer and the second copper foil layer are arranged on the two opposite surfaces of the insulation layer respectively. The base plate comprises a product area and a non-product area, wherein the product area is mutually corresponding to a circuit board unit to be formed; and the non-product area is the area needing to be removed after the circuit board is formed. At least one test area is defined in the non-product area, and the at least one test area is used for testing interlayer offset distance of the product area.
Description
Technical field
The present invention relates to a kind of manufacture method of circuit board.
Background technology
Existing printed circuit board (PCB) is generally sandwich construction, and it is to be formed by the pressing of multiple printed circuit veneer, has mismachining tolerance during due to pressing, between each orifice ring of multi-layer sheet conductor layer or and idle loop between there will be the problem of skew.And the situation that how to detect the offset distance between each printed circuit veneer after pressing is the insoluble difficult problems of those skilled in the art always.In prior art, for two-ply, adopt section and could observe interlayer skew by microscope, process is loaded down with trivial details; For multi-layer sheet, generally need observe interlayer skew by X-ray equipment, but this equipment price costliness, and detect Software for Design complexity, be unfavorable for saving production cost.
Summary of the invention
In view of above-mentioned condition, be necessary to provide a kind of circuit board manufacturing method that can overcome the problems referred to above.
One basal plate is provided, this basal plate has the first copper foil layer, insulating barrier and the second copper foil layer, this first copper foil layer and this second copper foil layer lay respectively at two opposing surfaces of this insulating barrier, this basal plate comprises product zone and at least one test section, and this at least one test section is used for the interlayer offset distance in test products district, this first copper foil layer in this product zone is made and formed the first conducting wire, this second copper foil layer making formation, second conducting wire, this first copper foil layer in this at least one test section is made into multiple conduction copper packings of M × N arrayed, and this second copper foil layer in this at least one test section is made into multiple conductive copper of M × N arrayed, the first row conductive copper during this M is capable is electrically connected by copper metal line, this copper metal line extends to this inner plating edge and forms plating wiring, the plurality of conduction copper packing is corresponding one by one with the plurality of conductive copper, the diameter of this conduction copper packing is less than the diameter of the conductive copper corresponding with it, along the direction of this conductive copper arrayed, the diameter of this conductive copper successively constant amplitude increases, in each conduction copper packing, form the first through hole, this first through hole runs through this first conductive pad, this intermediate insulating layer and this conductive copper, the equal diameters of this each the first through hole, this first through hole is carried out to the filling of electric conducting material to form this first via, and the conduction copper packing of this test section is carried out to electrolytic gold plating, draw the second conducting wire in this product zone offset distance with respect to this first conducting wire by estimating the number of the plated gold of the first row conduction copper packing in capable of M on this test section.
Compared with prior art, the circuit board that the circuit board manufacturing method that the technical program provides is made into, comprise Yu Fei product zone, product zone, by defining a test section in non-product zone, the first copper foil layer of test section is made into the conduction copper packing of arrayed, the second copper foil layer of test section is made into the conductive copper of arrayed, electroplate by the conduction copper packing to test section, the number of the plated gold of conduction copper packing on surface, visual test section show that the second conducting wire of product zone is with respect to the skew of the first circuit.Detect the complete non-product zone of removing, only leave the product zone that client needs, method is simple, cost-saving.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of internal substrate provided by the invention.
Fig. 2 is the profile of Fig. 1 along II-II direction.
Fig. 3 is the product zone that is made into, a surface of the internal substrate of Fig. 1 and the structure chart of test section.
Fig. 4 is the product zone that is made into, another surface of the internal substrate of Fig. 1 and the structure chart of test section.
Fig. 5 is the profile of Fig. 3 along V-V direction.
Fig. 6 is the schematic diagram that forms the first through hole on surface, test section.
Fig. 7 is the sectional view of the circuit board 100 that is made into of first embodiment of the invention.
Fig. 8 is the sectional view of the circuit board 200 that is made into of second embodiment of the invention.
Schematic diagram is tested for the circuit board providing in Fig. 8 carries out interlayer offset distance in Fig. 9-11.
Main element symbol description
| |
100、200 |
| |
10 |
| The first |
11 |
| The second |
13 |
| |
12 |
| |
101 |
| |
102 |
| |
103、1031 |
| |
110 |
| |
130 |
| The first conducting |
111 |
| The second conducting |
112 |
| The first through |
1101 |
| The first via | 1102 |
| Electric conducting |
1103 |
| |
1301 |
| |
1302 |
| B1 layer the second conducting |
1121 |
| B2 layer the second conducting |
1122 |
| B3 layer the second conducting |
1123 |
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Below with embodiment and by reference to the accompanying drawings to circuit board manufacturing method further description provided by the invention.
A manufacture method for circuit board 100, its manufacture method comprises step:
The first step, refers to Fig. 1 and Fig. 2, and an internal substrate 10 is provided.This internal substrate 10 is for having the structure of both sides conductive layer and the composition of the insulating barrier between two conductive layers.In the present embodiment, internal substrate 10 is double-sided copper-clad substrate, and it comprises the first copper foil layer 11, insulating barrier 12 and the second copper foil layer 13, and this first copper foil layer 11 and this second copper foil layer 13 lay respectively at two opposing surfaces of this insulating barrier 12.
This internal substrate 10 comprises 101Ji Fei product zone, product zone 102.Product zone 101 is mutually corresponding with circuit board unit to be formed, and non-product zone 102 for needing removed region after circuit board molding.In the present embodiment, internal substrate 10 is rectangle, and it includes a product zone 101, defines a test section 103 in the non-product zone 102 of internal substrate 10.This test section 103 is used for the interlayer offset distance in test products district, is appreciated that number and position that this test section 103 arranges can set according to actual needs, and the number of this test section 103 can be multiple.
Second step, sees also Fig. 3-5, this first copper foil layer 11 in this product zone 101 is made and is formed the first conducting wire 111, and this second copper foil layer 13 is made and formed the second conducting wire 112.Wherein, this first conducting wire 111 is all to set according to the pattern of actual needs with this second conducting wire 112.This first copper foil layer 11 in this test section 103 is made into multiple conduction copper packings 110 of M × N arrayed; This second copper foil layer 13 in this test section 103 is made into multiple conductive copper 130 of M × N arrayed.Along the direction of these conductive copper 130 arrayed, the diameter of this conductive copper 130 successively constant amplitude increases.Wherein M represents line number, M≤1, and N represents columns, N > 1, if but need on the basis of this circuit board 100, continue to make multilayer circuit board, the numerical value of this M is determined by the quantity of this second copper foil layer 13, N is greater than 1.The plurality of conduction copper packing 110 is corresponding one by one with the plurality of conductive copper 130; The diameter of this conduction copper packing 110 is less than the diameter of the conductive copper corresponding with it 130.
Between the first row conductive copper 130 during this M is capable, be electrically connected by copper metal line 1301, and this copper metal line 1301 extends to these the second copper foil layer 13 edges and forms plating wiring 1302.
The 3rd step, refers to Fig. 6, in each this conduction copper packing 110, utilizes laser to form the first through hole 1101, and this first through hole 1101 runs through this conduction copper packing 110, this intermediate insulating layer 12 and this conductive copper 130.Place, the center of circle straight line of the center of circle of each this conduction copper packing 110 and each this first through hole 1101 corresponding with it is perpendicular to this insulating barrier 12.Along the direction of these conductive copper 130 arrayed, the diameter of each this first through hole 1101 all equates.Due to above-mentioned, making when conductive copper 130, along the direction of these conductive copper 130 arrayed, the diameter of this conductive copper 130 successively constant amplitude increases, thus herein the internal diameter of this first through hole 1101 and this conductive copper 130 successively constant amplitude increase.
In present embodiment, N=6.The value of N can design according to actual needs in other embodiments.Be 6 by the setting value of N, be 6 row with regard to the columns of representative conduction copper packing 110 and conductive copper 130.Situation without skew between board layer under the perfect condition showing in Fig. 6.Now, the distance A between this first through hole 1101 and the interior ring of conductive copper 130
1, A
2, A
3, A
4, A
5, A
6be set as respectively 45mm, 50mm, 55mm, 60mm, 65mm, 70mm.In other embodiments, the distance between this first through hole 1101 and the interior ring of this conductive copper 130 also can design according to the actual needs of circuit board and size.
The 4th step, refers to Fig. 7, Fig. 7 show be this first through hole 1101 is carried out to electric conducting material 1103 filling to form the first via 1102.This electric conducting material 1103 is generally the conductive materials such as copper cream, gold, tin.This circuit that substantially completes this circuit board 100 is made flow process.
The 5th step, adopts test section 103 to detect the interlayer offset distance of circuit board 100, particularly, detects the offset distance of this second conducting wire 112 with respect to this first conducting wire 111.Need to provide electroplanting device to electroplate the conduction copper packing 110 on these 103 surfaces, test section herein.Wherein, the access point that this plating wiring 1302 of this circuit board frontside edge is electroplanting device.Drawn this second conducting wire 112 in this product zone 101 offset distance with respect to this first conducting wire 111 by estimating this first row conduction copper packing 110 in capable of M on this test section 103 of this circuit board 100 by gold-plated number.
Particularly, first suppose that this second conducting wire 112 is L with respect to the offset distance of this first conducting wire 111, as L < A
1time, the first via 1102 of this first row can not contact conducting with this conductive copper 130 of same column, thus the conduction copper packing 110 of this first row can not be coated with gold; Work as A
1< L < A
2time, the first via 1102 of this first row contacts conducting with this conductive copper 130 of same column, thus the conduction copper packing of this first row 110 can be by gold-plated; Work as A
2< L < A
3the first via 1102 of this first row and this first via 1102 of this secondary series contact conducting respectively with this conductive copper 130 of its same column, this conduction copper packing 110 of first row and secondary series all can be by gold-plated immediately, in like manner, and as L > A
6time, 6 row conductions copper packings 110 all can plated with gold, represents that offset distance L is greater than 70mm.
So, just can directly be drawn the interlayer offset distance of conducting wire on this circuit board 100 by gold-plated number according to this conduction copper packing 110.Offset distance detection to this circuit board 100 is complete, and test section can be removed, and only leaves the product zone 101 that client needs, and can circuit board 100 be divided into different grades according to offset distance with the method.
The invention still further relates to a kind of method of making multilayer circuit board 200 on the basis of this circuit board 100.Specifically comprise: a circuit board 100 as above is provided, forms successively P layer insulating 12 and P layer the second copper foil layer 13 on the surface of this second conducting wire 112, wherein, this insulating barrier 12 and this second copper foil layer 13 are successively separately.Because this conduction copper packing 110 is gold-plated for visual detection, can not be insulated layer or copper foil layer and cover herein.So need to make multilayer circuit board time, should increase insulating barrier 12 with copper foil layer 13 on the surface of this second conducting wire 112 and make conducting wire on copper foil layer 13.
Pi layer in this product zone 101 the second copper foil layer formed to Pi layer the second conducting channel 112, Pi layer the second copper foil layer in this test section 103 is made into multiple conductive copper 130 of M × N arrayed, wherein, M, N, i, P are natural number, M=P+1; N ﹥ 1, i≤1.For this Pi layer second copper foil layer 13 in this P layer second copper foil layer 13, between the capable conductive copper of i+1 in the capable conductive copper of this M, be electrically connected by this copper metal line 1301, this copper metal line 1301 extends to this second copper foil layer 13 edge of this Pi layer and forms and electroplate wiring 1302.
Above-mentioned this first through hole 1101 is extended and makes it run through this internal substrate 10, P layer insulating 12 and P layer the second copper foil layer 13.Place, the center of circle straight line of the center of circle of this each conduction copper packing 110 and this each first through hole 1101 corresponding with it is perpendicular to this this insulating barrier 12.In present embodiment, this conduction copper packing 110, this conductive copper 130, this first conducting wire 111 and this second conducting wire 112 all adopt image transfer technique and etch process to form simultaneously.Finally this first through hole 1101 is carried out to the filling of electric conducting material 1103, to form this first via 1102.
For the structure of this multilayer circuit board 200 of simple declaration, make P=2 herein, in other embodiments, the number of plies of initialization circuit plate according to actual needs.
What Fig. 8 showed is the circuit board 200 in the situation of P=2, and what Fig. 9-11 showed is the structure diagram of the test section 1031 of this circuit board 200.This test section 1301 is in order to clearly show the concrete grammar of test, the insulating barrier 12 between conducting wire has been omitted in Fig. 9-11, and in order to know the skew of describing between conducting wire, Fig. 9-11 are all arranged on the copper foil layer surface towards these conduction copper packing 110 places in the diagram by this conductive copper 130 of arrayed that should be opposing with conduction copper packing 110 on each line layer of test section in Fig. 8.This does not affect the description of test effect.
Due in the manufacturing process of specific boards 200, every one deck second 112Dou test section, conducting wire of product zone 101 is provided with this conductive ring 130 of the array arrangement for testing this layer the second conducting wire 112 offset distance.In this case convenience this circuit board 200 is described, will be provided with second called after B1 layer the second conducting wire 1121, B2 layer the second conducting wire 1122, B3 layer second conducting wire 1123 respectively, conducting wire 112 at conductive ring 130 places.Be appreciated that, this B1 layer the second conducting wire 1121 is the second conducting wire 112 of this circuit board 100, and this B2 layer the second conducting wire 1122 and this B3 layer the second conducting wire 1123 are this second copper foil layer 12 of pressing and design formings on the basis of circuit board 100.
As previously mentioned, for this Pi layer second copper foil layer 13 in this P layer second copper foil layer 13, between capable this conductive copper 130 of i+1 in the capable conductive copper of this M, be electrically connected by this copper metal line 1301.Incorporated by reference to Fig. 9-11, for this B1 layer the second conducting wire 1121, between this first row conductive ring 130, connect by copper metal line 1301 and extend to these circuit board 200 edges formation and electroplate wiring 1302; Form plating wiring 1302 for connecting by copper metal line 1301 between these B2 layer second conducting wire 1122, the 2 row conductive rings 130 and extending to these circuit board 200 edges; Between this conductive ring 130 of the 3rd row, connect by copper metal line 1301 and extend to these circuit board 200 edges and form this plating wiring 1302.
In the time testing the skew of this second conducting wire 112 of every one deck, the access point that this plating wiring 1302 at the every one deck of this circuit board 200 edge is electroplanting device, then the conduction copper packing 110 on these circuit board 200 surfaces is electroplated, observed the conduction copper packing 110 on these circuit board 200 surfaces and just can be learnt that by gold-plated situation the second conducting wire of this circuit board 200 is with respect to the skew of this first conducting wire.
Compared with prior art, the circuit board that the circuit board manufacturing method that the technical program provides is made into, comprise Yu Fei product zone, product zone, by defining a test section in non-product zone, the first copper foil layer of test section is made into the conduction copper packing of arrayed, the second copper foil layer of test section is made into the conductive copper of arrayed, electroplate by the conduction copper packing to test section, the number of the plated gold of conduction copper packing on surface, visual test section show that the second conducting wire of product zone is with respect to the skew of the first circuit.Method is simple, cost-saving.
In addition, those skilled in the art also can do other and change in spirit of the present invention, and certainly, the variation that these do according to spirit of the present invention, all should be included in the present invention's scope required for protection.
Claims (10)
1. a manufacture method for circuit board, comprises step:
One basal plate is provided, this basal plate has the first copper foil layer, insulating barrier and the second copper foil layer, this first copper foil layer and this second copper foil layer lay respectively at two opposing surfaces of this insulating barrier, this basal plate comprises product zone and at least one test section, and this at least one test section is used for the interlayer offset distance in test products district;
This first copper foil layer in this product zone is made and formed the first conducting wire, this second copper foil layer making formation, second conducting wire;
This first copper foil layer in this at least one test section is made into multiple conduction copper packings of M × N arrayed, and this second copper foil layer in this at least one test section is made into multiple conductive copper of M × N arrayed, the first row conductive copper during this M is capable is electrically connected by copper metal line, this copper metal line extends to this inner plating edge and forms plating wiring, the plurality of conduction copper packing is corresponding one by one with the plurality of conductive copper, the diameter of this conduction copper packing is less than the diameter of the conductive copper corresponding with it, along the direction of this conductive copper arrayed, the diameter of this conductive copper successively constant amplitude increases,
In each conduction copper packing, form the first through hole, this first through hole runs through this first conductive pad, this intermediate insulating layer and this conductive copper, the equal diameters of this each the first through hole; This first through hole is carried out to the filling of electric conducting material to form this first via;
And the conduction copper packing of this test section is carried out to electrolytic gold plating, draw the second conducting wire in this product zone offset distance with respect to this first conducting wire by estimating the number of the plated gold of the first row conduction copper packing in capable of M on this test section.
2. circuit board manufacturing method as claimed in claim 1: at side pressing formation P layer insulating and P layer second copper foil layer successively of this second conducting wire, wherein, insulating barrier and the second copper foil layer are successively separately, and each the second copper foil layer Pi in P layer the second copper foil layer in this product zone is formed to the second conducting channel, each the second copper foil layer Pi in P layer the second copper foil layer in this at least one test section is made into multiple conductive copper of M × N arrayed, the plurality of conductive pad is corresponding one by one with the plurality of conductive copper, wherein, M, N, i, P is natural number, M=P+1, N ﹥ 1, i≤1.
3. circuit board manufacturing method as claimed in claim 2, is characterized in that: extend this first through hole and make this first through hole run through this basal plate, P layer insulating and P layer copper foil layer.
4. circuit board manufacturing method as claimed in claim 3, is characterized in that: this first filling through hole electric conducting material is formed to the first via.
5. the manufacture method of circuit board as claimed in claim 1 or 2, is characterized in that: this conduction copper packing, conductive copper, the first conducting wire and the second conducting wire adopt image transfer technique and etch process to form simultaneously.
6. the manufacture method of circuit board as claimed in claim 2, is characterized in that: between the conductive copper that on this Pi layer, the i+1 of M in capable is capable, be electrically connected by copper metal line, this copper metal line extends to this second copper foil layer edge and forms plating wiring.
7. the manufacture method of circuit board as claimed in claim 1, it is characterized in that: between the first row conductive copper in capable near this M in this second copper foil layer of this first copper foil layer, be electrically connected by copper metal line, and this copper metal line extends to this second copper foil layer edge and forms plating wiring.
8. the manufacture method of circuit board as claimed in claim 1, is characterized in that: the direction of arranging along this conductive copper pad array, the diameter of this conduction copper packing all equates.
9. the manufacture method of circuit board as claimed in claim 1, is characterized in that: the detection method of the offset distance of described circuit board is: first set the direction of arranging along this conductive copper, the distance between the interior ring of this first through hole and this conductive copper is respectively A
1, A
2, A
3, A
4, A
5..., An, A
n+1, this second conducting wire is L with respect to the offset distance of this first conducting wire; As L < A
1time, the first via of this first row with can not contact conducting with the conductive copper of its same column, thereby the conduction copper packing of this first row can not be coated with gold; Work as A
1< L < A
2time, the first via of this first row contacts conducting with this conductive copper of same column, and the conductive copper inwall of these row can be coated with gold, thus the conduction copper packing of this first row can be by gold-plated; Work as A
2< L < A
3, this first via of the first via of this first row and secondary series contacts conducting respectively with this conductive copper of its same column, thus the conduction copper packing of this first row and this secondary series can be by gold-plated, in like manner, as L > A
n+1time, n+1 row conduction copper packing all can plated with gold, represents that offset distance L is greater than A
n+1.
10. the manufacture method of circuit board as claimed in claim 9, is characterized in that: A
n+1with A
nbetween difference be certain value.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210429680.XA CN103796429B (en) | 2012-11-01 | 2012-11-01 | The manufacture method of circuit board |
| TW101142285A TW201419971A (en) | 2012-11-01 | 2012-11-13 | Method of manufacturing circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210429680.XA CN103796429B (en) | 2012-11-01 | 2012-11-01 | The manufacture method of circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103796429A true CN103796429A (en) | 2014-05-14 |
| CN103796429B CN103796429B (en) | 2017-03-15 |
Family
ID=50671558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210429680.XA Active CN103796429B (en) | 2012-11-01 | 2012-11-01 | The manufacture method of circuit board |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103796429B (en) |
| TW (1) | TW201419971A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108648639A (en) * | 2018-06-07 | 2018-10-12 | 江西兴泰科技有限公司 | A kind of COG segment encodes display base plate and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001358464A (en) * | 2000-06-15 | 2001-12-26 | Nippon Avionics Co Ltd | Build-up printed-wiring board and its manufacturing method |
| CN101212896A (en) * | 2006-12-27 | 2008-07-02 | 株式会社东芝 | Method of inspecting printed wiring board and printed wiring board |
| CN102098884A (en) * | 2010-12-29 | 2011-06-15 | 北大方正集团有限公司 | Standard laminated plate and manufacturing method thereof |
| CN102548249A (en) * | 2010-12-13 | 2012-07-04 | 富葵精密组件(深圳)有限公司 | Manufacturing method of circuit boards |
| CN102612266A (en) * | 2011-01-21 | 2012-07-25 | 富葵精密组件(深圳)有限公司 | Manufacturing method of circuit board |
-
2012
- 2012-11-01 CN CN201210429680.XA patent/CN103796429B/en active Active
- 2012-11-13 TW TW101142285A patent/TW201419971A/en unknown
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001358464A (en) * | 2000-06-15 | 2001-12-26 | Nippon Avionics Co Ltd | Build-up printed-wiring board and its manufacturing method |
| CN101212896A (en) * | 2006-12-27 | 2008-07-02 | 株式会社东芝 | Method of inspecting printed wiring board and printed wiring board |
| CN102548249A (en) * | 2010-12-13 | 2012-07-04 | 富葵精密组件(深圳)有限公司 | Manufacturing method of circuit boards |
| CN102098884A (en) * | 2010-12-29 | 2011-06-15 | 北大方正集团有限公司 | Standard laminated plate and manufacturing method thereof |
| CN102612266A (en) * | 2011-01-21 | 2012-07-25 | 富葵精密组件(深圳)有限公司 | Manufacturing method of circuit board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108648639A (en) * | 2018-06-07 | 2018-10-12 | 江西兴泰科技有限公司 | A kind of COG segment encodes display base plate and preparation method thereof |
| CN108648639B (en) * | 2018-06-07 | 2024-05-24 | 江西兴泰科技股份有限公司 | COG segment code display substrate and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201419971A (en) | 2014-05-16 |
| CN103796429B (en) | 2017-03-15 |
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