CN103796336A - FPGA-based ZigBee wireless sensing network IP construction method - Google Patents
FPGA-based ZigBee wireless sensing network IP construction method Download PDFInfo
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Abstract
The invention relates to an FPGA-based ZigBee wireless sensing network IP construction method and belongs to the technical field of wireless sensing network devices and applications. According to the FPGA-based ZigBee wireless sensing network IP construction method, a processor module, an Avalon bus, a counter module, an asynchronous communication module, a wireless communication module, a digital frequency control module, an instantaneous memory storage module, a DMA control module, a power source control module and the like are provided; one end of a NiosIICPU processor is connected with the Avalon bus, and the other end of the NiosIICPU processor is connected with a debugging interface; one end of a counter is connected with the bus, and the other end of the counter is connected with a data control end; and one end of the wireless communication module is connected with a transmitting-end controller, and the other end of the wireless communication module is connected with the bus. The method includes the following five steps of: step one, hardcore construction; step two, hard core function and logic simulation; step three, soft core construction; step four, incentive simulation and port verification; and step five, ZigBee IP core generation.
Description
One, technical field
The present invention relates to the application that FPGA embeds ZigBee IP kernel, relate in particular to a kind of ZigBee radio sensing network IP kernel construction method based on FPGA platform, belong to the technical field of radio sensing network equipment and application.
Two, background technology
The features such as ZigBee in the market has the features such as cost is low, networking is simple, network capacity is large, but shortcoming is to realize its function on ZigBee chip, and arithmetic speed is slow, system response time is long, logic function is simple.Along with the development of microelectric technique, nanometer technology and programming device and EDA developing instrument, making to realize its function on fpga chip becomes possibility.Therefore it is necessary designing a portable, configuring the ZigBee IP kernel based on FPGA simple, application efficiency is high and cost is less.In FPGA, not only can realize the repertoire of ZigBee completely but also can also carry out data processing fast to obtained data.A kind of ZigBee radio sensing network IP kernel construction method based on FPGA is disclosed herein.
Three, summary of the invention
1, goal of the invention
Existing ZigBee processor is based on CMOS technique, although have lower system power dissipation, its design is complicated, portable poor, and application efficiency is not high.The present invention adopts the design to ZigBee IP kernel to be embedded in FPGA, object is the poor feature of limitation, transplantability in order to overcome ZigBee chip, the IP kernel construction method that a kind of ZigBee based on programmable gate array (FPGA) is provided, it can realize ZigBee repertoire; And have transplantability strong, configure the features such as simple, improve system integration operational data speed.
2, technical scheme
1), the present invention is a kind of ZigBee radio sensing network IP kernel construction method based on FPGA, it is made up of processor module, Avalon bus, counter module, asynchronous communication module, wireless communication module, numerical frequency control module, immediate memory memory module, DMA control module, energy supply control module etc.Signal between them flows to and position connects as described below:
NiosII CPU processor one end is connected to Avalon bus, and one end is connected to debugging interface in addition; Counter module one end is connected to the other end in bus and is connected to Data Control end; Wireless communication module one end is connected to the transmitting terminal controller other end and is connected in bus.
1. total line traffic control arbitration modules (01) one end is received NiosII cpu controller (02), one end is received immediate memory memory module (06), and it accepts to pass through the control of Avalon bus to wireless module from the control data of CPU;
2. wireless communication module (05) is the core component of whole IP kernel, and it adopts the wireless transceiving modes of Zigbee protocol regulation to carry out networking.It is upper that immediate memory memory module (06) is received in total line traffic control arbitration (01), realizes the buffer memory that receives data, so that the processing of CPU to data.Complete the period allocated of a receiving and transmitting signal by counter module (03).
3. asynchronous communication module (04) is received in Avalon bus, by the asynchronous communication of signal being handled to the acquisition process of paired data, complete the digital frequency division of signal is completed to the preparation to signal transmitting by numerical frequency control module (07).
4. dma module (08) for by the information reproduction that is sent to module to internal memory (RAM), and allow processed information automatically to move on to external peripheral devices from internal memory.Be convenient to the memory function of equipment to signal.
5. energy supply control module (09) is controlled whole IP kernel operating voltage and electric current, works for system powers on.
2), the present invention is a kind of ZigBee radio sensing network IP kernel construction method based on FPGA, the concrete steps of the method are as follows, its flow chart as shown in the figure.
Step 1: stone builds.According to ZigBee input and output protocol requirement, design object is divided into each functional module.Functional module mainly comprises total line traffic control arbitration modules (01), NiosII cpu controller (02), counter module (03), asynchronous mutual trust module (04), wireless communication module (05), immediate memory memory module (06), numerical frequency control module (07), DMA control module (08), energy supply control module (09).Then adopt hardware description language Verilog HDL write code construction stone and realize functions, should write logical constraint condition simultaneously and meet the demands.
Step 2: stone function and logical simulation.Application ModelSim emulation tool carries out functional simulation to constructed stone modules and top-level module, verifies the correctness of design according to the waveform of simulation result.If do not meet, should revise code, until complete functions requirement.Application QuartusII software translating creating environments project file, the functions module file using upper step by emulation is as input file, and arranging and compiling the parameter of changing commanders is the port file that has compiled rear output net meter file and input and output.
Step 3: soft core builds.Build wireless communication module (05) and numerical frequency control module (07) and realize the transmission-receiving function of wireless data by NiosII.
Step 4: excitation emulation and port authorization: before distributing, net meter file is carried out to functional verification, judge according to simulation result whether allomeric function meets design requirement.If do not meet, return to step 1, revise ungratified code, until meet.
Step 5: generate ZigBee IP kernel.After logical simulation, can generate a net meter file and corresponding port input-output file.Under QuartusII software, set up Top-layer Design Method file and call the ZigBee IP kernel of generation, distribute input and output to call in order to other module.
Wherein, the stone described in step 2 be based on described in Verilog language and under QuartusII translation and compiling environment comprehensive realization.QuartusII translation and compiling environment is the FPGA Integrated Development Environment that ALTERA company releases, function mainly comprises design input, comprehensive, emulation, realization and download, cover the overall process of FPGA exploitation, need to be by other any third party's eda softwares in function.
3) design effect
Existing ZigBee processor is based on CMOS technique, although have lower system power dissipation, its design is complicated, portable poor, and application efficiency is not high.Adopt the design to ZigBee IP kernel to be embedded in FPGA herein, object is the poor feature of limitation, transplantability in order to overcome ZigBee chip, and it is necessary designing a portable, configuring the ZigBee IP kernel based on FPGA simple, application efficiency is high and cost is less.In FPGA, not only can realize the repertoire of ZigBee completely but also can also carry out data processing fast to obtained data.
Four, accompanying drawing explanation
Fig. 1 is a simple ZigBee IP kernel system schematic based on FPGA
Fig. 2 is the ZigBee IP kernel system architecture diagram based on FPGA of the present invention
Fig. 3 is the construction method FB(flow block) of the ZigBee IP kernel based on FPGA of the present invention
Symbol description in figure is as follows:
CPU (Central Processing Unit): central processing unit;
FPGA: field programmable gate array;
IO: digital quantity input/output port;
DMA: direct memory access.
Five, embodiment
For system specialization mentality of designing of the present invention, therefore provide a simple examples application of Zigbee protocol, as shown in the figure.This application example system is made up of NiosII CPU, Avalon bus, counter module, asynchronous communication module, wireless communication module, numerical frequency control module.Wireless communication module is complete paired data transmitting-receiving operation under the control of NiosII CPU, by Avalon bus access control counter module and numerical frequency control module, and complete paired data frequency division and counting operation.Wherein wireless communication module is the core of whole equipment, for the ZigBee IP kernel based on FPGA provides hardware realization condition, allow data send according to the requirement of Zigbee protocol stack, therefore design collection and the sending function of the complete paired data of equipment of the ZigBee IP kernel based on FPGA.
Realize radio transmission-receiving function in order to be embedded into ZigBee radio sensing network IP kernel in FPGA, method is that NiosII CPU sends the transmitting-receiving of controlling wireless data in instruction FPGA bus.
Embodiment:
Shown in Fig. 1, be a kind of ZigBee radio sensing network IP kernel construction method structure chart based on FPGA, to send access as example by ZigBee radio sensing network being carried out to a signal, describe one embodiment of the present of invention.
1, the present invention is a kind of ZigBee radio sensing network IP kernel construction method based on FPGA, and it is made up of processor module, Avalon bus, counter module, asynchronous communication module, wireless communication module, numerical frequency control module, immediate memory storage control module, DMA control module, energy supply control module etc.Signal between them flows to and position connects as described below: NiosII CPU processor one end is connected to Avalon bus, and one end is connected to debugging interface in addition; Counter module one end is connected to the other end in bus and is connected to Data Control end; Wireless communication module one end is connected to the transmitting terminal controller other end and is connected in bus.1) total line traffic control arbitration modules (01) one end is received NiosII cpu controller (02), one end is received immediate memory memory module (06), and it accepts to pass through the control of Avalon bus to wireless module from the control data of CPU; 2) wireless communication module (05) is the core component of whole IP kernel, and it adopts the wireless transceiving modes of Zigbee protocol regulation to carry out networking.It is upper that immediate memory memory module (06) is received in total line traffic control arbitration (01), realizes the buffer memory that receives data, so that the processing of CPU to data.Complete the period allocated of a receiving and transmitting signal by counter module (03).3) asynchronous communication module (04) is received in Avalon bus, by the asynchronous communication of signal being handled to the acquisition process of paired data, complete the digital frequency division of signal is completed to the preparation to signal transmitting by numerical frequency control module (07).4) dma module (08) for by the information reproduction that is sent to module to internal memory (RAM), and allow processed information automatically to move on to external peripheral devices from internal memory.Be convenient to the memory function of equipment to signal.5) energy supply control module (09) is controlled whole IP kernel operating voltage and electric current, works for system powers on.
Described counter module (03) is made up of 8 digit counters, 16 digit counters, a protocol address counter, the tally function of complete paired data, its module is connected in bus and can is completed the data of all buses of flowing through are carried out to counting work by bus control module (01).
Described asynchronous communication module (04) is in the time sending data, and the time slot between the data that send can be arbitrarily, and certainly, receiving terminal must be carried out the preparation of reception the moment.Transmitting terminal can start to send data at any time, therefore must add mark in the place of the beginning of each character and end, adds start bit and position of rest, to receiving terminal can correctly be got off each receive character.
Described wireless communication module (05) is the core of whole ZigBee IP kernel, mainly formed by radio memory, CSMA/CA gate processor, wireless data interface etc., be connected with bus arbitration control module (01) by Avalon bus, by total line traffic control core CPU (02) controller, wireless communication module (05) controlled the object of radio communication.
Described numerical frequency control module (06) is carried out FREQUENCY CONTROL to data, data for new reception complete frequency dividing control by this module, the dual control of gain to signal and frequency, reach the function that meets its transmission data, this module and wireless communication module (05) intercommunication, controls its fractional frequency signal by NiosII CPU (02) and finally completes transmission.
Described immediate memory memory module (07) is that the data to gathering are carried out immediate memory storage, is being processed and is being sent by wireless communication module (05) by NiosII CPU (02) by the data of wireless communication module (05) and instantaneous the storing in this module of the data of bus control module (01) energy.
Described dma module (08) for by the information reproduction that is sent to module to internal memory (RAM), and allow processed information automatically to move on to external peripheral devices from internal memory.Be convenient to the memory function of equipment to signal.Described energy supply control module (09) is controlled whole IP kernel operating voltage and electric current, works for system powers on.
2), the present invention is a kind of ZigBee radio sensing network IP kernel construction method based on FPGA, the concrete steps of the method are as follows, its flow chart as shown in the figure.
Step 1: stone builds.According to ZigBee input and output protocol requirement, design object is divided into each functional module.Functional module mainly comprises total line traffic control arbitration modules (01), NiosII cpu controller (02), counter module (03), asynchronous mutual trust module (04), wireless communication module (05), immediate memory memory module (06), numerical frequency control module (07), DMA control module (08), energy supply control module (09).Then adopt hardware description language Verliog HDL write code construction stone and realize functions, should write logical constraint condition simultaneously and meet the demands.
Step 2: stone function and logical simulation.Application ModelSim emulation tool carries out functional simulation to constructed stone modules and top-level module, verifies the correctness of design according to the waveform of simulation result.If do not meet, should revise code, until complete functions requirement.Application QuartusII software translating creating environments project file, the functions module file using upper step by emulation is as input file, and arranging and compiling the parameter of changing commanders is the port file that has compiled rear output net meter file and input and output.
Step 3: soft core builds.Build wireless communication module (05) and numerical frequency control module (07) and realize the transmission-receiving function of wireless data by NiosII.
Step 4: excitation emulation and port authorization: before distributing, net meter file is carried out to functional verification, judge according to simulation result whether allomeric function meets design requirement.If do not meet, return to step 1, revise ungratified code, until meet.
Step 5: generate ZigBee IP kernel.After logical simulation, can generate a net meter file and corresponding port input-output file.Under QuartusII software, set up Top-layer Design Method file and call the ZigBee IP kernel of generation, distribute input and output to call in order to other module.
Wherein, the stone described in step 2 be based on Verilog language description and under QuartusII translation and compiling environment comprehensive realization.QuartusII translation and compiling environment is the FPGA Integrated Development Environment that ALTERA company releases, function mainly comprises design input, comprehensive, emulation, realization and download, cover the overall process of FPGA exploitation, need to be by other any third party's eda softwares in function.
Claims (3)
1. the present invention is a kind of ZigBee radio sensing network IP kernel construction method based on FPGA, it is characterized in that: it is made up of processor module, Avalon bus, counter module, asynchronous communication module, wireless communication module, numerical frequency control module, immediate memory storage control module, DMA control module, energy supply control module etc.Signal between them flows to and position connects as described below: NiosII CPU processor one end is connected to Avalon bus, and one end is connected to debugging interface in addition; Counter module one end is connected to the other end in bus and is connected to Data Control end; Wireless communication module one end is connected to the transmitting terminal controller other end and is connected in bus.
Described counter module is made up of 8 digit counters, 16 digit counters, a protocol address counter, the tally function of complete paired data, its module is connected in bus and can is completed the data of all buses of flowing through are carried out to counting work by bus control module.
Described asynchronous communication module is in the time sending data, and the time slot between the data that send can be arbitrarily, and certainly, receiving terminal must be carried out the preparation of reception the moment.Transmitting terminal can start to send data at any time, therefore must add mark in the place of the beginning of each character and end, adds start bit and position of rest, to receiving terminal can correctly be got off each receive character.
Described wireless communication module is the core of whole ZigBee IP kernel, mainly formed by radio memory, CSMA/CA gate processor, wireless data interface etc., be connected with bus arbitration control module by Avalon bus, by total line traffic control core cpu controller, wireless communication module controlled the object of radio communication.
Described numerical frequency control module is carried out FREQUENCY CONTROL to data, data for new reception complete frequency dividing control by this module, the dual control of gain to signal and frequency, reach the function that meets its transmission data, this module and wireless communication module intercommunication, control its fractional frequency signal by NiosII CPU and finally complete transmission.
Described immediate memory memory module is that the data to gathering are carried out immediate memory storage, is being processed and is being sent by wireless communication module by NiosII CPU by the data of wireless communication module and instantaneous the storing in this module of the data of bus control module energy.
Described dma module for by the information reproduction that is sent to module to internal memory (RAM), and allow processed information automatically to move on to external peripheral devices from internal memory.The equipment of being convenient to has a storage function to signal.
The whole IP kernel operating voltage of described energy supply control module control and electric current, work for system powers on.
2. a kind of ZigBee radio sensing network IP kernel construction method based on FPGA according to claim 1, is characterized in that: the concrete steps of the method are as follows:
Step 1: stone builds.According to ZigBee input and output protocol requirement, design object is divided into each functional module.Functional module mainly comprises total line traffic control arbitration modules, NiosII cpu controller, counter module, asynchronous mutual trust module, wireless communication module, immediate memory memory module, numerical frequency control module, DMA control module, energy supply control module.Then adopt hardware description language Verilog HDL write code construction stone and realize functions, should write logical constraint condition simultaneously and meet the demands.
Step 2: stone function and logical simulation.Application ModelSim emulation tool carries out functional simulation to constructed stone modules and top-level module, verifies the correctness of design according to the waveform of simulation result.If do not meet, should revise code, until complete functions requirement.Application QuartusII software translating creating environments project file, the functions module file using upper step by emulation is as input file, and arranging and compiling the parameter of changing commanders is the port file that has compiled rear output net meter file and input and output.
Step 3: soft core builds.Build wireless communication module and numerical frequency control module and realize the transmission-receiving function of wireless data by NiosII.
Step 4: excitation emulation and port authorization: before distributing, net meter file is carried out to functional verification, judge according to simulation result whether allomeric function meets design requirement.If do not meet, return to step 1, revise ungratified code, until meet.
Step 5: generate ZigBee IP kernel.After logical simulation, can generate a net meter file and corresponding port input-output file.Under QuartusII software, set up Top-layer Design Method file and call the ZigBee IP kernel of generation, distribute input and output to call in order to other module.
3. it is characterized in that according to claim 2: the stone described in step 2 be based on Verilog language description and under QuartusII translation and compiling environment comprehensive realization.QuartusII translation and compiling environment is the FPGA Integrated Development Environment that ALTERA company releases, function mainly comprises design input, comprehensive, emulation, realization and download, cover the overall process of FPGA exploitation, need to be by other any third party's eda softwares in function.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105843993A (en) * | 2016-03-17 | 2016-08-10 | 中国科学院微电子研究所 | IP generation method and tool |
| CN111787505A (en) * | 2020-07-06 | 2020-10-16 | 北京理工大学 | Modular reconfigurable wireless network test node system and working method |
| CN113126569A (en) * | 2021-04-19 | 2021-07-16 | 北京航空航天大学 | Digital twin equipment construction method and system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105843993A (en) * | 2016-03-17 | 2016-08-10 | 中国科学院微电子研究所 | IP generation method and tool |
| CN105843993B (en) * | 2016-03-17 | 2020-10-20 | 中科芯时代科技有限公司 | IP generation method and tool |
| CN111787505A (en) * | 2020-07-06 | 2020-10-16 | 北京理工大学 | Modular reconfigurable wireless network test node system and working method |
| CN113126569A (en) * | 2021-04-19 | 2021-07-16 | 北京航空航天大学 | Digital twin equipment construction method and system |
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