CN103794581B - A kind of thermoelectric radiating device - Google Patents
A kind of thermoelectric radiating device Download PDFInfo
- Publication number
- CN103794581B CN103794581B CN201210422441.1A CN201210422441A CN103794581B CN 103794581 B CN103794581 B CN 103794581B CN 201210422441 A CN201210422441 A CN 201210422441A CN 103794581 B CN103794581 B CN 103794581B
- Authority
- CN
- China
- Prior art keywords
- hole
- silicon
- metallic silicon
- type silicon
- metallic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a kind of thermoelectric radiating device, including: top layer chip, it includes top layer substrate and the P-type silicon through hole running through top layer substrate and the first metallic silicon through hole, and P-type silicon through hole is for connecting the zero potential of power supply, and the first metallic silicon through hole is for connecting the positive potential of power supply；Intermediate layer chip, it is stacked is connected to top layer chip bottom, and the second metallic silicon through hole including intermediate layer substrate and running through intermediate layer substrate and the 3rd metallic silicon through hole are formed with electronic device in the chip of intermediate layer；Bottom chip, it is stacked and is connected between a layer chip bottom, including underlying substrate and the N-type silicon through hole and the 4th metallic silicon through hole that run through underlying substrate, and two through hole is interconnected in the bottom of bottom chip, wherein, P-type silicon through hole, the second metallic silicon through hole and N-type silicon through hole are sequentially connected with, and the first metallic silicon through hole, the 3rd metallic silicon through hole and the 4th metallic silicon through hole are sequentially connected with.The radiating effect of this thermoelectric radiating device is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of thermoelectric radiating device.
Background technology
In technical field of manufacturing semiconductors, what the cooling of integrated circuit always must solve important asks
Topic.The high temperature produced due to Joule heat usually can reduce the Performance And Reliability of IDE.
After the thermocouple being made up of N, P-type material is applied DC voltage, the side being passed through because of unidirectional current
To difference, will produce at galvanic couple node heat absorption and exothermic phenomenon, a node heating, simultaneously another
Individual node turns cold, and this phenomenon is referred to as peltier effect.Peltier thermoelectric heat abstractor is a kind of utilization
Paltie effect is to produce the device of heat pump effect.Peltier thermoelectric heat abstractor has cold end and hot junction
Two ends, connect between cold end and hot junction and have one or several thermocouple.All these thermocouples
Link together, and extract two power connector ends at two ends out.Straight when applying to two power connector ends
During stream voltage, above-mentioned cold junction temperature reduces and hot-side temperature raises, and the heat of the coldest end is conducted
To hot junction.This equipment does not produce heat or absorbs heat, but is conducted to another from one end by heat
End, thus makes one end be cooled.
Need to provide a kind of thermoelectric radiating device, to solve the cooling problem of said integrated circuit.
Summary of the invention
For solving above-mentioned technical problem, according to an aspect of the invention, it is provided a kind of thermoelectric radiating
Device, comprising: top layer chip, it includes top layer substrate and runs through the P-type silicon of top layer substrate and lead to
Hole and the first metallic silicon through hole, P-type silicon through hole is for connecting the zero potential of power supply, and the first metallic silicon leads to
Hole is for connecting the positive potential of power supply；Intermediate layer chip, it is stacked is connected to top layer chip bottom, in
Interbed chip includes intermediate layer substrate and the second metallic silicon through hole running through intermediate layer substrate and the 3rd metal
Silicon through hole, is formed with electronic device in the chip of intermediate layer；Bottom chip, it is stacked and is connected between layer
Chip bottom, bottom chip includes underlying substrate and runs through N-type silicon through hole and the 4th gold medal of underlying substrate
Belong to silicon through hole, and N-type silicon through hole and the 4th metallic silicon through hole be interconnected in the bottom of bottom chip,
Wherein, P-type silicon through hole, the second metallic silicon through hole and N-type silicon through hole are sequentially connected with, and the first metal
Silicon through hole, the 3rd metallic silicon through hole and the 4th metallic silicon through hole are sequentially connected with.
Further, top layer chip also includes the fifth metal silicon through hole running through top layer substrate, five metals
Belong to silicon through hole for connection of electronic devices.
Further, thermoelectric radiating device includes many groups of the P-type silicon through holes being sequentially connected with, the second metals
Silicon through hole and N-type silicon through hole.
Further, P-type silicon through hole, the second metallic silicon through hole and the N-type silicon that many groups are sequentially connected with leads to
Hole is arranged around electronic device.
Further, the bottom of bottom chip is provided with redistribution layer, N-type silicon through hole and the 4th metal
Silicon through hole is interconnected by redistribution layer.
Further, the top of silicon through hole is provided with pad.
Further, P-type silicon through hole, the second metallic silicon through hole and N-type silicon through hole sequentially pass through soldered ball
Connect, and the first metallic silicon through hole, the 3rd metallic silicon through hole and the 4th metallic silicon through hole sequentially pass through weldering
Ball connects.
Further, the first metallic silicon through hole, the second metallic silicon through hole, the 3rd metallic silicon through hole and
The packing material of four metallic silicon through holes is copper.
Further, the packing material of P-type silicon through hole and N-type silicon through hole be Tellurobismuthite., Sb2Te3,
Bi2Te3, PbTe, SiGe, crystal phonon glasses or nano material.
The present invention has following technical effect that
In the thermoelectric radiating device of the present invention, in P-type silicon through hole in top layer chip, intermediate layer chip
The second metallic silicon through hole and bottom chip in N-type silicon through hole be sequentially connected with, formed Peltier form
Thermoelectric radiating part.Further, N-type silicon through hole interconnects mutually with the 4th metallic silicon through hole in bottom chip
Logical, and the first metallic silicon through hole, the 3rd metallic silicon through hole and the 4th metallic silicon through hole are sequentially connected with, from
And N shape silicon through hole is connected with the first metallic silicon through hole in top layer chip, so it is positioned in top layer chip
P-type silicon through hole and the first metallic silicon through hole form two power supplys of thermoelectric radiating device respectively and connect
End.Wherein connect the zero potential of power supply at P-type silicon through hole, the first metallic silicon through hole is just connecting power supply
During current potential, its hot junction is formed on the top of this thermoelectric radiating device and bottom, and centre becomes cold end.
Thus, owing to intermediate layer chip being formed with electronic device, allow for this electronic device and cold end
Contact, obtains the cooling of cold end, to keep temperature significantly to raise in the course of the work.This thermoelectricity
Heat abstractor good heat dissipation effect, integrated level is high, and conveniently (both positive and negative polarity of power supply all connects to connect circuit
Relevant position to top layer chip).
Introducing the concept of a series of reduced form in Summary, this will be in specific embodiment party
Formula part further describes.The Summary of the present invention is not meant to attempt to limit
Go out key feature and the essential features of technical scheme required for protection, more do not mean that and attempt really
The protection domain of fixed technical scheme required for protection.
Below in conjunction with accompanying drawing, describe advantages and features of the invention in detail.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.In accompanying drawing
Show embodiments of the present invention and description thereof, be used for explaining the principle of the present invention.In the accompanying drawings,
Fig. 1 shows the structural representation of thermoelectric radiating device according to an embodiment of the invention.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide the most thorough to the present invention
Understanding.It will be apparent, however, to one skilled in the art that the present invention can be without
These details one or more and be carried out.In other example, in order to avoid sending out with the present invention
Life is obscured, and is not described for technical characteristics more well known in the art.
In order to thoroughly understand the present invention, detailed structure will be proposed in following description.Obviously, originally
The execution of invention is not limited to the specific details that those skilled in the art is familiar with.The present invention is relatively
Good embodiment is described in detail as follows, but in addition to these describe in detail, the present invention can also have it
His embodiment.
As it is shown in figure 1, according to an embodiment of the invention thermoelectric radiating device include top layer chip 1,
Intermediate layer chip 2 and bottom chip 3.This top layer chip 1 includes top layer substrate 101, runs through top layer base
The P-type silicon through hole 102 at the end 101 and the first metallic silicon through hole 103, wherein P-type silicon through hole 102 is used
In the zero potential of connection power supply, the first metallic silicon through hole 103 is for connecting the positive potential of power supply.Middle
Layer chip 2 is stacked is connected to top layer chip 1 bottom, including intermediate layer substrate 201 with run through intermediate layer
Second metallic silicon through hole 202 and the 3rd metallic silicon through hole 203 of substrate 201, in intermediate layer chip 2
It is formed with electronic device 204.Bottom chip 3 is stacked is connected between layer chip 2 bottom, the end of including
Layer substrate 301 and N-type silicon through hole 302 and the 4th metallic silicon through hole 303 running through underlying substrate 301.
As shown in fig. 1, N-type silicon through hole 302 and the 4th metallic silicon through hole 303 are at the end of bottom chip 3
Portion is interconnected.Further, P-type silicon through hole the 102, second metallic silicon through hole 202 and N-type silicon through hole
302 are sequentially connected with from top to bottom, the first metallic silicon through hole the 103, the 3rd metallic silicon through hole 203 and the 4th
Metallic silicon through hole 303 is sequentially connected with from top to bottom.
Being appreciated that in the thermoelectric radiating device of the present embodiment, the P-type silicon in top layer chip 1 is led to
The second metallic silicon through hole 202 in hole 102, intermediate layer chip 2 and the N-type silicon in bottom chip 3
Through hole 302 is sequentially connected with, and forms the thermoelectric radiating part of Peltier form.First metallic silicon through hole 103,
3rd metallic silicon through hole 203 and the 4th metallic silicon through hole 303 are sequentially connected with, and form the effect of wire,
And N shape silicon through hole 302 and the 4th metallic silicon through hole 303 in bottom chip 3 are interconnected, from
And be connected with the first metallic silicon through hole 103 in top layer chip 1, so, it is positioned in top layer chip 1
P-type silicon through hole 102 and the first metallic silicon through hole 103 form two electricity of thermoelectric radiating device respectively
Source connection.
Wherein, as shown in fig. 1, the zero potential of power supply, the first gold medal are connected at P-type silicon through hole 102
When belonging to the positive potential that silicon through hole 103 connects power supply, at the P-type silicon through hole 102, second being sequentially connected with
In the PN junction that metallic silicon through hole 202 and N-type silicon through hole 302 are formed, electronics enters to bottom from top
And towards the anode flow of power supply, and positive charge flows (arrow from bottom to top towards the negative pole of power supply
Head A shows the flow direction of electric current), thus its hot junction is formed on the top of this thermoelectric radiating device and bottom,
And centre becomes cold end.Middle heat discharges downwards (arrow in figure by top upward and through bottom
Head B shows the flow direction of heat).
Thus, owing to intermediate layer chip 2 being formed with electronic device 204, this electronic device is allowed for
204 with the cold end in contact of this thermoelectric radiating device, obtain the cooling of cold end, to protect in the course of the work
Hold temperature will not significantly raise.
The effect of cooling can be assessed by Z value, wherein Z=S2× E/T, wherein S represents plug shellfish
Gram coefficient (Seebeck coefficient), E represents that electrical conductivity, T represent thermal conductivity.Due to this thermoelectric radiating device
PN junction silicon clear size of opening relatively big, thus hole, electron stream momentum are bigger so that electrical conductivity E
It is improved, thus improves the radiating effect of thermoelectric radiating device；And in intermediate layer chip 2
Metallic silicon through hole makes thermal conductivity T be reduced, and further increases the heat radiation effect of thermoelectric radiating device
Really.Additionally, as described above, middle heat is discharged, from separately by top and two bottom sides simultaneously
On the one hand improve cooling radiating effect.
It addition, the form of upper and lower three layers of chip stack makes whole device integrated level higher.Additionally, even
When connecing power supply, the both positive and negative polarity of power supply is connected to top layer chip 1, thus it is the most very convenient to connect circuit.
Specifically, the both positive and negative polarity of power supply be connected to top layer chip 1 relevant position (respectively P-type silicon lead to
Hole 102 and the first metallic silicon through hole 103).
It addition, as it is shown in figure 1, in the present embodiment, top layer substrate 101 is coated with between ground floor
Dielectric layer 105, similarly, is coated with the second dielectric layer 205, at bottom in intermediate layer substrate 201
The 3rd dielectric layer 305 it is coated with in substrate 301.Each corresponding silicon through hole in each substrate is running through
The dielectric layer above substrate is also extended through while substrate.And, it is preferable that in the present embodiment, p-type
The top of silicon through hole 102 and the first metallic silicon through hole 103 is each formed with pad 5, in order to be connected to
Positive pole/the negative pole of power supply；Preferably, also, each silicon in intermediate layer chip 2 and bottom chip 3
The top of through hole is the most all each formed with pad 5, moreover it is preferred that intermediate layer chip 2 and top layer
The bottom of all above-mentioned silicon through hole in chip 1 is all each formed with soldered ball 6, is used for and next layer of core
The respective pad 5 of the corresponding silicon via top of sheet is welded.
As it is shown in figure 1, in this embodiment, it is preferred that, top layer chip 1 also includes running through top layer base
The fifth metal silicon through hole 104 at the end 101, this fifth metal silicon through hole 104 is for connection of electronic devices
204.Thus electronic device 204 can be by fifth metal silicon through hole 104 at the table of top layer chip 1
Face is connected to other elements etc. in the external world.Similarly, it is preferable that this fifth metal silicon through hole 104 pushes up
Portion is also formed with pad 5, for the welding of other elements extraneous, and this fifth metal silicon through hole
Soldered ball 6 it is also formed with, for the connection with electronic device 204 bottom 104.In the present embodiment, electronics
In the intermediate layer substrate 201 of 204 formed between layers of chip of device 2, and by running through the second dielectric
The contact hole of layer 205 is connected to the pad 5 of intermediate layer substrate 201 top relative set, this pad 5
It is connected to the soldered ball 6 bottom fifth metal silicon through hole 104, so that electronic device 204 is connected to
Five metallic silicon through holes 104.
It addition, thermoelectric radiating device preferably include the many groups of P-type silicon through holes 102 being sequentially connected with,
Two metallic silicon through holes 202 and N-type silicon through hole 302, so that increasing PN junction silicon through hole further
Size, and then increase the amount of flow of hole, electronics further, improve electrical conductivity E, thus enter one
Step improves cooling effect.As it is shown in figure 1, in the present embodiment, thermoelectric radiating device include two groups suitable
P-type silicon through hole 102, the second metallic silicon through hole 202 of secondary connection and N-type silicon through hole 302, permissible
Understand, in practice, according to thermoelectric radiating device, the concrete structure of electronic device 204 and size,
Any suitable number of P-type silicon through hole the 102, second metallic silicon through hole 202 being sequentially connected with can be set
With N-type silicon through hole 302.
It is highly preferred that the many groups of P-type silicon through hole being sequentially connected with the 102, second metallic silicon through hole 202 and
N-type silicon through hole 302 can be arranged around electronic device 204, with thus increasing heat radiation effect.
It addition, as shown in fig. 1, in the present embodiment, the bottom of bottom chip 3 is preferably provided with
Redistribution layer 304, N-type silicon through hole 302 and the 4th metallic silicon through hole 303 are mutual by redistribution layer
Connection.
Further, as described above, the top of each silicon through hole is provided preferably with respective pad 5, and
Preferably, P-type silicon through hole the 102, second metallic silicon through hole 202 and N-type silicon through hole 302 sequentially lead to
Cross soldered ball 6 to connect, and the first metallic silicon through hole the 103, the 3rd metallic silicon through hole 203 and the 4th metal
Silicon through hole 303 sequentially passes through soldered ball 6 and connects.
Moreover it is preferred that first metallic silicon through hole the 103, second metallic silicon through hole the 202, the 3rd metal
The packing material of silicon through hole 203 and the 4th metallic silicon through hole 303 is copper.And preferably, p-type
The packing material of silicon through hole 102 and N-type silicon through hole 302 be Tellurobismuthite., Sb2Te3, Bi2Te3, PbTe,
SiGe, crystal phonon glasses or nano material.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned enforcement
Example is only intended to citing and descriptive purpose, and is not intended to limit the invention to described embodiment
In the range of.In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-mentioned enforcement
Example, can also make more kinds of variants and modifications according to the teachings of the present invention, these variants and modifications
Within all falling within scope of the present invention.Protection scope of the present invention is wanted by attached right
Book and equivalent scope thereof is asked to be defined.
Claims (9)
1. a thermoelectric radiating device, it is characterised in that including:
Top layer chip, it includes top layer substrate and the P-type silicon through hole running through described top layer substrate and
One metallic silicon through hole, described P-type silicon through hole is for connecting the zero potential of power supply, described first metallic silicon
Through hole is for connecting the positive potential of described power supply；
Intermediate layer chip, it is stacked is connected to described top layer chip bottom, and described intermediate layer chip includes
Intermediate layer substrate and run through the second metallic silicon through hole and the 3rd metallic silicon through hole of the substrate of described intermediate layer,
Described intermediate layer chip is formed with electronic device；
Bottom chip, it is stacked is connected to chip bottom, described intermediate layer, and described bottom chip includes the end
Layer substrate and run through N-type silicon through hole and the 4th metallic silicon through hole of described underlying substrate, and described N
Type silicon through hole and the 4th metallic silicon through hole are interconnected in the bottom of described bottom chip,
Wherein, described P-type silicon through hole, described second metallic silicon through hole and described N-type silicon through hole are sequentially
Connect, and described first metallic silicon through hole, described 3rd metallic silicon through hole and described 4th metallic silicon are logical
Hole is sequentially connected with.
Thermoelectric radiating device the most according to claim 1, it is characterised in that described top layer core
Sheet also includes the fifth metal silicon through hole running through described top layer substrate, and described fifth metal silicon through hole is used for
Connect described electronic device.
Thermoelectric radiating device the most according to claim 1, it is characterised in that described thermoelectricity dissipates
Thermal includes the many groups of described P-type silicon through holes being sequentially connected with, described second metallic silicon through hole and described
N-type silicon through hole.
Thermoelectric radiating device the most according to claim 3, it is characterised in that described many groups are suitable
The P-type silicon through hole of secondary connection, the second metallic silicon through hole and N-type silicon through hole are around described electronic device cloth
Put.
Thermoelectric radiating device the most according to claim 1, it is characterised in that described bottom core
The bottom of sheet is provided with redistribution layer, described N-type silicon through hole and the 4th metallic silicon through hole by described heavy
Distribution layer is interconnected.
Thermoelectric radiating device the most according to claim 1, it is characterised in that described silicon through hole
Top be provided with pad.
Thermoelectric radiating device the most according to claim 1, it is characterised in that described P-type silicon
Through hole, described second metallic silicon through hole and described N-type silicon through hole sequentially pass through soldered ball and connect, and described
First metallic silicon through hole, described 3rd metallic silicon through hole and described 4th metallic silicon through hole sequentially pass through weldering
Ball connects.
Thermoelectric radiating device the most according to claim 1, it is characterised in that described first gold medal
Belong to silicon through hole, described second metallic silicon through hole, described 3rd metallic silicon through hole and described 4th metallic silicon
The packing material of through hole is copper.
Thermoelectric radiating device the most according to claim 1, it is characterised in that described P-type silicon
The packing material of through hole and described N-type silicon through hole be Tellurobismuthite., Sb2Te3, Bi2Te3, PbTe, SiGe,
Crystal phonon glasses or nano material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210422441.1A CN103794581B (en) | 2012-10-29 | 2012-10-29 | A kind of thermoelectric radiating device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210422441.1A CN103794581B (en) | 2012-10-29 | 2012-10-29 | A kind of thermoelectric radiating device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103794581A CN103794581A (en) | 2014-05-14 |
| CN103794581B true CN103794581B (en) | 2016-12-21 |
Family
ID=50670112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210422441.1A Active CN103794581B (en) | 2012-10-29 | 2012-10-29 | A kind of thermoelectric radiating device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103794581B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9559283B2 (en) | 2015-03-30 | 2017-01-31 | International Business Machines Corporation | Integrated circuit cooling using embedded peltier micro-vias in substrate |
| US9941458B2 (en) | 2015-03-30 | 2018-04-10 | International Business Machines Corporation | Integrated circuit cooling using embedded peltier micro-vias in substrate |
| US11054597B2 (en) * | 2018-04-12 | 2021-07-06 | Rockley Photonics Limited | Electro-optical package and method of fabrication |
| KR20220048695A (en) | 2020-10-13 | 2022-04-20 | 삼성전자주식회사 | Semiconductor chip, and semiconductor package having the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764109A (en) * | 2008-12-22 | 2010-06-30 | 台湾积体电路制造股份有限公司 | Thermoelectric cooler for semiconductor devices with tsv |
| CN102543911A (en) * | 2010-12-21 | 2012-07-04 | 财团法人工业技术研究院 | Semiconductor device with a plurality of semiconductor chips |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005228915A (en) * | 2004-02-13 | 2005-08-25 | Toshiaki Eto | Separated peltier system |
| US8232137B2 (en) * | 2009-12-10 | 2012-07-31 | Intersil Americas Inc. | Heat conduction for chip stacks and 3-D circuits |
-
2012
- 2012-10-29 CN CN201210422441.1A patent/CN103794581B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764109A (en) * | 2008-12-22 | 2010-06-30 | 台湾积体电路制造股份有限公司 | Thermoelectric cooler for semiconductor devices with tsv |
| CN102543911A (en) * | 2010-12-21 | 2012-07-04 | 财团法人工业技术研究院 | Semiconductor device with a plurality of semiconductor chips |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103794581A (en) | 2014-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7851905B2 (en) | Microelectronic package and method of cooling an interconnect feature in same | |
| Adams et al. | Active peltier coolers based on correlated and magnon-drag metals | |
| US9620700B2 (en) | Wafer scale thermoelectric energy harvester | |
| US8866309B2 (en) | Chip package structure | |
| US20050279104A1 (en) | Thermoelectric module | |
| CN101859867A (en) | Thermoelectric element | |
| US10224474B2 (en) | Wafer scale thermoelectric energy harvester having interleaved, opposing thermoelectric legs and manufacturing techniques therefor | |
| CN103794581B (en) | A kind of thermoelectric radiating device | |
| US20120145209A1 (en) | Thermoelectric element and thermoelectric module including the same | |
| US9960336B2 (en) | Wafer scale thermoelectric energy harvester having trenches for capture of eutectic material | |
| JP2006521025A5 (en) | ||
| KR20120080820A (en) | Thermoelectric module | |
| CN108807451A (en) | Wafer level thermoelectric energy collector | |
| US8664509B2 (en) | Thermoelectric apparatus and method of fabricating the same | |
| US9755130B2 (en) | On-chip thermoelectric generator | |
| CN101764109B (en) | Thermoelectric cooler for semiconductor devices with tsv | |
| KR102510123B1 (en) | Thermoelectric element | |
| JP2015076607A (en) | Semiconductor chip structure | |
| JP5347886B2 (en) | Three-dimensional semiconductor device and method for cooling three-dimensional semiconductor device | |
| US20090007954A1 (en) | Temperature differential panel | |
| US20180226559A1 (en) | Thermoelectric conversion device | |
| KR102456680B1 (en) | Thermoelectric element | |
| KR101068647B1 (en) | Thermoelectric energy conversion module having spring structure | |
| CN106992244B (en) | Thermoelectric conversion device and thermoelectric converter | |
| CN106784278B (en) | Thermoelectric conversion device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |